sys/src/9/pc/ether82543gc.c

   1 /*
   2  * Intel RS-82543GC Gigabit Ethernet Controller
   3  * as found on the Intel PRO/1000[FT] Server Adapter.
   4  * The older non-[FT] cards use the 82542 (LSI L2A1157) chip; no attempt
   5  * is made to handle the older chip although it should be possible.
   6  * The datasheet is not very clear about running on a big-endian system
   7  * and this driver assumes little-endian throughout.
   8  * To do:
   9  *      GMII/MII
  10  *      receive tuning
  11  *      transmit tuning
  12  */
  13 #include "u.h"
  14 #include "../port/lib.h"
  15 #include "mem.h"
  16 #include "dat.h"
  17 #include "fns.h"
  18 #include "io.h"
  19 #include "../port/error.h"
  20 #include "../port/netif.h"
  21 #include "../port/etherif.h"
  22
  23 enum {
  24         Ctrl            = 0x00000000,   /* Device Control */
  25         Status          = 0x00000008,   /* Device Status */
  26         Eecd            = 0x00000010,   /* EEPROM/Flash Control/Data */
  27         Ctrlext         = 0x00000018,   /* Extended Device Control */
  28         Mdic            = 0x00000020,   /* MDI Control */
  29         Fcal            = 0x00000028,   /* Flow Control Address Low */
  30         Fcah            = 0x0000002C,   /* Flow Control Address High */
  31         Fct             = 0x00000030,   /* Flow Control Type */
  32         Icr             = 0x000000C0,   /* Interrupt Cause Read */
  33         Ics             = 0x000000C8,   /* Interrupt Cause Set */
  34         Ims             = 0x000000D0,   /* Interrupt Mask Set/Read */
  35         Imc             = 0x000000D8,   /* Interrupt mask Clear */
  36         Rctl            = 0x00000100,   /* Receive Control */
  37         Fcttv           = 0x00000170,   /* Flow Control Transmit Timer Value */
  38         Txcw            = 0x00000178,   /* Transmit configuration word reg. */
  39         Rxcw            = 0x00000180,   /* Receive configuration word reg. */
  40         Tctl            = 0x00000400,   /* Transmit Control */
  41         Tipg            = 0x00000410,   /* Transmit IPG */
  42         Tbt             = 0x00000448,   /* Transmit Burst Timer */
  43         Ait             = 0x00000458,   /* Adaptive IFS Throttle */
  44         Fcrtl           = 0x00002160,   /* Flow Control RX Threshold Low */
  45         Fcrth           = 0x00002168,   /* Flow Control Rx Threshold High */
  46         Rdfh            = 0x00002410,   /* Receive data fifo head */
  47         Rdft            = 0x00002418,   /* Receive data fifo tail */
  48         Rdfhs           = 0x00002420,   /* Receive data fifo head saved */
  49         Rdfts           = 0x00002428,   /* Receive data fifo tail saved */
  50         Rdfpc           = 0x00002430,   /* Receive data fifo packet count */
  51         Rdbal           = 0x00002800,   /* Rdesc Base Address Low */
  52         Rdbah           = 0x00002804,   /* Rdesc Base Address High */
  53         Rdlen           = 0x00002808,   /* Receive Descriptor Length */
  54         Rdh             = 0x00002810,   /* Receive Descriptor Head */
  55         Rdt             = 0x00002818,   /* Receive Descriptor Tail */
  56         Rdtr            = 0x00002820,   /* Receive Descriptor Timer Ring */
  57         Rxdctl          = 0x00002828,   /* Receive Descriptor Control */
  58         Txdmac          = 0x00003000,   /* Transfer DMA Control */
  59         Ett             = 0x00003008,   /* Early Transmit Control */
  60         Tdfh            = 0x00003410,   /* Transmit data fifo head */
  61         Tdft            = 0x00003418,   /* Transmit data fifo tail */
  62         Tdfhs           = 0x00003420,   /* Transmit data Fifo Head saved */
  63         Tdfts           = 0x00003428,   /* Transmit data fifo tail saved */
  64         Tdfpc           = 0x00003430,   /* Trasnmit data Fifo packet count */
  65         Tdbal           = 0x00003800,   /* Tdesc Base Address Low */
  66         Tdbah           = 0x00003804,   /* Tdesc Base Address High */
  67         Tdlen           = 0x00003808,   /* Transmit Descriptor Length */
  68         Tdh             = 0x00003810,   /* Transmit Descriptor Head */
  69         Tdt             = 0x00003818,   /* Transmit Descriptor Tail */
  70         Tidv            = 0x00003820,   /* Transmit Interrupt Delay Value */
  71         Txdctl          = 0x00003828,   /* Transmit Descriptor Control */
  72
  73         Statistics      = 0x00004000,   /* Start of Statistics Area */
  74         Gorcl           = 0x88/4,       /* Good Octets Received Count */
  75         Gotcl           = 0x90/4,       /* Good Octets Transmitted Count */
  76         Torl            = 0xC0/4,       /* Total Octets Received */
  77         Totl            = 0xC8/4,       /* Total Octets Transmitted */
  78         Nstatistics     = 64,
  79
  80         Rxcsum          = 0x00005000,   /* Receive Checksum Control */
  81         Mta             = 0x00005200,   /* Multicast Table Array */
  82         Ral             = 0x00005400,   /* Receive Address Low */
  83         Rah             = 0x00005404,   /* Receive Address High */
  84 };
  85
  86 enum {                                  /* Ctrl */
  87         Bem             = 0x00000002,   /* Big Endian Mode */
  88         Prior           = 0x00000004,   /* Priority on the PCI bus */
  89         Lrst            = 0x00000008,   /* Link Reset */
  90         Asde            = 0x00000020,   /* Auto-Speed Detection Enable */
  91         Slu             = 0x00000040,   /* Set Link Up */
  92         Ilos            = 0x00000080,   /* Invert Loss of Signal (LOS) */
  93         Frcspd          = 0x00000800,   /* Force Speed */
  94         Frcdplx         = 0x00001000,   /* Force Duplex */
  95         Swdpinslo       = 0x003C0000,   /* Software Defined Pins - lo nibble */
  96         Swdpin0         = 0x00040000,
  97         Swdpin1         = 0x00080000,
  98         Swdpin2         = 0x00100000,
  99         Swdpin3         = 0x00200000,
 100         Swdpiolo        = 0x03C00000,   /* Software Defined I/O Pins */
 101         Swdpio0         = 0x00400000,
 102         Swdpio1         = 0x00800000,
 103         Swdpio2         = 0x01000000,
 104         Swdpio3         = 0x02000000,
 105         Devrst          = 0x04000000,   /* Device Reset */
 106         Rfce            = 0x08000000,   /* Receive Flow Control Enable */
 107         Tfce            = 0x10000000,   /* Transmit Flow Control Enable */
 108         Vme             = 0x40000000,   /* VLAN Mode Enable */
 109 };
 110
 111 enum {                                  /* Status */
 112         Lu              = 0x00000002,   /* Link Up */
 113         Tckok           = 0x00000004,   /* Transmit clock is running */
 114         Rbcok           = 0x00000008,   /* Receive clock is running */
 115         Txoff           = 0x00000010,   /* Transmission Paused */
 116         Tbimode         = 0x00000020,   /* TBI Mode Indication */
 117         SpeedMASK       = 0x000000C0,
 118         Speed10         = 0x00000000,   /* 10Mb/s */
 119         Speed100        = 0x00000040,   /* 100Mb/s */
 120         Speed1000       = 0x00000080,   /* 1000Mb/s */
 121         Mtxckok         = 0x00000400,   /* MTX clock is running */
 122         Pci66           = 0x00000800,   /* PCI Bus speed indication */
 123         Bus64           = 0x00001000,   /* PCI Bus width indication */
 124 };
 125
 126 enum {                                  /* Ctrl and Status */
 127         Fd              = 0x00000001,   /* Full-Duplex */
 128         AsdvMASK        = 0x00000300,
 129         Asdv10          = 0x00000000,   /* 10Mb/s */
 130         Asdv100         = 0x00000100,   /* 100Mb/s */
 131         Asdv1000        = 0x00000200,   /* 1000Mb/s */
 132 };
 133
 134 enum {                                  /* Eecd */
 135         Sk              = 0x00000001,   /* Clock input to the EEPROM */
 136         Cs              = 0x00000002,   /* Chip Select */
 137         Di              = 0x00000004,   /* Data Input to the EEPROM */
 138         Do              = 0x00000008,   /* Data Output from the EEPROM */
 139 };
 140
 141 enum {                                  /* Ctrlext */
 142         Gpien           = 0x0000000F,   /* General Purpose Interrupt Enables */
 143         Swdpinshi       = 0x000000F0,   /* Software Defined Pins - hi nibble */
 144         Swdpiohi        = 0x00000F00,   /* Software Defined Pins - I or O */
 145         Asdchk          = 0x00001000,   /* ASD Check */
 146         Eerst           = 0x00002000,   /* EEPROM Reset */
 147         Ips             = 0x00004000,   /* Invert Power State */
 148         Spdbyps         = 0x00008000,   /* Speed Select Bypass */
 149 };
 150
 151 enum {                                  /* EEPROM content offsets */
 152         Ea              = 0x00,         /* Ethernet Address */
 153         Cf              = 0x03,         /* Compatibility Field */
 154         Pba             = 0x08,         /* Printed Board Assembly number */
 155         Icw1            = 0x0A,         /* Initialization Control Word 1 */
 156         Sid             = 0x0B,         /* Subsystem ID */
 157         Svid            = 0x0C,         /* Subsystem Vendor ID */
 158         Did             = 0x0D,         /* Device ID */
 159         Vid             = 0x0E,         /* Vendor ID */
 160         Icw2            = 0x0F,         /* Initialization Control Word 2 */
 161 };
 162
 163 enum {                                  /* Mdic */
 164         MDIdMASK        = 0x0000FFFF,   /* Data */
 165         MDIdSHIFT       = 0,
 166         MDIrMASK        = 0x001F0000,   /* PHY Register Address */
 167         MDIrSHIFT       = 16,
 168         MDIpMASK        = 0x03E00000,   /* PHY Address */
 169         MDIpSHIFT       = 21,
 170         MDIwop          = 0x04000000,   /* Write Operation */
 171         MDIrop          = 0x08000000,   /* Read Operation */
 172         MDIready        = 0x10000000,   /* End of Transaction */
 173         MDIie           = 0x20000000,   /* Interrupt Enable */
 174         MDIe            = 0x40000000,   /* Error */
 175 };
 176
 177 enum {                                  /* Icr, Ics, Ims, Imc */
 178         Txdw            = 0x00000001,   /* Transmit Descriptor Written Back */
 179         Txqe            = 0x00000002,   /* Transmit Queue Empty */
 180         Lsc             = 0x00000004,   /* Link Status Change */
 181         Rxseq           = 0x00000008,   /* Receive Sequence Error */
 182         Rxdmt0          = 0x00000010,   /* Rdesc Minimum Threshold Reached */
 183         Rxo             = 0x00000040,   /* Receiver Overrun */
 184         Rxt0            = 0x00000080,   /* Receiver Timer Interrupt */
 185         Mdac            = 0x00000200,   /* MDIO Access Completed */
 186         Rxcfg           = 0x00000400,   /* Receiving /C/ ordered sets */
 187         Gpi0            = 0x00000800,   /* General Purpose Interrupts */
 188         Gpi1            = 0x00001000,
 189         Gpi2            = 0x00002000,
 190         Gpi3            = 0x00004000,
 191 };
 192
 193 enum {                                  /* Txcw */
 194         Ane             = 0x80000000,   /* Autonegotiate enable */
 195         Np              = 0x00008000,   /* Next Page */
 196         As              = 0x00000100,   /* Asymmetric Flow control desired */
 197         Ps              = 0x00000080,   /* Pause supported */
 198         Hd              = 0x00000040,   /* Half duplex supported */
 199         TxcwFd          = 0x00000020,   /* Full Duplex supported */
 200 };
 201
 202 enum {                                  /* Rxcw */
 203         Rxword          = 0x0000FFFF,   /* Data from auto-negotiation process */
 204         Rxnocarrier     = 0x04000000,   /* Carrier Sense indication */
 205         Rxinvalid       = 0x08000000,   /* Invalid Symbol during configuration */
 206         Rxchange        = 0x10000000,   /* Change to the Rxword indication */
 207         Rxconfig        = 0x20000000,   /* /C/ order set reception indication */
 208         Rxsync          = 0x40000000,   /* Lost bit synchronization indication */
 209         Anc             = 0x80000000,   /* Auto Negotiation Complete */
 210 };
 211
 212 enum {                                  /* Rctl */
 213         Rrst            = 0x00000001,   /* Receiver Software Reset */
 214         Ren             = 0x00000002,   /* Receiver Enable */
 215         Sbp             = 0x00000004,   /* Store Bad Packets */
 216         Upe             = 0x00000008,   /* Unicast Promiscuous Enable */
 217         Mpe             = 0x00000010,   /* Multicast Promiscuous Enable */
 218         Lpe             = 0x00000020,   /* Long Packet Reception Enable */
 219         LbmMASK         = 0x000000C0,   /* Loopback Mode */
 220         LbmOFF          = 0x00000000,   /* No Loopback */
 221         LbmTBI          = 0x00000040,   /* TBI Loopback */
 222         LbmMII          = 0x00000080,   /* GMII/MII Loopback */
 223         LbmXCVR         = 0x000000C0,   /* Transceiver Loopback */
 224         RdtmsMASK       = 0x00000300,   /* Rdesc Minimum Threshold Size */
 225         RdtmsHALF       = 0x00000000,   /* Threshold is 1/2 Rdlen */
 226         RdtmsQUARTER    = 0x00000100,   /* Threshold is 1/4 Rdlen */
 227         RdtmsEIGHTH     = 0x00000200,   /* Threshold is 1/8 Rdlen */
 228         MoMASK          = 0x00003000,   /* Multicast Offset */
 229         Bam             = 0x00008000,   /* Broadcast Accept Mode */
 230         BsizeMASK       = 0x00030000,   /* Receive Buffer Size */
 231         Bsize2048       = 0x00000000,   /* Bsex = 0 */
 232         Bsize1024       = 0x00010000,   /* Bsex = 0 */
 233         Bsize512        = 0x00020000,   /* Bsex = 0 */
 234         Bsize256        = 0x00030000,   /* Bsex = 0 */
 235         Bsize16384      = 0x00010000,   /* Bsex = 1 */
 236         Vfe             = 0x00040000,   /* VLAN Filter Enable */
 237         Cfien           = 0x00080000,   /* Canonical Form Indicator Enable */
 238         Cfi             = 0x00100000,   /* Canonical Form Indicator value */
 239         Dpf             = 0x00400000,   /* Discard Pause Frames */
 240         Pmcf            = 0x00800000,   /* Pass MAC Control Frames */
 241         Bsex            = 0x02000000,   /* Buffer Size Extension */
 242         Secrc           = 0x04000000,   /* Strip CRC from incoming packet */
 243 };
 244
 245 enum {                                  /* Tctl */
 246         Trst            = 0x00000001,   /* Transmitter Software Reset */
 247         Ten             = 0x00000002,   /* Transmit Enable */
 248         Psp             = 0x00000008,   /* Pad Short Packets */
 249         CtMASK          = 0x00000FF0,   /* Collision Threshold */
 250         CtSHIFT         = 4,
 251         ColdMASK        = 0x003FF000,   /* Collision Distance */
 252         ColdSHIFT       = 12,
 253         Swxoff          = 0x00400000,   /* Sofware XOFF Transmission */
 254         Pbe             = 0x00800000,   /* Packet Burst Enable */
 255         Rtlc            = 0x01000000,   /* Re-transmit on Late Collision */
 256         Nrtu            = 0x02000000,   /* No Re-transmit on Underrrun */
 257 };
 258
 259 enum {                                  /* [RT]xdctl */
 260         PthreshMASK     = 0x0000003F,   /* Prefetch Threshold */
 261         PthreshSHIFT    = 0,
 262         HthreshMASK     = 0x00003F00,   /* Host Threshold */
 263         HthreshSHIFT    = 8,
 264         WthreshMASK     = 0x003F0000,   /* Writeback Threshold */
 265         WthreshSHIFT    = 16,
 266         Gran            = 0x00000000,   /* Granularity */
 267         RxGran          = 0x01000000,   /* Granularity */
 268 };
 269
 270 enum {                                  /* Rxcsum */
 271         PcssMASK        = 0x000000FF,   /* Packet Checksum Start */
 272         PcssSHIFT       = 0,
 273         Ipofl           = 0x00000100,   /* IP Checksum Off-load Enable */
 274         Tuofl           = 0x00000200,   /* TCP/UDP Checksum Off-load Enable */
 275 };
 276
 277 enum {                                  /* Receive Delay Timer Ring */
 278         Fpd             = 0x80000000,   /* Flush partial Descriptor Block */
 279 };
 280
 281 typedef struct Rdesc {                  /* Receive Descriptor */
 282         uint    addr[2];
 283         ushort  length;
 284         ushort  checksum;
 285         uchar   status;
 286         uchar   errors;
 287         ushort  special;
 288 } Rdesc;
 289
 290 enum {                                  /* Rdesc status */
 291         Rdd             = 0x01,         /* Descriptor Done */
 292         Reop            = 0x02,         /* End of Packet */
 293         Ixsm            = 0x04,         /* Ignore Checksum Indication */
 294         Vp              = 0x08,         /* Packet is 802.1Q (matched VET) */
 295         Tcpcs           = 0x20,         /* TCP Checksum Calculated on Packet */
 296         Ipcs            = 0x40,         /* IP Checksum Calculated on Packet */
 297         Pif             = 0x80,         /* Passed in-exact filter */
 298 };
 299
 300 enum {                                  /* Rdesc errors */
 301         Ce              = 0x01,         /* CRC Error or Alignment Error */
 302         Se              = 0x02,         /* Symbol Error */
 303         Seq             = 0x04,         /* Sequence Error */
 304         Cxe             = 0x10,         /* Carrier Extension Error */
 305         Tcpe            = 0x20,         /* TCP/UDP Checksum Error */
 306         Ipe             = 0x40,         /* IP Checksum Error */
 307         Rxe             = 0x80,         /* RX Data Error */
 308 };
 309
 310 typedef struct Tdesc {                  /* Legacy+Normal Transmit Descriptor */
 311         uint    addr[2];
 312         uint    control;                /* varies with descriptor type */
 313         uint    status;                 /* varies with descriptor type */
 314 } Tdesc;
 315
 316 enum {                                  /* Tdesc control */
 317         CsoMASK         = 0x00000F00,   /* Checksum Offset */
 318         CsoSHIFT        = 16,
 319         Teop            = 0x01000000,   /* End of Packet */
 320         Ifcs            = 0x02000000,   /* Insert FCS */
 321         Ic              = 0x04000000,   /* Insert Checksum (Dext == 0) */
 322         Tse             = 0x04000000,   /* TCP Segmentaion Enable (Dext == 1) */
 323         Rs              = 0x08000000,   /* Report Status */
 324         Rps             = 0x10000000,   /* Report Status Sent */
 325         Dext            = 0x20000000,   /* Extension (!legacy) */
 326         Vle             = 0x40000000,   /* VLAN Packet Enable */
 327         Ide             = 0x80000000,   /* Interrupt Delay Enable */
 328 };
 329
 330 enum {                                  /* Tdesc status */
 331         Tdd             = 0x00000001,   /* Descriptor Done */
 332         Ec              = 0x00000002,   /* Excess Collisions */
 333         Lc              = 0x00000004,   /* Late Collision */
 334         Tu              = 0x00000008,   /* Transmit Underrun */
 335         CssMASK         = 0x0000FF00,   /* Checksum Start Field */
 336         CssSHIFT        = 8,
 337 };
 338
 339 enum {
 340         Nrdesc          = 256,          /* multiple of 8 */
 341         Ntdesc          = 256,          /* multiple of 8 */
 342         Nblocks         = 4098,         /* total number of blocks to use */
 343
 344         SBLOCKSIZE      = 2048,
 345         JBLOCKSIZE      = 16384,
 346
 347         NORMAL          = 1,
 348         JUMBO           = 2,
 349 };
 350
 351 typedef struct Ctlr Ctlr;
 352 typedef struct Ctlr {
 353         int     port;
 354         Pcidev* pcidev;
 355         Ctlr*   next;
 356         int     active;
 357         int     started;
 358         int     id;
 359         ushort  eeprom[0x40];
 360
 361         int*    nic;
 362         int     im;                     /* interrupt mask */
 363
 364         Lock    slock;
 365         uint    statistics[Nstatistics];
 366
 367         Lock    rdlock;
 368         Rdesc*  rdba;                   /* receive descriptor base address */
 369         Block*  rb[Nrdesc];             /* receive buffers */
 370         int     rdh;                    /* receive descriptor head */
 371         int     rdt;                    /* receive descriptor tail */
 372         Block** freehead;               /* points to long or short head */
 373
 374         Lock    tdlock;
 375         Tdesc*  tdba;                   /* transmit descriptor base address */
 376         Block*  tb[Ntdesc];             /* transmit buffers */
 377         int     tdh;                    /* transmit descriptor head */
 378         int     tdt;                    /* transmit descriptor tail */
 379         int     txstalled;              /* count of times unable to send */
 380
 381         int     txcw;
 382         int     fcrtl;
 383         int     fcrth;
 384
 385         ulong   multimask[128];         /* bit mask for multicast addresses */
 386 } Ctlr;
 387
 388 static Ctlr* gc82543ctlrhead;
 389 static Ctlr* gc82543ctlrtail;
 390
 391 static Lock freelistlock;
 392 static Block* freeShortHead;
 393 static Block* freeJumboHead;
 394
 395 #define csr32r(c, r)    (*((c)->nic+((r)/4)))
 396 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
 397
 398 static void gc82543watchdog(void* arg);
 399
 400 static void
 401 gc82543attach(Ether* edev)
 402 {
 403         int ctl;
 404         Ctlr *ctlr;
 405         char name[KNAMELEN];
 406
 407         /*
 408          * To do here:
 409          *      one-time stuff;
 410          *              adjust queue length depending on speed;
 411          *              flow control.
 412          *      more needed here...
 413          */
 414         ctlr = edev->ctlr;
 415         lock(&ctlr->slock);
 416         if(ctlr->started == 0){
 417                 ctlr->started = 1;
 418                 snprint(name, KNAMELEN, "#l%d82543", edev->ctlrno);
 419                 kproc(name, gc82543watchdog, edev);
 420         }
 421         unlock(&ctlr->slock);
 422
 423         ctl = csr32r(ctlr, Rctl)|Ren;
 424         csr32w(ctlr, Rctl, ctl);
 425         ctl = csr32r(ctlr, Tctl)|Ten;
 426         csr32w(ctlr, Tctl, ctl);
 427
 428         csr32w(ctlr, Ims, ctlr->im);
 429 }
 430
 431 static char* statistics[Nstatistics] = {
 432         "CRC Error",
 433         "Alignment Error",
 434         "Symbol Error",
 435         "RX Error",
 436         "Missed Packets",
 437         "Single Collision",
 438         "Excessive Collisions",
 439         "Multiple Collision",
 440         "Late Collisions",
 441         nil,
 442         "Collision",
 443         "Transmit Underrun",
 444         "Defer",
 445         "Transmit - No CRS",
 446         "Sequence Error",
 447         "Carrier Extension Error",
 448         "Receive Error Length",
 449         nil,
 450         "XON Received",
 451         "XON Transmitted",
 452         "XOFF Received",
 453         "XOFF Transmitted",
 454         "FC Received Unsupported",
 455         "Packets Received (64 Bytes)",
 456         "Packets Received (65-127 Bytes)",
 457         "Packets Received (128-255 Bytes)",
 458         "Packets Received (256-511 Bytes)",
 459         "Packets Received (512-1023 Bytes)",
 460         "Packets Received (1024-1522 Bytes)",
 461         "Good Packets Received",
 462         "Broadcast Packets Received",
 463         "Multicast Packets Received",
 464         "Good Packets Transmitted",
 465         nil,
 466         "Good Octets Received",
 467         nil,
 468         "Good Octets Transmitted",
 469         nil,
 470         nil,
 471         nil,
 472         "Receive No Buffers",
 473         "Receive Undersize",
 474         "Receive Fragment",
 475         "Receive Oversize",
 476         "Receive Jabber",
 477         nil,
 478         nil,
 479         nil,
 480         "Total Octets Received",
 481         nil,
 482         "Total Octets Transmitted",
 483         nil,
 484         "Total Packets Received",
 485         "Total Packets Transmitted",
 486         "Packets Transmitted (64 Bytes)",
 487         "Packets Transmitted (65-127 Bytes)",
 488         "Packets Transmitted (128-255 Bytes)",
 489         "Packets Transmitted (256-511 Bytes)",
 490         "Packets Transmitted (512-1023 Bytes)",
 491         "Packets Transmitted (1024-1522 Bytes)",
 492         "Multicast Packets Transmitted",
 493         "Broadcast Packets Transmitted",
 494         "TCP Segmentation Context Transmitted",
 495         "TCP Segmentation Context Fail",
 496 };
 497
 498 static long
 499 gc82543ifstat(Ether* edev, void* a, long n, ulong offset)
 500 {
 501         Ctlr *ctlr;
 502         char *p, *s;
 503         int i, l, r;
 504         uvlong tuvl, ruvl;
 505
 506         p = smalloc(READSTR);
 507
 508         ctlr = edev->ctlr;
 509         lock(&ctlr->slock);
 510         l = 0;
 511         for(i = 0; i < Nstatistics; i++){
 512                 r = csr32r(ctlr, Statistics+i*4);
 513                 if((s = statistics[i]) == nil)
 514                         continue;
 515                 switch(i){
 516                 case Gorcl:
 517                 case Gotcl:
 518                 case Torl:
 519                 case Totl:
 520                         ruvl = r;
 521                         ruvl += ((uvlong)csr32r(ctlr, Statistics+(i+1)*4))<<32;
 522                         tuvl = ruvl;
 523                         tuvl += ctlr->statistics[i];
 524                         tuvl += ((uvlong)ctlr->statistics[i+1])<<32;
 525                         if(tuvl == 0)
 526                                 continue;
 527                         ctlr->statistics[i] = tuvl;
 528                         ctlr->statistics[i+1] = tuvl>>32;
 529                         l += snprint(p+l, READSTR-l, "%s: %llud %llud\n",
 530                                 s, tuvl, ruvl);
 531                         i++;
 532                         break;
 533
 534                 default:
 535                         ctlr->statistics[i] += r;
 536                         if(ctlr->statistics[i] == 0)
 537                                 continue;
 538                         l += snprint(p+l, READSTR-l, "%s: %ud %ud\n",
 539                                 s, ctlr->statistics[i], r);
 540                         break;
 541                 }
 542         }
 543
 544         l += snprint(p+l, READSTR-l, "eeprom:");
 545         for(i = 0; i < 0x40; i++){
 546                 if(i && ((i & 0x07) == 0))
 547                         l += snprint(p+l, READSTR-l, "\n       ");
 548                 l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->eeprom[i]);
 549         }
 550
 551         snprint(p+l, READSTR-l, "\ntxstalled %d\n", ctlr->txstalled);
 552         n = readstr(offset, a, n, p);
 553         free(p);
 554         unlock(&ctlr->slock);
 555
 556         return n;
 557 }
 558
 559 static void
 560 gc82543promiscuous(void* arg, int on)
 561 {
 562         int rctl;
 563         Ctlr *ctlr;
 564         Ether *edev;
 565
 566         edev = arg;
 567         ctlr = edev->ctlr;
 568
 569         rctl = csr32r(ctlr, Rctl);
 570         rctl &= ~MoMASK;                /* make sure we're using bits 47:36 */
 571         if(on)
 572                 rctl |= Upe|Mpe;
 573         else
 574                 rctl &= ~(Upe|Mpe);
 575         csr32w(ctlr, Rctl, rctl);
 576 }
 577
 578 static void
 579 gc82543multicast(void* arg, uchar* addr, int on)
 580 {
 581         int bit, x;
 582         Ctlr *ctlr;
 583         Ether *edev;
 584
 585         edev = arg;
 586         ctlr = edev->ctlr;
 587         x = addr[5]>>1;
 588         bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
 589         if(on)
 590                 ctlr->multimask[x] |= 1<<bit;
 591         else
 592                 ctlr->multimask[x] &= ~(1<<bit);
 593
 594         csr32w(ctlr, Mta+x*4, ctlr->multimask[x]);
 595 }
 596
 597 static long
 598 gc82543ctl(Ether* edev, void* buf, long n)
 599 {
 600         Cmdbuf *cb;
 601         Ctlr *ctlr;
 602         int ctrl, i, r;
 603
 604         ctlr = edev->ctlr;
 605         if(ctlr == nil)
 606                 error(Enonexist);
 607
 608         lock(&ctlr->slock);
 609         r = 0;
 610         cb = parsecmd(buf, n);
 611         if(cb->nf < 2)
 612                 r = -1;
 613         else if(cistrcmp(cb->f[0], "auto") == 0){
 614                 ctrl = csr32r(ctlr, Ctrl);
 615                 if(cistrcmp(cb->f[1], "off") == 0){
 616                         csr32w(ctlr, Txcw, ctlr->txcw & ~Ane);
 617                         ctrl |= (Slu|Fd);
 618                         if(ctlr->txcw & As)
 619                                 ctrl |= Rfce;
 620                         if(ctlr->txcw & Ps)
 621                                 ctrl |= Tfce;
 622                         csr32w(ctlr, Ctrl, ctrl);
 623                 }
 624                 else if(cistrcmp(cb->f[1], "on") == 0){
 625                         csr32w(ctlr, Txcw, ctlr->txcw);
 626                         ctrl &= ~(Slu|Fd);
 627                         csr32w(ctlr, Ctrl, ctrl);
 628                 }
 629                 else
 630                         r = -1;
 631         }
 632         else if(cistrcmp(cb->f[0], "clear") == 0){
 633                 if(cistrcmp(cb->f[1], "stats") == 0){
 634                         for(i = 0; i < Nstatistics; i++)
 635                                 ctlr->statistics[i] = 0;
 636                 }
 637                 else
 638                         r = -1;
 639         }
 640         else
 641                 r = -1;
 642         unlock(&ctlr->slock);
 643
 644         free(cb);
 645         return (r == 0) ? n : r;
 646 }
 647
 648 static void
 649 gc82543txinit(Ctlr* ctlr)
 650 {
 651         int i;
 652         int tdsize;
 653         Block *bp, **bpp;
 654
 655         tdsize = ROUND(Ntdesc*sizeof(Tdesc), 4096);
 656
 657         if(ctlr->tdba == nil)
 658                 ctlr->tdba = xspanalloc(tdsize, 32, 0);
 659
 660         for(i = 0; i < Ntdesc; i++){
 661                 bpp = &ctlr->tb[i];
 662                 bp = *bpp;
 663                 if(bp != nil){
 664                         *bpp = nil;
 665                         freeb(bp);
 666                 }
 667                 memset(&ctlr->tdba[i], 0, sizeof(Tdesc));
 668         }
 669
 670         csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
 671         csr32w(ctlr, Tdbah, 0);
 672         csr32w(ctlr, Tdlen, Ntdesc*sizeof(Tdesc));
 673
 674         /*
 675          * set the ring head and tail pointers.
 676          */
 677         ctlr->tdh = 0;
 678         csr32w(ctlr, Tdh, ctlr->tdh);
 679         ctlr->tdt = 0;
 680         csr32w(ctlr, Tdt, ctlr->tdt);
 681
 682         csr32w(ctlr, Tipg, (6<<20)|(8<<10)|6);
 683         csr32w(ctlr, Tidv, 128);
 684         csr32w(ctlr, Ait, 0);
 685         csr32w(ctlr, Txdmac, 0);
 686         csr32w(ctlr, Txdctl, Gran|(4<<WthreshSHIFT)|(1<<HthreshSHIFT)|16);
 687         csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(6<<ColdSHIFT));
 688
 689         ctlr->im |= Txdw;
 690 }
 691
 692 static void
 693 gc82543transmit(Ether* edev)
 694 {
 695         Block *bp, **bpp;
 696         Ctlr *ctlr;
 697         Tdesc *tdesc;
 698         int tdh, tdt, s;
 699
 700         ctlr = edev->ctlr;
 701
 702         ilock(&ctlr->tdlock);
 703         tdh = ctlr->tdh;
 704         for(;;){
 705                 /*
 706                  * Free any completed packets
 707                  */
 708                 tdesc = &ctlr->tdba[tdh];
 709                 if(!(tdesc->status & Tdd))
 710                         break;
 711                 memset(tdesc, 0, sizeof(Tdesc));
 712                 bpp = &ctlr->tb[tdh];
 713                 bp = *bpp;
 714                 if(bp != nil){
 715                         *bpp = nil;
 716                         freeb(bp);
 717                 }
 718                 tdh = NEXT(tdh, Ntdesc);
 719         }
 720         ctlr->tdh = tdh;
 721         s = csr32r(ctlr, Status);
 722
 723         /*
 724          * Try to fill the ring back up
 725          * but only if link is up and transmission isn't paused.
 726          */
 727         if((s & (Txoff|Lu)) == Lu){
 728                 tdt = ctlr->tdt;
 729                 while(NEXT(tdt, Ntdesc) != tdh){
 730                         if((bp = qget(edev->oq)) == nil)
 731                                 break;
 732
 733                         tdesc = &ctlr->tdba[tdt];
 734                         tdesc->addr[0] = PCIWADDR(bp->rp);
 735                         tdesc->control = Ide|Rs|Ifcs|Teop|BLEN(bp);
 736                         ctlr->tb[tdt] = bp;
 737                         tdt = NEXT(tdt, Ntdesc);
 738                 }
 739
 740                 if(tdt != ctlr->tdt){
 741                         ctlr->tdt = tdt;
 742                         csr32w(ctlr, Tdt, tdt);
 743                 }
 744         }
 745         else
 746                 ctlr->txstalled++;
 747
 748         iunlock(&ctlr->tdlock);
 749 }
 750
 751 static Block *
 752 gc82543allocb(Ctlr* ctlr)
 753 {
 754         Block *bp;
 755
 756         ilock(&freelistlock);
 757         if((bp = *(ctlr->freehead)) != nil){
 758                 *(ctlr->freehead) = bp->next;
 759                 bp->next = nil;
 760         }
 761         iunlock(&freelistlock);
 762         return bp;
 763 }
 764
 765 static void
 766 gc82543replenish(Ctlr* ctlr)
 767 {
 768         int rdt;
 769         Block *bp;
 770         Rdesc *rdesc;
 771
 772         ilock(&ctlr->rdlock);
 773         rdt = ctlr->rdt;
 774         while(NEXT(rdt, Nrdesc) != ctlr->rdh){
 775                 rdesc = &ctlr->rdba[rdt];
 776                 if(ctlr->rb[rdt] == nil){
 777                         bp = gc82543allocb(ctlr);
 778                         if(bp == nil){
 779                                 iprint("no available buffers\n");
 780                                 break;
 781                         }
 782                         ctlr->rb[rdt] = bp;
 783                         rdesc->addr[0] = PCIWADDR(bp->rp);
 784                         rdesc->addr[1] = 0;
 785                 }
 786                 coherence();
 787                 rdesc->status = 0;
 788                 rdt = NEXT(rdt, Nrdesc);
 789         }
 790         ctlr->rdt = rdt;
 791         csr32w(ctlr, Rdt, rdt);
 792         iunlock(&ctlr->rdlock);
 793 }
 794
 795 static void
 796 gc82543rxinit(Ctlr* ctlr)
 797 {
 798         int rdsize, i;
 799
 800         csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF);
 801
 802         /*
 803          * Allocate the descriptor ring and load its
 804          * address and length into the NIC.
 805          */
 806         rdsize = ROUND(Nrdesc*sizeof(Rdesc), 4096);
 807         if(ctlr->rdba == nil)
 808                 ctlr->rdba = xspanalloc(rdsize, 32, 0);
 809         memset(ctlr->rdba, 0, rdsize);
 810
 811         ctlr->rdh = 0;
 812         ctlr->rdt = 0;
 813
 814         csr32w(ctlr, Rdtr, Fpd|64);
 815         csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
 816         csr32w(ctlr, Rdbah, 0);
 817         csr32w(ctlr, Rdlen, Nrdesc*sizeof(Rdesc));
 818         csr32w(ctlr, Rdh, 0);
 819         csr32w(ctlr, Rdt, 0);
 820         for(i = 0; i < Nrdesc; i++){
 821                 if(ctlr->rb[i] != nil){
 822                         freeb(ctlr->rb[i]);
 823                         ctlr->rb[i] = nil;
 824                 }
 825         }
 826         gc82543replenish(ctlr);
 827
 828         csr32w(ctlr, Rxdctl, RxGran|(8<<WthreshSHIFT)|(4<<HthreshSHIFT)|1);
 829         ctlr->im |= Rxt0|Rxo|Rxdmt0|Rxseq;
 830 }
 831
 832 static void
 833 gc82543recv(Ether* edev, int icr)
 834 {
 835         Block *bp;
 836         Ctlr *ctlr;
 837         Rdesc *rdesc;
 838         int rdh;
 839
 840         ctlr = edev->ctlr;
 841
 842         rdh = ctlr->rdh;
 843         for(;;){
 844                 rdesc = &ctlr->rdba[rdh];
 845
 846                 if(!(rdesc->status & Rdd))
 847                         break;
 848
 849                 if((rdesc->status & Reop) && rdesc->errors == 0){
 850                         bp = ctlr->rb[rdh];
 851                         ctlr->rb[rdh] = nil;
 852                         bp->wp += rdesc->length;
 853                         bp->next = nil;
 854                         etheriq(edev, bp, 1);
 855                 }
 856
 857                 if(ctlr->rb[rdh] != nil){
 858                         /* either non eop packet, or error */
 859                         freeb(ctlr->rb[rdh]);
 860                         ctlr->rb[rdh] = nil;
 861                 }
 862                 memset(rdesc, 0, sizeof(Rdesc));
 863                 coherence();
 864                 rdh = NEXT(rdh, Nrdesc);
 865         }
 866         ctlr->rdh = rdh;
 867
 868         if(icr & Rxdmt0)
 869                 gc82543replenish(ctlr);
 870 }
 871
 872 static void
 873 freegc82543short(Block *bp)
 874 {
 875         ilock(&freelistlock);
 876         /* reset read/write pointer to proper positions */
 877         bp->rp = bp->lim - ROUND(SBLOCKSIZE, BLOCKALIGN);
 878         bp->wp = bp->rp;
 879         bp->next = freeShortHead;
 880         freeShortHead = bp;
 881         iunlock(&freelistlock);
 882 }
 883
 884 static void
 885 freegc82532jumbo(Block *bp)
 886 {
 887         ilock(&freelistlock);
 888         /* reset read/write pointer to proper positions */
 889         bp->rp = bp->lim - ROUND(JBLOCKSIZE, BLOCKALIGN);
 890         bp->wp = bp->rp;
 891         bp->next = freeJumboHead;
 892         freeJumboHead = bp;
 893         iunlock(&freelistlock);
 894 }
 895
 896 static void
 897 linkintr(Ctlr* ctlr)
 898 {
 899         int ctrl;
 900
 901         ctrl = csr32r(ctlr, Ctrl);
 902
 903         if((ctrl & Swdpin1) ||
 904           ((csr32r(ctlr, Rxcw) & Rxconfig) && !(csr32r(ctlr, Txcw) & Ane))){
 905                 csr32w(ctlr, Txcw, ctlr->txcw);
 906                 ctrl &= ~(Slu|Fd|Frcdplx);
 907                 csr32w(ctlr, Ctrl, ctrl);
 908         }
 909 }
 910
 911 static void
 912 gc82543interrupt(Ureg*, void* arg)
 913 {
 914         Ctlr *ctlr;
 915         Ether *edev;
 916         int icr;
 917
 918         edev = arg;
 919         ctlr = edev->ctlr;
 920
 921         while((icr = csr32r(ctlr, Icr) & ctlr->im) != 0){
 922                 /*
 923                  * Link status changed.
 924                  */
 925                 if(icr & (Lsc|Rxseq))
 926                         linkintr(ctlr);
 927
 928                 /*
 929                  * Process recv buffers.
 930                  */
 931                 gc82543recv(edev, icr);
 932
 933                 /*
 934                  * Refill transmit ring and free packets.
 935                  */
 936                 gc82543transmit(edev);
 937         }
 938 }
 939
 940 static int
 941 gc82543init(Ether* edev)
 942 {
 943         int csr, i;
 944         Block *bp;
 945         Ctlr *ctlr;
 946
 947         ctlr = edev->ctlr;
 948
 949         /*
 950          * Allocate private buffer pool to use for receiving packets.
 951          */
 952         ilock(&freelistlock);
 953         if (ctlr->freehead == nil){
 954                 for(i = 0; i < Nblocks; i++){
 955                         bp = iallocb(SBLOCKSIZE);
 956                         if(bp != nil){
 957                                 bp->next = freeShortHead;
 958                                 bp->free = freegc82543short;
 959                                 freeShortHead = bp;
 960                         }
 961                         else{
 962                                 print("82543gc: no memory\n");
 963                                 break;
 964                         }
 965                 }
 966                 ctlr->freehead = &freeShortHead;
 967         }
 968         iunlock(&freelistlock);
 969
 970         /*
 971          * Set up the receive addresses.
 972          * There are 16 addresses. The first should be the MAC address.
 973          * The others are cleared and not marked valid (MS bit of Rah).
 974          */
 975         csr = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
 976         csr32w(ctlr, Ral, csr);
 977         csr = 0x80000000|(edev->ea[5]<<8)|edev->ea[4];
 978         csr32w(ctlr, Rah, csr);
 979         for(i = 1; i < 16; i++){
 980                 csr32w(ctlr, Ral+i*8, 0);
 981                 csr32w(ctlr, Rah+i*8, 0);
 982         }
 983
 984         /*
 985          * Clear the Multicast Table Array.
 986          * It's a 4096 bit vector accessed as 128 32-bit registers.
 987          */
 988         for(i = 0; i < 128; i++)
 989                 csr32w(ctlr, Mta+i*4, 0);
 990
 991         gc82543txinit(ctlr);
 992         gc82543rxinit(ctlr);
 993
 994         return 0;
 995 }
 996
 997 static int
 998 at93c46io(Ctlr* ctlr, char* op, int data)
 999 {
1000         char *lp, *p;
1001         int i, loop, eecd, r;
1002
1003         eecd = csr32r(ctlr, Eecd);
1004
1005         r = 0;
1006         loop = -1;
1007         lp = nil;
1008         for(p = op; *p != '\0'; p++){
1009                 switch(*p){
1010                 default:
1011                         return -1;
1012                 case ' ':
1013                         continue;
1014                 case ':':                       /* start of loop */
1015                         if(lp != nil){
1016                                 if(p != (lp+1) || loop != 7)
1017                                         return -1;
1018                                 lp = p;
1019                                 loop = 15;
1020                                 continue;
1021                         }
1022                         lp = p;
1023                         loop = 7;
1024                         continue;
1025                 case ';':                       /* end of loop */
1026                         if(lp == nil)
1027                                 return -1;
1028                         loop--;
1029                         if(loop >= 0)
1030                                 p = lp;
1031                         else
1032                                 lp = nil;
1033                         continue;
1034                 case 'C':                       /* assert clock */
1035                         eecd |= Sk;
1036                         break;
1037                 case 'c':                       /* deassert clock */
1038                         eecd &= ~Sk;
1039                         break;
1040                 case 'D':                       /* next bit in 'data' byte */
1041                         if(loop < 0)
1042                                 return -1;
1043                         if(data & (1<<loop))
1044                                 eecd |= Di;
1045                         else
1046                                 eecd &= ~Di;
1047                         break;
1048                 case 'O':                       /* collect data output */
1049                         i = (csr32r(ctlr, Eecd) & Do) != 0;
1050                         if(loop >= 0)
1051                                 r |= (i<<loop);
1052                         else
1053                                 r = i;
1054                         continue;
1055                 case 'I':                       /* assert data input */
1056                         eecd |= Di;
1057                         break;
1058                 case 'i':                       /* deassert data input */
1059                         eecd &= ~Di;
1060                         break;
1061                 case 'S':                       /* enable chip select */
1062                         eecd |= Cs;
1063                         break;
1064                 case 's':                       /* disable chip select */
1065                         eecd &= ~Cs;
1066                         break;
1067                 }
1068                 csr32w(ctlr, Eecd, eecd);
1069                 microdelay(1);
1070         }
1071         if(loop >= 0)
1072                 return -1;
1073         return r;
1074 }
1075
1076 static int
1077 at93c46r(Ctlr* ctlr)
1078 {
1079         ushort sum;
1080         int addr, data;
1081
1082         sum = 0;
1083         for(addr = 0; addr < 0x40; addr++){
1084                 /*
1085                  * Read a word at address 'addr' from the Atmel AT93C46
1086                  * 3-Wire Serial EEPROM or compatible. The EEPROM access is
1087                  * controlled by 4 bits in Eecd. See the AT93C46 datasheet
1088                  * for protocol details.
1089                  */
1090                 if(at93c46io(ctlr, "S ICc :DCc;", (0x02<<6)|addr) != 0)
1091                         break;
1092                 data = at93c46io(ctlr, "::COc;", 0);
1093                 at93c46io(ctlr, "sic", 0);
1094                 ctlr->eeprom[addr] = data;
1095                 sum += data;
1096         }
1097
1098         return sum;
1099 }
1100
1101 static void
1102 gc82543detach(Ctlr* ctlr)
1103 {
1104         /*
1105          * Perform a device reset to get the chip back to the
1106          * power-on state, followed by an EEPROM reset to read
1107          * the defaults for some internal registers.
1108          */
1109         csr32w(ctlr, Imc, ~0);
1110         csr32w(ctlr, Rctl, 0);
1111         csr32w(ctlr, Tctl, 0);
1112
1113         delay(10);
1114
1115         csr32w(ctlr, Ctrl, Devrst);
1116         while(csr32r(ctlr, Ctrl) & Devrst)
1117                 ;
1118
1119         csr32w(ctlr, Ctrlext, Eerst);
1120         while(csr32r(ctlr, Ctrlext) & Eerst)
1121                 ;
1122
1123         csr32w(ctlr, Imc, ~0);
1124         while(csr32r(ctlr, Icr))
1125                 ;
1126 }
1127
1128 static void
1129 gc82543checklink(Ctlr* ctlr)
1130 {
1131         int ctrl, status, rxcw;
1132
1133         ctrl = csr32r(ctlr, Ctrl);
1134         status = csr32r(ctlr, Status);
1135         rxcw = csr32r(ctlr, Rxcw);
1136
1137         if(!(status & Lu)){
1138                 if(!(ctrl & (Swdpin1|Slu)) && !(rxcw & Rxconfig)){
1139                         csr32w(ctlr, Txcw, ctlr->txcw & ~Ane);
1140                         ctrl |= (Slu|Fd);
1141                         if(ctlr->txcw & As)
1142                                 ctrl |= Rfce;
1143                         if(ctlr->txcw & Ps)
1144                                 ctrl |= Tfce;
1145                         csr32w(ctlr, Ctrl, ctrl);
1146                 }
1147         }
1148         else if((ctrl & Slu) && (rxcw & Rxconfig)){
1149                 csr32w(ctlr, Txcw, ctlr->txcw);
1150                 ctrl &= ~(Slu|Fd);
1151                 csr32w(ctlr, Ctrl, ctrl);
1152         }
1153 }
1154
1155 static void
1156 gc82543shutdown(Ether* ether)
1157 {
1158         gc82543detach(ether->ctlr);
1159 }
1160
1161 static int
1162 gc82543reset(Ctlr* ctlr)
1163 {
1164         int ctl;
1165         int te;
1166
1167         /*
1168          * Read the EEPROM, validate the checksum
1169          * then get the device back to a power-on state.
1170          */
1171         if(at93c46r(ctlr) != 0xBABA)
1172                 return -1;
1173
1174         gc82543detach(ctlr);
1175
1176         te = ctlr->eeprom[Icw2];
1177         if((te & 0x3000) == 0){
1178                 ctlr->fcrtl = 0x00002000;
1179                 ctlr->fcrth = 0x00004000;
1180                 ctlr->txcw = Ane|TxcwFd;
1181         }
1182         else if((te & 0x3000) == 0x2000){
1183                 ctlr->fcrtl = 0;
1184                 ctlr->fcrth = 0;
1185                 ctlr->txcw = Ane|TxcwFd|As;
1186         }
1187         else{
1188                 ctlr->fcrtl = 0x00002000;
1189                 ctlr->fcrth = 0x00004000;
1190                 ctlr->txcw = Ane|TxcwFd|As|Ps;
1191         }
1192
1193         csr32w(ctlr, Txcw, ctlr->txcw);
1194
1195         csr32w(ctlr, Ctrlext, (te & 0x00f0)<<4);
1196
1197         csr32w(ctlr, Tctl, csr32r(ctlr, Tctl)|(64<<ColdSHIFT));
1198
1199         te = ctlr->eeprom[Icw1];
1200         ctl = ((te & 0x01E0)<<17)|(te & 0x0010)<<3;
1201         csr32w(ctlr, Ctrl, ctl);
1202
1203         delay(10);
1204
1205         /*
1206          * Flow control - values from the datasheet.
1207          */
1208         csr32w(ctlr, Fcal, 0x00C28001);
1209         csr32w(ctlr, Fcah, 0x00000100);
1210         csr32w(ctlr, Fct, 0x00008808);
1211         csr32w(ctlr, Fcttv, 0x00000100);
1212
1213         csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1214         csr32w(ctlr, Fcrth, ctlr->fcrth);
1215
1216         ctlr->im = Lsc;
1217         gc82543checklink(ctlr);
1218
1219         return 0;
1220 }
1221
1222 static void
1223 gc82543watchdog(void* arg)
1224 {
1225         Ether *edev;
1226         Ctlr *ctlr;
1227
1228         edev = arg;
1229         while(waserror())
1230                 ;
1231         for(;;){
1232                 tsleep(&up->sleep, return0, 0, 1000);
1233                 ctlr = edev->ctlr;
1234                 if(ctlr == nil)
1235                         break;
1236
1237                 gc82543checklink(ctlr);
1238                 gc82543replenish(ctlr);
1239         }
1240         print("%s: exiting\n", up->text);
1241         pexit("disabled", 1);
1242 }
1243
1244 static void
1245 gc82543pci(void)
1246 {
1247         int cls;
1248         void *mem;
1249         Pcidev *p;
1250         Ctlr *ctlr;
1251
1252         p = nil;
1253         while(p = pcimatch(p, 0, 0)){
1254                 if(p->ccrb != 0x02 || p->ccru != 0)
1255                         continue;
1256
1257                 switch((p->did<<16)|p->vid){
1258                 case (0x1000<<16)|0x8086:       /* LSI L2A1157 (82542) */
1259                 case (0x1004<<16)|0x8086:       /* Intel PRO/1000 T */
1260                 case (0x1008<<16)|0x8086:       /* Intel PRO/1000 XT */
1261                 default:
1262                         continue;
1263                 case (0x1001<<16)|0x8086:       /* Intel PRO/1000 F */
1264                         break;
1265                 }
1266
1267                 ctlr = malloc(sizeof(Ctlr));
1268                 if(ctlr == nil){
1269                         print("82543gc: can't allocate memory\n");
1270                         continue;
1271                 }
1272                 mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
1273                 if(mem == 0){
1274                         print("82543gc: can't map %8.8luX\n", p->mem[0].bar);
1275                         free(ctlr);
1276                         continue;
1277                 }
1278                 cls = pcicfgr8(p, PciCLS);
1279                 switch(cls){
1280                 case 0x08:
1281                 case 0x10:
1282                         break;
1283                 default:
1284                         print("82543gc: p->cls %#ux, setting to 0x10\n", p->cls);
1285                         p->cls = 0x10;
1286                         pcicfgw8(p, PciCLS, p->cls);
1287                 }
1288                 ctlr->port = p->mem[0].bar & ~0x0F;
1289                 ctlr->pcidev = p;
1290                 ctlr->id = (p->did<<16)|p->vid;
1291                 ctlr->nic = mem;
1292
1293                 if(gc82543reset(ctlr)){
1294                         free(ctlr);
1295                         continue;
1296                 }
1297
1298                 if(gc82543ctlrhead != nil)
1299                         gc82543ctlrtail->next = ctlr;
1300                 else
1301                         gc82543ctlrhead = ctlr;
1302                 gc82543ctlrtail = ctlr;
1303         }
1304 }
1305
1306 static int
1307 gc82543pnp(Ether* edev)
1308 {
1309         int i;
1310         Ctlr *ctlr;
1311         uchar ea[Eaddrlen];
1312
1313         if(gc82543ctlrhead == nil)
1314                 gc82543pci();
1315
1316         /*
1317          * Any adapter matches if no edev->port is supplied,
1318          * otherwise the ports must match.
1319          */
1320         for(ctlr = gc82543ctlrhead; ctlr != nil; ctlr = ctlr->next){
1321                 if(ctlr->active)
1322                         continue;
1323                 if(edev->port == 0 || edev->port == ctlr->port){
1324                         ctlr->active = 1;
1325                         break;
1326                 }
1327         }
1328         if(ctlr == nil)
1329                 return -1;
1330
1331         edev->ctlr = ctlr;
1332         edev->port = ctlr->port;
1333         edev->irq = ctlr->pcidev->intl;
1334         edev->tbdf = ctlr->pcidev->tbdf;
1335         edev->mbps = 1000;
1336
1337         /*
1338          * Check if the adapter's station address is to be overridden.
1339          * If not, read it from the EEPROM and set in ether->ea prior to
1340          * loading the station address in the hardware.
1341          */
1342         memset(ea, 0, Eaddrlen);
1343         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1344                 for(i = Ea; i < Eaddrlen/2; i++){
1345                         edev->ea[2*i] = ctlr->eeprom[i];
1346                         edev->ea[2*i+1] = ctlr->eeprom[i]>>8;
1347                 }
1348         }
1349         gc82543init(edev);
1350
1351         /*
1352          * Linkage to the generic ethernet driver.
1353          */
1354         edev->attach = gc82543attach;
1355         edev->transmit = gc82543transmit;
1356         edev->interrupt = gc82543interrupt;
1357         edev->ifstat = gc82543ifstat;
1358         edev->shutdown = gc82543shutdown;
1359         edev->ctl = gc82543ctl;
1360         edev->arg = edev;
1361         edev->promiscuous = gc82543promiscuous;
1362         edev->multicast = gc82543multicast;
1363
1364         return 0;
1365 }
1366
1367 void
1368 ether82543gclink(void)
1369 {
1370         addethercard("82543GC", gc82543pnp);
1371 }