sys/src/9/pc/ether8169.c

   1 /*
   2  * Realtek RTL8110S/8169S Gigabit Ethernet Controllers.
   3  * Mostly there. There are some magic register values used
   4  * which are not described in any datasheet or driver but seem
   5  * to be necessary.
   6  * No tuning has been done. Only tested on an RTL8110S, there
   7  * are slight differences between the chips in the series so some
   8  * tweaks may be needed.
   9  */
  10 #include "u.h"
  11 #include "../port/lib.h"
  12 #include "mem.h"
  13 #include "dat.h"
  14 #include "fns.h"
  15 #include "io.h"
  16 #include "../port/error.h"
  17 #include "../port/netif.h"
  18
  19 #include "etherif.h"
  20 #include "ethermii.h"
  21
  22 enum {                                  /* registers */
  23         Idr0            = 0x00,         /* MAC address */
  24         Mar0            = 0x08,         /* Multicast address */
  25         Dtccr           = 0x10,         /* Dump Tally Counter Command */
  26         Tnpds           = 0x20,         /* Transmit Normal Priority Descriptors */
  27         Thpds           = 0x28,         /* Transmit High Priority Descriptors */
  28         Flash           = 0x30,         /* Flash Memory Read/Write */
  29         Erbcr           = 0x34,         /* Early Receive Byte Count */
  30         Ersr            = 0x36,         /* Early Receive Status */
  31         Cr              = 0x37,         /* Command Register */
  32         Tppoll          = 0x38,         /* Transmit Priority Polling */
  33         Imr             = 0x3C,         /* Interrupt Mask */
  34         Isr             = 0x3E,         /* Interrupt Status */
  35         Tcr             = 0x40,         /* Transmit Configuration */
  36         Rcr             = 0x44,         /* Receive Configuration */
  37         Tctr            = 0x48,         /* Timer Count */
  38         Mpc             = 0x4C,         /* Missed Packet Counter */
  39         Cr9346          = 0x50,         /* 9346 Command Register */
  40         Config0         = 0x51,         /* Configuration Register 0 */
  41         Config1         = 0x52,         /* Configuration Register 1 */
  42         Config2         = 0x53,         /* Configuration Register 2 */
  43         Config3         = 0x54,         /* Configuration Register 3 */
  44         Config4         = 0x55,         /* Configuration Register 4 */
  45         Config5         = 0x56,         /* Configuration Register 5 */
  46         Timerint        = 0x58,         /* Timer Interrupt */
  47         Mulint          = 0x5C,         /* Multiple Interrupt Select */
  48         Phyar           = 0x60,         /* PHY Access */
  49         Tbicsr0         = 0x64,         /* TBI Control and Status */
  50         Tbianar         = 0x68,         /* TBI Auto-Negotiation Advertisment */
  51         Tbilpar         = 0x6A,         /* TBI Auto-Negotiation Link Partner */
  52         Phystatus       = 0x6C,         /* PHY Status */
  53         Pmch            = 0x6F,         /* power management */
  54         Ldps            = 0x82,         /* link down power saving */
  55
  56         Rms             = 0xDA,         /* Receive Packet Maximum Size */
  57         Cplusc          = 0xE0,         /* C+ Command */
  58         Coal            = 0xE2,         /* Interrupt Mitigation (Coalesce) */
  59         Rdsar           = 0xE4,         /* Receive Descriptor Start Address */
  60         Etx             = 0xEC,         /* Early Transmit Threshold */
  61 };
  62
  63 enum {                                  /* Dtccr */
  64         Cmd             = 0x00000008,   /* Command */
  65 };
  66
  67 enum {                                  /* Cr */
  68         Te              = 0x04,         /* Transmitter Enable */
  69         Re              = 0x08,         /* Receiver Enable */
  70         Rst             = 0x10,         /* Software Reset */
  71 };
  72
  73 enum {                                  /* Tppoll */
  74         Fswint          = 0x01,         /* Forced Software Interrupt */
  75         Npq             = 0x40,         /* Normal Priority Queue polling */
  76         Hpq             = 0x80,         /* High Priority Queue polling */
  77 };
  78
  79 enum {                                  /* Imr/Isr */
  80         Rok             = 0x0001,       /* Receive OK */
  81         Rer             = 0x0002,       /* Receive Error */
  82         Tok             = 0x0004,       /* Transmit OK */
  83         Ter             = 0x0008,       /* Transmit Error */
  84         Rdu             = 0x0010,       /* Receive Descriptor Unavailable */
  85         Punlc           = 0x0020,       /* Packet Underrun or Link Change */
  86         Fovw            = 0x0040,       /* Receive FIFO Overflow */
  87         Tdu             = 0x0080,       /* Transmit Descriptor Unavailable */
  88         Swint           = 0x0100,       /* Software Interrupt */
  89         Timeout         = 0x4000,       /* Timer */
  90         Serr            = 0x8000,       /* System Error */
  91 };
  92
  93 enum {                                  /* Tcr */
  94         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
  95         MtxdmaMASK      = 0x00000700,
  96         Mtxdmaunlimited = 0x00000700,
  97         Acrc            = 0x00010000,   /* Append CRC (not) */
  98         Lbk0            = 0x00020000,   /* Loopback Test 0 */
  99         Lbk1            = 0x00040000,   /* Loopback Test 1 */
 100         Ifg2            = 0x00080000,   /* Interframe Gap 2 */
 101         HwveridSHIFT    = 23,           /* Hardware Version ID */
 102         HwveridMASK     = 0x7C800000,
 103         Macv01          = 0x00000000,   /* RTL8169 */
 104         Macv02          = 0x00800000,   /* RTL8169S/8110S */
 105         Macv03          = 0x04000000,   /* RTL8169S/8110S */
 106         Macv04          = 0x10000000,   /* RTL8169SB/8110SB */
 107         Macv05          = 0x18000000,   /* RTL8169SC/8110SC */
 108         Macv07          = 0x24800000,   /* RTL8102e */
 109         Macv07a         = 0x34800000,   /* RTL8102e */
 110         Macv11          = 0x30000000,   /* RTL8168B/8111B */
 111         Macv12          = 0x38000000,   /* RTL8169B/8111B */
 112         Macv12a         = 0x3c000000,   /* RTL8169C/8111C */
 113         Macv13          = 0x34000000,   /* RTL8101E */
 114         Macv14          = 0x30800000,   /* RTL8100E */
 115         Macv15          = 0x38800000,   /* RTL8100E */
 116 //      Macv19          = 0x3c000000,   /* dup Macv12a: RTL8111c-gr */
 117         Macv25          = 0x28000000,   /* RTL8168D */
 118         Macv26          = 0x48000000,   /* RTL8111/8168B */
 119         Macv27          = 0x2c800000,   /* RTL8111e */
 120         Macv28          = 0x2c000000,   /* RTL8111/8168B */
 121         Macv29          = 0x40800000,   /* RTL8101/8102E */
 122         Macv30          = 0x24000000,   /* RTL8101E? (untested) */
 123         Ifg0            = 0x01000000,   /* Interframe Gap 0 */
 124         Ifg1            = 0x02000000,   /* Interframe Gap 1 */
 125 };
 126
 127 enum {                                  /* Rcr */
 128         Aap             = 0x00000001,   /* Accept All Packets */
 129         Apm             = 0x00000002,   /* Accept Physical Match */
 130         Am              = 0x00000004,   /* Accept Multicast */
 131         Ab              = 0x00000008,   /* Accept Broadcast */
 132         Ar              = 0x00000010,   /* Accept Runt */
 133         Aer             = 0x00000020,   /* Accept Error */
 134         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
 135         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 136         MrxdmaMASK      = 0x00000700,
 137         Mrxdmaunlimited = 0x00000700,
 138         RxfthSHIFT      = 13,           /* Receive Buffer Length */
 139         RxfthMASK       = 0x0000E000,
 140         Rxfth256        = 0x00008000,
 141         Rxfthnone       = 0x0000E000,
 142         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
 143         MulERINT        = 0x01000000,   /* Multiple Early Interrupt Select */
 144 };
 145
 146 enum {                                  /* Cr9346 */
 147         Eedo            = 0x01,         /* */
 148         Eedi            = 0x02,         /* */
 149         Eesk            = 0x04,         /* */
 150         Eecs            = 0x08,         /* */
 151         Eem0            = 0x40,         /* Operating Mode */
 152         Eem1            = 0x80,
 153 };
 154
 155 enum {                                  /* Phyar */
 156         DataMASK        = 0x0000FFFF,   /* 16-bit GMII/MII Register Data */
 157         DataSHIFT       = 0,
 158         RegaddrMASK     = 0x001F0000,   /* 5-bit GMII/MII Register Address */
 159         RegaddrSHIFT    = 16,
 160         Flag            = 0x80000000,   /* */
 161 };
 162
 163 enum {                                  /* Phystatus */
 164         Fd              = 0x01,         /* Full Duplex */
 165         Linksts         = 0x02,         /* Link Status */
 166         Speed10         = 0x04,         /* */
 167         Speed100        = 0x08,         /* */
 168         Speed1000       = 0x10,         /* */
 169         Rxflow          = 0x20,         /* */
 170         Txflow          = 0x40,         /* */
 171         Entbi           = 0x80,         /* */
 172 };
 173
 174 enum {                                  /* Cplusc */
 175         Txenb           = 0x0001,       /* enable C+ transmit mode */
 176         Rxenb           = 0x0002,       /* enable C+ receive mode */
 177         Mulrw           = 0x0008,       /* PCI Multiple R/W Enable */
 178         Dac             = 0x0010,       /* PCI Dual Address Cycle Enable */
 179         Rxchksum        = 0x0020,       /* Receive Checksum Offload Enable */
 180         Rxvlan          = 0x0040,       /* Receive VLAN De-tagging Enable */
 181         Endian          = 0x0200,       /* Endian Mode */
 182 };
 183
 184 typedef struct D D;                     /* Transmit/Receive Descriptor */
 185 struct D {
 186         u32int  control;
 187         u32int  vlan;
 188         u32int  addrlo;
 189         u32int  addrhi;
 190 };
 191
 192 enum {                                  /* Transmit Descriptor control */
 193         TxflMASK        = 0x0000FFFF,   /* Transmit Frame Length */
 194         TxflSHIFT       = 0,
 195         Tcps            = 0x00010000,   /* TCP Checksum Offload */
 196         Udpcs           = 0x00020000,   /* UDP Checksum Offload */
 197         Ipcs            = 0x00040000,   /* IP Checksum Offload */
 198         Lgsen           = 0x08000000,   /* TSO; WARNING: contains lark's vomit */
 199 };
 200
 201 enum {                                  /* Receive Descriptor control */
 202         RxflMASK        = 0x00001FFF,   /* Receive Frame Length */
 203         Tcpf            = 0x00004000,   /* TCP Checksum Failure */
 204         Udpf            = 0x00008000,   /* UDP Checksum Failure */
 205         Ipf             = 0x00010000,   /* IP Checksum Failure */
 206         Pid0            = 0x00020000,   /* Protocol ID0 */
 207         Pid1            = 0x00040000,   /* Protocol ID1 */
 208         Crce            = 0x00080000,   /* CRC Error */
 209         Runt            = 0x00100000,   /* Runt Packet */
 210         Res             = 0x00200000,   /* Receive Error Summary */
 211         Rwt             = 0x00400000,   /* Receive Watchdog Timer Expired */
 212         Fovf            = 0x00800000,   /* FIFO Overflow */
 213         Bovf            = 0x01000000,   /* Buffer Overflow */
 214         Bar             = 0x02000000,   /* Broadcast Address Received */
 215         Pam             = 0x04000000,   /* Physical Address Matched */
 216         Mar             = 0x08000000,   /* Multicast Address Received */
 217 };
 218
 219 enum {                                  /* General Descriptor control */
 220         Ls              = 0x10000000,   /* Last Segment Descriptor */
 221         Fs              = 0x20000000,   /* First Segment Descriptor */
 222         Eor             = 0x40000000,   /* End of Descriptor Ring */
 223         Own             = 0x80000000,   /* Ownership */
 224 };
 225
 226 /*
 227  */
 228 enum {                                  /* Ring sizes  (<= 1024) */
 229         Ntd             = 64,           /* Transmit Ring */
 230         Nrd             = 256,          /* Receive Ring */
 231
 232         Mtu             = ETHERMAXTU,
 233         Mps             = ROUNDUP(ETHERMAXTU+4, 128),
 234 };
 235
 236 typedef struct Dtcc Dtcc;
 237 struct Dtcc {
 238         u64int  txok;
 239         u64int  rxok;
 240         u64int  txer;
 241         u32int  rxer;
 242         u16int  misspkt;
 243         u16int  fae;
 244         u32int  tx1col;
 245         u32int  txmcol;
 246         u64int  rxokph;
 247         u64int  rxokbrd;
 248         u32int  rxokmu;
 249         u16int  txabt;
 250         u16int  txundrn;
 251 };
 252
 253 enum {                                          /* Variants */
 254         Rtl8100e        = (0x8136<<16)|0x10EC,  /* RTL810[01]E: pci -e */
 255         Rtl8169c        = (0x0116<<16)|0x16EC,  /* RTL8169C+ (USR997902) */
 256         Rtl8169sc       = (0x8167<<16)|0x10EC,  /* RTL8169SC */
 257         Rtl8168b        = (0x8168<<16)|0x10EC,  /* RTL8168B: pci-e */
 258         Rtl8169         = (0x8169<<16)|0x10EC,  /* RTL8169 */
 259 };
 260
 261 typedef struct Ctlr Ctlr;
 262 typedef struct Ctlr {
 263         Lock;
 264
 265         int     port;
 266         Pcidev* pcidev;
 267         Ctlr*   next;
 268         int     active;
 269
 270         QLock   alock;                  /* attach */
 271         int     init;                   /*  */
 272         Rendez  reset;
 273
 274         int     pciv;                   /*  */
 275         int     macv;                   /* MAC version */
 276         int     phyv;                   /* PHY version */
 277         int     pcie;                   /* flag: pci-express device? */
 278
 279         uvlong  mchash;                 /* multicast hash */
 280
 281         Mii*    mii;
 282
 283         D*      td;                     /* descriptor ring */
 284         Block** tb;                     /* transmit buffers */
 285         int     ntd;
 286
 287         int     tdh;                    /* head - producer index (host) */
 288         int     tdt;                    /* tail - consumer index (NIC) */
 289         int     ntq;
 290
 291         D*      rd;                     /* descriptor ring */
 292         Block** rb;                     /* receive buffers */
 293         int     nrd;
 294
 295         int     rdh;                    /* head - producer index (NIC) */
 296         int     rdt;                    /* tail - consumer index (host) */
 297         int     nrq;
 298
 299         int     tcr;                    /* transmit configuration register */
 300         int     rcr;                    /* receive configuration register */
 301         int     imr;
 302
 303         QLock   slock;                  /* statistics */
 304         Dtcc*   dtcc;
 305         uint    txdu;
 306         uint    tcpf;
 307         uint    udpf;
 308         uint    ipf;
 309         uint    fovf;
 310         uint    rer;
 311         uint    rdu;
 312         uint    punlc;
 313         uint    serr;
 314         uint    fovw;
 315         uint    mcast;
 316         uint    frag;                   /* partial packets; rb was too small */
 317 } Ctlr;
 318
 319 static Ctlr* rtl8169ctlrhead;
 320 static Ctlr* rtl8169ctlrtail;
 321
 322 #define csr8r(c, r)     (inb((c)->port+(r)))
 323 #define csr16r(c, r)    (ins((c)->port+(r)))
 324 #define csr32r(c, r)    (inl((c)->port+(r)))
 325 #define csr8w(c, r, b)  (outb((c)->port+(r), (u8int)(b)))
 326 #define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w)))
 327 #define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l)))
 328
 329 static int
 330 rtl8169miimir(Mii* mii, int pa, int ra)
 331 {
 332         uint r;
 333         int timeo;
 334         Ctlr *ctlr;
 335
 336         if(pa != 1)
 337                 return -1;
 338         ctlr = mii->ctlr;
 339
 340         r = (ra<<16) & RegaddrMASK;
 341         csr32w(ctlr, Phyar, r);
 342         delay(1);
 343         for(timeo = 0; timeo < 2000; timeo++){
 344                 if((r = csr32r(ctlr, Phyar)) & Flag)
 345                         break;
 346                 microdelay(100);
 347         }
 348         if(!(r & Flag))
 349                 return -1;
 350
 351         return (r & DataMASK)>>DataSHIFT;
 352 }
 353
 354 static int
 355 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
 356 {
 357         uint r;
 358         int timeo;
 359         Ctlr *ctlr;
 360
 361         if(pa != 1)
 362                 return -1;
 363         ctlr = mii->ctlr;
 364
 365         r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
 366         csr32w(ctlr, Phyar, r);
 367         delay(1);
 368         for(timeo = 0; timeo < 2000; timeo++){
 369                 if(!((r = csr32r(ctlr, Phyar)) & Flag))
 370                         break;
 371                 microdelay(100);
 372         }
 373         if(r & Flag)
 374                 return -1;
 375
 376         return 0;
 377 }
 378
 379 static int
 380 rtl8169mii(Ctlr* ctlr)
 381 {
 382         MiiPhy *phy;
 383
 384         /*
 385          * Link management.
 386          */
 387         if((ctlr->mii = malloc(sizeof(Mii))) == nil)
 388                 return -1;
 389         ctlr->mii->mir = rtl8169miimir;
 390         ctlr->mii->miw = rtl8169miimiw;
 391         ctlr->mii->ctlr = ctlr;
 392
 393         /*
 394          * PHY wakeup
 395          */
 396         switch(ctlr->macv){
 397         case Macv25:
 398         case Macv28:
 399         case Macv29:
 400         case Macv30:
 401                 csr8w(ctlr, Pmch, csr8r(ctlr, Pmch) | 0x80);
 402                 break;
 403         }
 404         rtl8169miimiw(ctlr->mii, 1, 0x1f, 0);
 405         rtl8169miimiw(ctlr->mii, 1, 0x0e, 0);
 406
 407         /*
 408          * Get rev number out of Phyidr2 so can config properly.
 409          * There's probably more special stuff for Macv0[234] needed here.
 410          */
 411         ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
 412         if(ctlr->macv == Macv02){
 413                 csr8w(ctlr, Ldps, 1);                           /* magic */
 414                 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);      /* magic */
 415         }
 416
 417         if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
 418                 free(ctlr->mii);
 419                 ctlr->mii = nil;
 420                 return -1;
 421         }
 422         print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 423                 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 424
 425         miireset(ctlr->mii);
 426
 427         microdelay(100);
 428
 429         miiane(ctlr->mii, ~0, ~0, ~0);
 430
 431         return 0;
 432 }
 433
 434 static void
 435 rtl8169promiscuous(void* arg, int on)
 436 {
 437         Ether *edev;
 438         Ctlr * ctlr;
 439
 440         edev = arg;
 441         ctlr = edev->ctlr;
 442         ilock(ctlr);
 443         if(on)
 444                 ctlr->rcr |= Aap;
 445         else
 446                 ctlr->rcr &= ~Aap;
 447         csr32w(ctlr, Rcr, ctlr->rcr);
 448         iunlock(ctlr);
 449 }
 450
 451 enum {
 452         /* everyone else uses 0x04c11db7, but they both produce the same crc */
 453         Etherpolybe = 0x04c11db6,
 454         Bytemask = (1<<8) - 1,
 455 };
 456
 457 static ulong
 458 ethercrcbe(uchar *addr, long len)
 459 {
 460         int i, j;
 461         ulong c, crc, carry;
 462
 463         crc = ~0UL;
 464         for (i = 0; i < len; i++) {
 465                 c = addr[i];
 466                 for (j = 0; j < 8; j++) {
 467                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
 468                         crc <<= 1;
 469                         c >>= 1;
 470                         if (carry)
 471                                 crc = (crc ^ Etherpolybe) | carry;
 472                 }
 473         }
 474         return crc;
 475 }
 476
 477 static ulong
 478 swabl(ulong l)
 479 {
 480         return l>>24 | (l>>8) & (Bytemask<<8) |
 481                 (l<<8) & (Bytemask<<16) | l<<24;
 482 }
 483
 484 static void
 485 rtl8169multicast(void* ether, uchar *eaddr, int add)
 486 {
 487         Ether *edev;
 488         Ctlr *ctlr;
 489
 490         if (!add)
 491                 return; /* ok to keep receiving on old mcast addrs */
 492
 493         edev = ether;
 494         ctlr = edev->ctlr;
 495         ilock(ctlr);
 496
 497         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
 498
 499         ctlr->rcr |= Am;
 500         csr32w(ctlr, Rcr, ctlr->rcr);
 501
 502         /* pci-e variants reverse the order of the hash byte registers */
 503         if (ctlr->pcie) {
 504                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
 505                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
 506         } else {
 507                 csr32w(ctlr, Mar0,   ctlr->mchash);
 508                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
 509         }
 510
 511         iunlock(ctlr);
 512 }
 513
 514 static long
 515 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
 516 {
 517         char *p;
 518         Ctlr *ctlr;
 519         Dtcc *dtcc;
 520         int i, l, r, timeo;
 521
 522         p = smalloc(READSTR);
 523
 524         ctlr = edev->ctlr;
 525         qlock(&ctlr->slock);
 526
 527         if(waserror()){
 528                 qunlock(&ctlr->slock);
 529                 free(p);
 530                 nexterror();
 531         }
 532
 533         csr32w(ctlr, Dtccr+4, 0);
 534         csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd);
 535         for(timeo = 0; timeo < 1000; timeo++){
 536                 if(!(csr32r(ctlr, Dtccr) & Cmd))
 537                         break;
 538                 delay(1);
 539         }
 540         if(csr32r(ctlr, Dtccr) & Cmd)
 541                 error(Eio);
 542         dtcc = ctlr->dtcc;
 543
 544         edev->oerrs = dtcc->txer;
 545         edev->crcs = dtcc->rxer;
 546         edev->frames = dtcc->fae;
 547         edev->buffs = dtcc->misspkt;
 548         edev->overflows = ctlr->txdu+ctlr->rdu;
 549
 550         if(n == 0){
 551                 qunlock(&ctlr->slock);
 552                 poperror();
 553                 free(p);
 554                 return 0;
 555         }
 556
 557         l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
 558         l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
 559         l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
 560         l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
 561         l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
 562         l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
 563         l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
 564         l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
 565         l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
 566         l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
 567         l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
 568         l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
 569         l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
 570
 571         l += snprint(p+l, READSTR-l, "serr: %ud\n", ctlr->serr);
 572         l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
 573
 574         l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
 575         l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
 576         l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
 577         l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
 578         l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
 579         l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
 580         l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
 581         l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
 582
 583         l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
 584         l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
 585         l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
 586
 587         if(ctlr->mii != nil && ctlr->mii->curphy != nil){
 588                 l += snprint(p+l, READSTR, "phy:   ");
 589                 for(i = 0; i < NMiiPhyr; i++){
 590                         if(i && ((i & 0x07) == 0))
 591                                 l += snprint(p+l, READSTR-l, "\n       ");
 592                         r = miimir(ctlr->mii, i);
 593                         l += snprint(p+l, READSTR-l, " %4.4ux", r);
 594                 }
 595                 snprint(p+l, READSTR-l, "\n");
 596         }
 597
 598         n = readstr(offset, a, n, p);
 599
 600         qunlock(&ctlr->slock);
 601         poperror();
 602         free(p);
 603
 604         return n;
 605 }
 606
 607 static void
 608 rtl8169halt(Ctlr* ctlr)
 609 {
 610         csr8w(ctlr, Cr, 0);
 611         csr16w(ctlr, Imr, 0);
 612         csr16w(ctlr, Isr, ~0);
 613 }
 614
 615 static int
 616 rtl8169reset(Ctlr* ctlr)
 617 {
 618         u32int r;
 619         int timeo;
 620
 621         /*
 622          * Soft reset the controller.
 623          */
 624         csr8w(ctlr, Cr, Rst);
 625         for(r = timeo = 0; timeo < 1000; timeo++){
 626                 r = csr8r(ctlr, Cr);
 627                 if(!(r & Rst))
 628                         break;
 629                 delay(1);
 630         }
 631         rtl8169halt(ctlr);
 632
 633         if(r & Rst)
 634                 return -1;
 635         return 0;
 636 }
 637
 638 static void
 639 rtl8169replenish(Ctlr* ctlr)
 640 {
 641         D *d;
 642         int x;
 643         Block *bp;
 644
 645         x = ctlr->rdt;
 646         while(NEXT(x, ctlr->nrd) != ctlr->rdh){
 647                 bp = iallocb(Mps);
 648                 if(bp == nil){
 649                         iprint("rtl8169: no available buffers\n");
 650                         break;
 651                 }
 652                 ctlr->rb[x] = bp;
 653                 ctlr->nrq++;
 654                 d = &ctlr->rd[x];
 655                 d->addrlo = PCIWADDR(bp->rp);
 656                 d->addrhi = 0;
 657                 coherence();
 658                 d->control = (d->control & Eor) | Own | BALLOC(bp);
 659                 x = NEXT(x, ctlr->nrd);
 660                 ctlr->rdt = x;
 661         }
 662 }
 663
 664 static int
 665 rtl8169init(Ether* edev)
 666 {
 667         int i;
 668         u32int r;
 669         Block *bp;
 670         Ctlr *ctlr;
 671         u8int cplusc;
 672
 673         ctlr = edev->ctlr;
 674         ilock(ctlr);
 675
 676         rtl8169reset(ctlr);
 677
 678         memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
 679         ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
 680         ctlr->td[ctlr->ntd-1].control = Eor;
 681         for(i = 0; i < ctlr->ntd; i++)
 682                 if(bp = ctlr->tb[i]){
 683                         ctlr->tb[i] = nil;
 684                         freeb(bp);
 685                 }
 686
 687         memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
 688         ctlr->rdh = ctlr->rdt = ctlr->nrq = 0;
 689         ctlr->rd[ctlr->nrd-1].control = Eor;
 690         for(i = 0; i < ctlr->nrd; i++)
 691                 if(bp = ctlr->rb[i]){
 692                         ctlr->rb[i] = nil;
 693                         freeb(bp);
 694                 }
 695
 696         rtl8169replenish(ctlr);
 697
 698         cplusc = csr16r(ctlr, Cplusc);
 699         cplusc &= ~(Endian|Rxchksum);
 700         cplusc |= Txenb|Rxenb|Mulrw;
 701         csr16w(ctlr, Cplusc, cplusc);
 702
 703         csr32w(ctlr, Tnpds+4, 0);
 704         csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
 705         csr32w(ctlr, Rdsar+4, 0);
 706         csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
 707
 708         csr8w(ctlr, Cr, Te|Re);
 709
 710         csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
 711         ctlr->tcr = csr32r(ctlr, Tcr);
 712         ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
 713         ctlr->mchash = 0;
 714         csr32w(ctlr, Mar0,   0);
 715         csr32w(ctlr, Mar0+4, 0);
 716         csr32w(ctlr, Rcr, ctlr->rcr);
 717
 718         /* maximum packet sizes, unlimited */
 719         csr8w(ctlr, Etx, 0x3f);
 720         csr16w(ctlr, Rms, 0x3fff);
 721
 722         csr16w(ctlr, Coal, 0);
 723
 724         /* no early rx interrupts */
 725         r = csr16r(ctlr, Mulint) & 0xF000;
 726         csr16w(ctlr, Mulint, r);
 727
 728         ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Rer|Rok|Tdu;
 729         csr16w(ctlr, Imr, ctlr->imr);
 730
 731         csr32w(ctlr, Mpc, 0);
 732
 733         iunlock(ctlr);
 734
 735         return 0;
 736 }
 737
 738 static void
 739 rtl8169reseter(void *arg)
 740 {
 741         Ether *edev;
 742         Ctlr *ctlr;
 743
 744         edev = arg;
 745
 746         for(;;){
 747                 rtl8169init(edev);
 748
 749                 ctlr = edev->ctlr;
 750                 qunlock(&ctlr->alock);
 751
 752                 while(waserror())
 753                         ;
 754                 sleep(&ctlr->reset, return0, nil);
 755                 poperror();
 756
 757                 qlock(&ctlr->alock);
 758         }
 759 }
 760
 761 static void
 762 rtl8169attach(Ether* edev)
 763 {
 764         int timeo;
 765         Ctlr *ctlr;
 766
 767         ctlr = edev->ctlr;
 768         qlock(&ctlr->alock);
 769         if(!ctlr->init){
 770                 ctlr->ntd = Ntd;
 771                 ctlr->nrd = Nrd;
 772                 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
 773                 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
 774                 ctlr->td = mallocalign(sizeof(D)*ctlr->ntd, 256, 0, 0);
 775                 ctlr->rd = mallocalign(sizeof(D)*ctlr->nrd, 256, 0, 0);
 776                 ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
 777                 if(ctlr->rb == nil || ctlr->rb == nil ||
 778                    ctlr->rd == nil || ctlr->rd == nil || ctlr->dtcc == nil){
 779                         free(ctlr->tb);
 780                         ctlr->tb = nil;
 781                         free(ctlr->rb);
 782                         ctlr->rb = nil;
 783                         free(ctlr->td);
 784                         ctlr->td = nil;
 785                         free(ctlr->rd);
 786                         ctlr->rd = nil;
 787                         free(ctlr->dtcc);
 788                         ctlr->dtcc = nil;
 789                         qunlock(&ctlr->alock);
 790                         error(Enomem);
 791                 }
 792                 ctlr->init = 1;
 793                 kproc("rtl8169", rtl8169reseter, edev);
 794
 795                 /* rtl8169reseter() does qunlock(&ctlr->alock) when complete */
 796                 qlock(&ctlr->alock);
 797         }
 798         qunlock(&ctlr->alock);
 799
 800         /*
 801          * Wait for link to be ready.
 802          */
 803         for(timeo = 0; timeo < 35; timeo++){
 804                 if(miistatus(ctlr->mii) == 0)
 805                         break;
 806                 delay(100);             /* print fewer miistatus messages */
 807         }
 808 }
 809
 810 static void
 811 rtl8169link(Ether* edev)
 812 {
 813         uint r;
 814         int limit;
 815         Ctlr *ctlr;
 816
 817         ctlr = edev->ctlr;
 818
 819         /*
 820          * Maybe the link changed - do we care very much?
 821          * Could stall transmits if no link, maybe?
 822          */
 823         if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
 824                 edev->link = 0;
 825                 return;
 826         }
 827         edev->link = 1;
 828
 829         limit = 256*1024;
 830         if(r & Speed10){
 831                 edev->mbps = 10;
 832                 limit = 65*1024;
 833         } else if(r & Speed100)
 834                 edev->mbps = 100;
 835         else if(r & Speed1000)
 836                 edev->mbps = 1000;
 837
 838         if(edev->oq != nil)
 839                 qsetlimit(edev->oq, limit);
 840 }
 841
 842 static void
 843 rtl8169transmit(Ether* edev)
 844 {
 845         D *d;
 846         Block *bp;
 847         Ctlr *ctlr;
 848         int x;
 849
 850         ctlr = edev->ctlr;
 851
 852         if(!canlock(ctlr))
 853                 return;
 854         for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
 855                 d = &ctlr->td[x];
 856                 if(d->control & Own)
 857                         break;
 858
 859                 /*
 860                  * Free it up.
 861                  * Need to clean the descriptor here? Not really.
 862                  * Simple freeb for now (no chain and freeblist).
 863                  * Use ntq count for now.
 864                  */
 865                 freeb(ctlr->tb[x]);
 866                 ctlr->tb[x] = nil;
 867                 ctlr->ntq--;
 868         }
 869         ctlr->tdh = x;
 870
 871         x = ctlr->tdt;
 872         while(ctlr->ntq < (ctlr->ntd-1)){
 873                 if((bp = qget(edev->oq)) == nil)
 874                         break;
 875
 876                 d = &ctlr->td[x];
 877                 d->addrlo = PCIWADDR(bp->rp);
 878                 d->addrhi = 0;
 879                 coherence();
 880                 d->control = (d->control & Eor) | Own | Fs | Ls | BLEN(bp);
 881
 882                 ctlr->tb[x] = bp;
 883                 ctlr->ntq++;
 884
 885                 x = NEXT(x, ctlr->ntd);
 886         }
 887         if(x != ctlr->tdt)
 888                 ctlr->tdt = x;
 889         else if(ctlr->ntq >= (ctlr->ntd-1))
 890                 ctlr->txdu++;
 891
 892         if(ctlr->ntq > 0){
 893                 coherence();
 894                 csr8w(ctlr, Tppoll, Npq);
 895         }
 896         unlock(ctlr);
 897 }
 898
 899 static void
 900 rtl8169receive(Ether* edev)
 901 {
 902         D *d;
 903         Block *bp;
 904         Ctlr *ctlr;
 905         u32int control;
 906         int x;
 907
 908         ctlr = edev->ctlr;
 909         x = ctlr->rdh;
 910         for(;;){
 911                 d = &ctlr->rd[x];
 912                 if((control = d->control) & Own)
 913                         break;
 914
 915                 bp = ctlr->rb[x];
 916                 ctlr->rb[x] = nil;
 917                 ctlr->nrq--;
 918
 919                 x = NEXT(x, ctlr->nrd);
 920                 ctlr->rdh = x;
 921
 922                 if(ctlr->nrq < ctlr->nrd/2)
 923                         rtl8169replenish(ctlr);
 924
 925                 if((control & (Fs|Ls|Res)) == (Fs|Ls)){
 926                         bp->wp = bp->rp + (control & RxflMASK) - 4;
 927
 928                         if(control & Fovf)
 929                                 ctlr->fovf++;
 930                         if(control & Mar)
 931                                 ctlr->mcast++;
 932
 933                         switch(control & (Pid1|Pid0)){
 934                         default:
 935                                 break;
 936                         case Pid0:
 937                                 if(control & Tcpf){
 938                                         ctlr->tcpf++;
 939                                         break;
 940                                 }
 941                                 bp->flag |= Btcpck;
 942                                 break;
 943                         case Pid1:
 944                                 if(control & Udpf){
 945                                         ctlr->udpf++;
 946                                         break;
 947                                 }
 948                                 bp->flag |= Budpck;
 949                                 break;
 950                         case Pid1|Pid0:
 951                                 if(control & Ipf){
 952                                         ctlr->ipf++;
 953                                         break;
 954                                 }
 955                                 bp->flag |= Bipck;
 956                                 break;
 957                         }
 958                         etheriq(edev, bp, 1);
 959                 }else{
 960                         if(!(control & Res))
 961                                 ctlr->frag++;
 962                         freeb(bp);
 963                 }
 964         }
 965 }
 966
 967 static void
 968 rtl8169restart(Ctlr *ctlr)
 969 {
 970         ctlr->imr = 0;
 971         rtl8169halt(ctlr);
 972         wakeup(&ctlr->reset);
 973 }
 974
 975 static void
 976 rtl8169interrupt(Ureg*, void* arg)
 977 {
 978         Ctlr *ctlr;
 979         Ether *edev;
 980         u32int isr;
 981
 982         edev = arg;
 983         ctlr = edev->ctlr;
 984
 985         while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
 986                 csr16w(ctlr, Isr, isr);
 987                 if((isr & ctlr->imr) == 0)
 988                         break;
 989
 990                 if(isr & Serr)
 991                         ctlr->serr++;
 992                 if(isr & Fovw)
 993                         ctlr->fovw++;
 994                 if(isr & Rer)
 995                         ctlr->rer++;
 996                 if(isr & Rdu)
 997                         ctlr->rdu++;
 998                 if(isr & Punlc)
 999                         ctlr->punlc++;
1000
1001                 if(isr & (Serr|Fovw)){
1002                         rtl8169restart(ctlr);
1003                         break;
1004                 }
1005
1006                 if(isr & (Punlc|Rdu|Rer|Rok))
1007                         rtl8169receive(edev);
1008
1009                 if(isr & (Tdu|Ter|Tok))
1010                         rtl8169transmit(edev);
1011
1012                 if(isr & Punlc)
1013                         rtl8169link(edev);
1014         }
1015 }
1016
1017 int
1018 vetmacv(Ctlr *ctlr, uint *macv)
1019 {
1020         *macv = csr32r(ctlr, Tcr) & HwveridMASK;
1021         switch(*macv){
1022         default:
1023                 return -1;
1024         case Macv01:
1025         case Macv02:
1026         case Macv03:
1027         case Macv04:
1028         case Macv05:
1029         case Macv07:
1030         case Macv07a:
1031         case Macv11:
1032         case Macv12:
1033         case Macv12a:
1034         case Macv13:
1035         case Macv14:
1036         case Macv15:
1037         case Macv25:
1038         case Macv26:
1039         case Macv27:
1040         case Macv28:
1041         case Macv29:
1042         case Macv30:
1043                 break;
1044         }
1045         return 0;
1046 }
1047
1048 static void
1049 rtl8169pci(void)
1050 {
1051         Pcidev *p;
1052         Ctlr *ctlr;
1053         int i, port, pcie;
1054         uint macv;
1055
1056         p = nil;
1057         while(p = pcimatch(p, 0, 0)){
1058                 if(p->ccrb != 0x02 || p->ccru != 0)
1059                         continue;
1060
1061                 pcie = 0;
1062                 switch(i = ((p->did<<16)|p->vid)){
1063                 default:
1064                         continue;
1065                 case Rtl8100e:                  /* RTL810[01]E ? */
1066                 case Rtl8168b:                  /* RTL8168B */
1067                         pcie = 1;
1068                         break;
1069                 case Rtl8169c:                  /* RTL8169C */
1070                 case Rtl8169sc:                 /* RTL8169SC */
1071                 case Rtl8169:                   /* RTL8169 */
1072                         break;
1073                 case (0xC107<<16)|0x1259:       /* Corega CG-LAPCIGT */
1074                         i = Rtl8169;
1075                         break;
1076                 }
1077
1078                 port = p->mem[0].bar & ~0x01;
1079                 if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
1080                         print("rtl8169: port %#ux in use\n", port);
1081                         continue;
1082                 }
1083                 ctlr = malloc(sizeof(Ctlr));
1084                 if(ctlr == nil){
1085                         print("rtl8169: can't allocate memory\n");
1086                         iofree(port);
1087                         continue;
1088                 }
1089                 ctlr->port = port;
1090                 ctlr->pcidev = p;
1091                 ctlr->pciv = i;
1092                 ctlr->pcie = pcie;
1093
1094                 if(vetmacv(ctlr, &macv) == -1){
1095                         iofree(port);
1096                         free(ctlr);
1097                         print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1098                         continue;
1099                 }
1100
1101                 if(pcigetpms(p) > 0){
1102                         pcisetpms(p, 0);
1103
1104                         for(i = 0; i < 6; i++)
1105                                 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1106                         pcicfgw8(p, PciINTL, p->intl);
1107                         pcicfgw8(p, PciLTR, p->ltr);
1108                         pcicfgw8(p, PciCLS, p->cls);
1109                         pcicfgw16(p, PciPCR, p->pcr);
1110                 }
1111
1112                 if(rtl8169reset(ctlr)){
1113                         iofree(port);
1114                         free(ctlr);
1115                         print("rtl8169: reset failed\n");
1116                         continue;
1117                 }
1118
1119                 /*
1120                  * Extract the chip hardware version,
1121                  * needed to configure each properly.
1122                  */
1123                 ctlr->macv = macv;
1124
1125                 rtl8169mii(ctlr);
1126
1127                 pcisetbme(p);
1128
1129                 if(rtl8169ctlrhead != nil)
1130                         rtl8169ctlrtail->next = ctlr;
1131                 else
1132                         rtl8169ctlrhead = ctlr;
1133                 rtl8169ctlrtail = ctlr;
1134         }
1135 }
1136
1137 static int
1138 rtl8169pnp(Ether* edev)
1139 {
1140         u32int r;
1141         Ctlr *ctlr;
1142         uchar ea[Eaddrlen];
1143         static int once;
1144
1145         if(once == 0){
1146                 once = 1;
1147                 rtl8169pci();
1148         }
1149
1150         /*
1151          * Any adapter matches if no edev->port is supplied,
1152          * otherwise the ports must match.
1153          */
1154         for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1155                 if(ctlr->active)
1156                         continue;
1157                 if(edev->port == 0 || edev->port == ctlr->port){
1158                         ctlr->active = 1;
1159                         break;
1160                 }
1161         }
1162         if(ctlr == nil)
1163                 return -1;
1164
1165         edev->ctlr = ctlr;
1166         edev->port = ctlr->port;
1167         edev->irq = ctlr->pcidev->intl;
1168         edev->tbdf = ctlr->pcidev->tbdf;
1169         edev->mbps = 100;
1170         edev->maxmtu = Mtu;
1171
1172         /*
1173          * Check if the adapter's station address is to be overridden.
1174          * If not, read it from the device and set in edev->ea.
1175          */
1176         memset(ea, 0, Eaddrlen);
1177         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1178                 r = csr32r(ctlr, Idr0);
1179                 edev->ea[0] = r;
1180                 edev->ea[1] = r>>8;
1181                 edev->ea[2] = r>>16;
1182                 edev->ea[3] = r>>24;
1183                 r = csr32r(ctlr, Idr0+4);
1184                 edev->ea[4] = r;
1185                 edev->ea[5] = r>>8;
1186         }
1187
1188         edev->attach = rtl8169attach;
1189         edev->transmit = rtl8169transmit;
1190         edev->interrupt = rtl8169interrupt;
1191         edev->ifstat = rtl8169ifstat;
1192
1193         edev->arg = edev;
1194         edev->promiscuous = rtl8169promiscuous;
1195         edev->multicast = rtl8169multicast;
1196
1197         rtl8169link(edev);
1198
1199         return 0;
1200 }
1201
1202 void
1203 ether8169link(void)
1204 {
1205         addethercard("rtl8169", rtl8169pnp);
1206 }