sys/src/9/pc/ether8169.c

   1 /*
   2  * Realtek RTL8110S/8169S Gigabit Ethernet Controllers.
   3  * Mostly there. There are some magic register values used
   4  * which are not described in any datasheet or driver but seem
   5  * to be necessary.
   6  * No tuning has been done. Only tested on an RTL8110S, there
   7  * are slight differences between the chips in the series so some
   8  * tweaks may be needed.
   9  */
  10 #include "u.h"
  11 #include "../port/lib.h"
  12 #include "mem.h"
  13 #include "dat.h"
  14 #include "fns.h"
  15 #include "io.h"
  16 #include "../port/error.h"
  17 #include "../port/netif.h"
  18 #include "../port/etherif.h"
  19
  20 #include "ethermii.h"
  21
  22 enum {                                  /* registers */
  23         Idr0            = 0x00,         /* MAC address */
  24         Mar0            = 0x08,         /* Multicast address */
  25         Dtccr           = 0x10,         /* Dump Tally Counter Command */
  26         Tnpds           = 0x20,         /* Transmit Normal Priority Descriptors */
  27         Thpds           = 0x28,         /* Transmit High Priority Descriptors */
  28         Flash           = 0x30,         /* Flash Memory Read/Write */
  29         Erbcr           = 0x34,         /* Early Receive Byte Count */
  30         Ersr            = 0x36,         /* Early Receive Status */
  31         Cr              = 0x37,         /* Command Register */
  32         Tppoll          = 0x38,         /* Transmit Priority Polling */
  33         Imr             = 0x3C,         /* Interrupt Mask */
  34         Isr             = 0x3E,         /* Interrupt Status */
  35         Tcr             = 0x40,         /* Transmit Configuration */
  36         Rcr             = 0x44,         /* Receive Configuration */
  37         Tctr            = 0x48,         /* Timer Count */
  38         Mpc             = 0x4C,         /* Missed Packet Counter */
  39         Cr9346          = 0x50,         /* 9346 Command Register */
  40         Config0         = 0x51,         /* Configuration Register 0 */
  41         Config1         = 0x52,         /* Configuration Register 1 */
  42         Config2         = 0x53,         /* Configuration Register 2 */
  43         Config3         = 0x54,         /* Configuration Register 3 */
  44         Config4         = 0x55,         /* Configuration Register 4 */
  45         Config5         = 0x56,         /* Configuration Register 5 */
  46         Timerint        = 0x58,         /* Timer Interrupt */
  47         Mulint          = 0x5C,         /* Multiple Interrupt Select */
  48         Phyar           = 0x60,         /* PHY Access */
  49         Tbicsr0         = 0x64,         /* TBI Control and Status */
  50         Tbianar         = 0x68,         /* TBI Auto-Negotiation Advertisment */
  51         Tbilpar         = 0x6A,         /* TBI Auto-Negotiation Link Partner */
  52         Phystatus       = 0x6C,         /* PHY Status */
  53         Pmch            = 0x6F,         /* power management */
  54         Ldps            = 0x82,         /* link down power saving */
  55
  56         Rms             = 0xDA,         /* Receive Packet Maximum Size */
  57         Cplusc          = 0xE0,         /* C+ Command */
  58         Coal            = 0xE2,         /* Interrupt Mitigation (Coalesce) */
  59         Rdsar           = 0xE4,         /* Receive Descriptor Start Address */
  60         Etx             = 0xEC,         /* Early Transmit Threshold */
  61 };
  62
  63 enum {                                  /* Dtccr */
  64         Cmd             = 0x00000008,   /* Command */
  65 };
  66
  67 enum {                                  /* Cr */
  68         Te              = 0x04,         /* Transmitter Enable */
  69         Re              = 0x08,         /* Receiver Enable */
  70         Rst             = 0x10,         /* Software Reset */
  71 };
  72
  73 enum {                                  /* Tppoll */
  74         Fswint          = 0x01,         /* Forced Software Interrupt */
  75         Npq             = 0x40,         /* Normal Priority Queue polling */
  76         Hpq             = 0x80,         /* High Priority Queue polling */
  77 };
  78
  79 enum {                                  /* Imr/Isr */
  80         Rok             = 0x0001,       /* Receive OK */
  81         Rer             = 0x0002,       /* Receive Error */
  82         Tok             = 0x0004,       /* Transmit OK */
  83         Ter             = 0x0008,       /* Transmit Error */
  84         Rdu             = 0x0010,       /* Receive Descriptor Unavailable */
  85         Punlc           = 0x0020,       /* Packet Underrun or Link Change */
  86         Fovw            = 0x0040,       /* Receive FIFO Overflow */
  87         Tdu             = 0x0080,       /* Transmit Descriptor Unavailable */
  88         Swint           = 0x0100,       /* Software Interrupt */
  89         Timeout         = 0x4000,       /* Timer */
  90         Serr            = 0x8000,       /* System Error */
  91 };
  92
  93 enum {                                  /* Tcr */
  94         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
  95         MtxdmaMASK      = 0x00000700,
  96         Mtxdmaunlimited = 0x00000700,
  97         Acrc            = 0x00010000,   /* Append CRC (not) */
  98         Lbk0            = 0x00020000,   /* Loopback Test 0 */
  99         Lbk1            = 0x00040000,   /* Loopback Test 1 */
 100         Ifg2            = 0x00080000,   /* Interframe Gap 2 */
 101         HwveridSHIFT    = 23,           /* Hardware Version ID */
 102         HwveridMASK     = 0x7C800000,
 103         Macv01          = 0x00000000,   /* RTL8169 */
 104         Macv02          = 0x00800000,   /* RTL8169S/8110S */
 105         Macv03          = 0x04000000,   /* RTL8169S/8110S */
 106         Macv04          = 0x10000000,   /* RTL8169SB/8110SB */
 107         Macv05          = 0x18000000,   /* RTL8169SC/8110SC */
 108         Macv07          = 0x24800000,   /* RTL8102e */
 109         Macv07a         = 0x34800000,   /* RTL8102e */
 110         Macv11          = 0x30000000,   /* RTL8168B/8111B */
 111         Macv12          = 0x38000000,   /* RTL8169B/8111B */
 112         Macv12a         = 0x3c000000,   /* RTL8169C/8111C */
 113         Macv13          = 0x34000000,   /* RTL8101E */
 114         Macv14          = 0x30800000,   /* RTL8100E */
 115         Macv15          = 0x38800000,   /* RTL8100E */
 116 //      Macv19          = 0x3c000000,   /* dup Macv12a: RTL8111c-gr */
 117         Macv25          = 0x28000000,   /* RTL8168D */
 118         Macv26          = 0x48000000,   /* RTL8111/8168B */
 119         Macv27          = 0x2c800000,   /* RTL8111e */
 120         Macv28          = 0x2c000000,   /* RTL8111/8168B */
 121         Macv29          = 0x40800000,   /* RTL8101/8102E */
 122         Macv30          = 0x24000000,   /* RTL8101E? (untested) */
 123         Macv39          = 0x44800000,   /* RTL8106E */
 124         Macv40          = 0x4c000000,   /* RTL8168G */
 125         Macv42          = 0x50800000,   /* RTL8168GU */
 126         Macv44          = 0x5c800000,   /* RTL8411B */
 127         Macv45          = 0x54000000,   /* RTL8111HN */
 128
 129         Ifg0            = 0x01000000,   /* Interframe Gap 0 */
 130         Ifg1            = 0x02000000,   /* Interframe Gap 1 */
 131 };
 132
 133 enum {                                  /* Rcr */
 134         Aap             = 0x00000001,   /* Accept All Packets */
 135         Apm             = 0x00000002,   /* Accept Physical Match */
 136         Am              = 0x00000004,   /* Accept Multicast */
 137         Ab              = 0x00000008,   /* Accept Broadcast */
 138         Ar              = 0x00000010,   /* Accept Runt */
 139         Aer             = 0x00000020,   /* Accept Error */
 140         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
 141         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 142         MrxdmaMASK      = 0x00000700,
 143         Mrxdmaunlimited = 0x00000700,
 144         RxfthSHIFT      = 13,           /* Receive Buffer Length */
 145         RxfthMASK       = 0x0000E000,
 146         Rxfth256        = 0x00008000,
 147         Rxfthnone       = 0x0000E000,
 148         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
 149         MulERINT        = 0x01000000,   /* Multiple Early Interrupt Select */
 150 };
 151
 152 enum {                                  /* Cr9346 */
 153         Eedo            = 0x01,         /* */
 154         Eedi            = 0x02,         /* */
 155         Eesk            = 0x04,         /* */
 156         Eecs            = 0x08,         /* */
 157         Eem0            = 0x40,         /* Operating Mode */
 158         Eem1            = 0x80,
 159 };
 160
 161 enum {                                  /* Phyar */
 162         DataMASK        = 0x0000FFFF,   /* 16-bit GMII/MII Register Data */
 163         DataSHIFT       = 0,
 164         RegaddrMASK     = 0x001F0000,   /* 5-bit GMII/MII Register Address */
 165         RegaddrSHIFT    = 16,
 166         Flag            = 0x80000000,   /* */
 167 };
 168
 169 enum {                                  /* Phystatus */
 170         Fd              = 0x01,         /* Full Duplex */
 171         Linksts         = 0x02,         /* Link Status */
 172         Speed10         = 0x04,         /* */
 173         Speed100        = 0x08,         /* */
 174         Speed1000       = 0x10,         /* */
 175         Rxflow          = 0x20,         /* */
 176         Txflow          = 0x40,         /* */
 177         Entbi           = 0x80,         /* */
 178 };
 179
 180 enum {                                  /* Cplusc */
 181         Txenb           = 0x0001,       /* enable C+ transmit mode */
 182         Rxenb           = 0x0002,       /* enable C+ receive mode */
 183         Mulrw           = 0x0008,       /* PCI Multiple R/W Enable */
 184         Dac             = 0x0010,       /* PCI Dual Address Cycle Enable */
 185         Rxchksum        = 0x0020,       /* Receive Checksum Offload Enable */
 186         Rxvlan          = 0x0040,       /* Receive VLAN De-tagging Enable */
 187         Macstatdis      = 0x0080,       /* Disable Mac Statistics */
 188         Endian          = 0x0200,       /* Endian Mode */
 189 };
 190
 191 typedef struct D D;                     /* Transmit/Receive Descriptor */
 192 struct D {
 193         u32int  control;
 194         u32int  vlan;
 195         u32int  addrlo;
 196         u32int  addrhi;
 197 };
 198
 199 enum {                                  /* Transmit Descriptor control */
 200         TxflMASK        = 0x0000FFFF,   /* Transmit Frame Length */
 201         TxflSHIFT       = 0,
 202         Tcps            = 0x00010000,   /* TCP Checksum Offload */
 203         Udpcs           = 0x00020000,   /* UDP Checksum Offload */
 204         Ipcs            = 0x00040000,   /* IP Checksum Offload */
 205         Lgsen           = 0x08000000,   /* TSO; WARNING: contains lark's vomit */
 206 };
 207
 208 enum {                                  /* Receive Descriptor control */
 209         RxflMASK        = 0x00001FFF,   /* Receive Frame Length */
 210         Tcpf            = 0x00004000,   /* TCP Checksum Failure */
 211         Udpf            = 0x00008000,   /* UDP Checksum Failure */
 212         Ipf             = 0x00010000,   /* IP Checksum Failure */
 213         Pid0            = 0x00020000,   /* Protocol ID0 */
 214         Pid1            = 0x00040000,   /* Protocol ID1 */
 215         Crce            = 0x00080000,   /* CRC Error */
 216         Runt            = 0x00100000,   /* Runt Packet */
 217         Res             = 0x00200000,   /* Receive Error Summary */
 218         Rwt             = 0x00400000,   /* Receive Watchdog Timer Expired */
 219         Fovf            = 0x00800000,   /* FIFO Overflow */
 220         Bovf            = 0x01000000,   /* Buffer Overflow */
 221         Bar             = 0x02000000,   /* Broadcast Address Received */
 222         Pam             = 0x04000000,   /* Physical Address Matched */
 223         Mar             = 0x08000000,   /* Multicast Address Received */
 224 };
 225
 226 enum {                                  /* General Descriptor control */
 227         Ls              = 0x10000000,   /* Last Segment Descriptor */
 228         Fs              = 0x20000000,   /* First Segment Descriptor */
 229         Eor             = 0x40000000,   /* End of Descriptor Ring */
 230         Own             = 0x80000000,   /* Ownership */
 231 };
 232
 233 /*
 234  */
 235 enum {                                  /* Ring sizes  (<= 1024) */
 236         Ntd             = 64,           /* Transmit Ring */
 237         Nrd             = 256,          /* Receive Ring */
 238
 239         Mtu             = ETHERMAXTU,
 240         Mps             = ROUNDUP(ETHERMAXTU+4, 128),
 241 };
 242
 243 typedef struct Dtcc Dtcc;
 244 struct Dtcc {
 245         u64int  txok;
 246         u64int  rxok;
 247         u64int  txer;
 248         u32int  rxer;
 249         u16int  misspkt;
 250         u16int  fae;
 251         u32int  tx1col;
 252         u32int  txmcol;
 253         u64int  rxokph;
 254         u64int  rxokbrd;
 255         u32int  rxokmu;
 256         u16int  txabt;
 257         u16int  txundrn;
 258 };
 259
 260 enum {                                          /* Variants */
 261         Rtl8100e        = (0x8136<<16)|0x10EC,  /* RTL810[01]E: pci -e */
 262         Rtl8169c        = (0x0116<<16)|0x16EC,  /* RTL8169C+ (USR997902) */
 263         Rtl8169sc       = (0x8167<<16)|0x10EC,  /* RTL8169SC */
 264         Rtl8168b        = (0x8168<<16)|0x10EC,  /* RTL8168B: pci-e */
 265         Rtl8169         = (0x8169<<16)|0x10EC,  /* RTL8169 */
 266 };
 267
 268 typedef struct Ctlr Ctlr;
 269 typedef struct Ctlr {
 270         Lock;
 271
 272         int     port;
 273         Pcidev* pcidev;
 274         Ctlr*   next;
 275         int     active;
 276
 277         QLock   alock;                  /* attach */
 278         int     init;                   /*  */
 279         Rendez  reset;
 280
 281         int     pciv;                   /*  */
 282         int     macv;                   /* MAC version */
 283         int     phyv;                   /* PHY version */
 284         int     pcie;                   /* flag: pci-express device? */
 285
 286         uvlong  mchash;                 /* multicast hash */
 287
 288         Mii*    mii;
 289
 290         D*      td;                     /* descriptor ring */
 291         Block** tb;                     /* transmit buffers */
 292         int     ntd;
 293
 294         int     tdh;                    /* head - producer index (host) */
 295         int     tdt;                    /* tail - consumer index (NIC) */
 296         int     ntq;
 297
 298         D*      rd;                     /* descriptor ring */
 299         Block** rb;                     /* receive buffers */
 300         int     nrd;
 301
 302         int     rdh;                    /* head - producer index (NIC) */
 303         int     rdt;                    /* tail - consumer index (host) */
 304         int     nrq;
 305
 306         int     tcr;                    /* transmit configuration register */
 307         int     rcr;                    /* receive configuration register */
 308         int     imr;
 309
 310         QLock   slock;                  /* statistics */
 311         Dtcc*   dtcc;
 312         uint    txdu;
 313         uint    tcpf;
 314         uint    udpf;
 315         uint    ipf;
 316         uint    fovf;
 317         uint    rer;
 318         uint    rdu;
 319         uint    punlc;
 320         uint    serr;
 321         uint    fovw;
 322         uint    mcast;
 323         uint    frag;                   /* partial packets; rb was too small */
 324 } Ctlr;
 325
 326 static Ctlr* rtl8169ctlrhead;
 327 static Ctlr* rtl8169ctlrtail;
 328
 329 #define csr8r(c, r)     (inb((c)->port+(r)))
 330 #define csr16r(c, r)    (ins((c)->port+(r)))
 331 #define csr32r(c, r)    (inl((c)->port+(r)))
 332 #define csr8w(c, r, b)  (outb((c)->port+(r), (u8int)(b)))
 333 #define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w)))
 334 #define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l)))
 335
 336 static int
 337 rtl8169miimir(Mii* mii, int pa, int ra)
 338 {
 339         uint r;
 340         int timeo;
 341         Ctlr *ctlr;
 342
 343         if(pa != 1)
 344                 return -1;
 345         ctlr = mii->ctlr;
 346
 347         r = (ra<<16) & RegaddrMASK;
 348         csr32w(ctlr, Phyar, r);
 349         delay(1);
 350         for(timeo = 0; timeo < 2000; timeo++){
 351                 if((r = csr32r(ctlr, Phyar)) & Flag)
 352                         break;
 353                 microdelay(100);
 354         }
 355         if(!(r & Flag))
 356                 return -1;
 357
 358         return (r & DataMASK)>>DataSHIFT;
 359 }
 360
 361 static int
 362 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
 363 {
 364         uint r;
 365         int timeo;
 366         Ctlr *ctlr;
 367
 368         if(pa != 1)
 369                 return -1;
 370         ctlr = mii->ctlr;
 371
 372         r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
 373         csr32w(ctlr, Phyar, r);
 374         delay(1);
 375         for(timeo = 0; timeo < 2000; timeo++){
 376                 if(!((r = csr32r(ctlr, Phyar)) & Flag))
 377                         break;
 378                 microdelay(100);
 379         }
 380         if(r & Flag)
 381                 return -1;
 382
 383         return 0;
 384 }
 385
 386 static int
 387 rtl8169mii(Ctlr* ctlr)
 388 {
 389         MiiPhy *phy;
 390
 391         /*
 392          * Link management.
 393          */
 394         if((ctlr->mii = malloc(sizeof(Mii))) == nil)
 395                 return -1;
 396         ctlr->mii->mir = rtl8169miimir;
 397         ctlr->mii->miw = rtl8169miimiw;
 398         ctlr->mii->ctlr = ctlr;
 399
 400         /*
 401          * PHY wakeup
 402          */
 403         switch(ctlr->macv){
 404         case Macv25:
 405         case Macv28:
 406         case Macv29:
 407         case Macv30:
 408                 csr8w(ctlr, Pmch, csr8r(ctlr, Pmch) | 0x80);
 409                 break;
 410         }
 411         rtl8169miimiw(ctlr->mii, 1, 0x1f, 0);
 412         rtl8169miimiw(ctlr->mii, 1, 0x0e, 0);
 413
 414         /*
 415          * Get rev number out of Phyidr2 so can config properly.
 416          * There's probably more special stuff for Macv0[234] needed here.
 417          */
 418         ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
 419         if(ctlr->macv == Macv02){
 420                 csr8w(ctlr, Ldps, 1);                           /* magic */
 421                 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);      /* magic */
 422         }
 423
 424         if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
 425                 free(ctlr->mii);
 426                 ctlr->mii = nil;
 427                 return -1;
 428         }
 429         print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 430                 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 431
 432         miireset(ctlr->mii);
 433
 434         microdelay(100);
 435
 436         miiane(ctlr->mii, ~0, ~0, ~0);
 437
 438         return 0;
 439 }
 440
 441 static void
 442 rtl8169promiscuous(void* arg, int on)
 443 {
 444         Ether *edev;
 445         Ctlr * ctlr;
 446
 447         edev = arg;
 448         ctlr = edev->ctlr;
 449         ilock(ctlr);
 450         if(on)
 451                 ctlr->rcr |= Aap;
 452         else
 453                 ctlr->rcr &= ~Aap;
 454         csr32w(ctlr, Rcr, ctlr->rcr);
 455         iunlock(ctlr);
 456 }
 457
 458 enum {
 459         /* everyone else uses 0x04c11db7, but they both produce the same crc */
 460         Etherpolybe = 0x04c11db6,
 461         Bytemask = (1<<8) - 1,
 462 };
 463
 464 static ulong
 465 ethercrcbe(uchar *addr, long len)
 466 {
 467         int i, j;
 468         ulong c, crc, carry;
 469
 470         crc = ~0UL;
 471         for (i = 0; i < len; i++) {
 472                 c = addr[i];
 473                 for (j = 0; j < 8; j++) {
 474                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
 475                         crc <<= 1;
 476                         c >>= 1;
 477                         if (carry)
 478                                 crc = (crc ^ Etherpolybe) | carry;
 479                 }
 480         }
 481         return crc;
 482 }
 483
 484 static ulong
 485 swabl(ulong l)
 486 {
 487         return l>>24 | (l>>8) & (Bytemask<<8) |
 488                 (l<<8) & (Bytemask<<16) | l<<24;
 489 }
 490
 491 static void
 492 rtl8169multicast(void* ether, uchar *eaddr, int add)
 493 {
 494         Ether *edev;
 495         Ctlr *ctlr;
 496
 497         if (!add)
 498                 return; /* ok to keep receiving on old mcast addrs */
 499
 500         edev = ether;
 501         ctlr = edev->ctlr;
 502         ilock(ctlr);
 503
 504         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
 505
 506         ctlr->rcr |= Am;
 507         csr32w(ctlr, Rcr, ctlr->rcr);
 508
 509         /* pci-e variants reverse the order of the hash byte registers */
 510         if (ctlr->pcie) {
 511                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
 512                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
 513         } else {
 514                 csr32w(ctlr, Mar0,   ctlr->mchash);
 515                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
 516         }
 517
 518         iunlock(ctlr);
 519 }
 520
 521 static long
 522 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
 523 {
 524         char *p;
 525         Ctlr *ctlr;
 526         Dtcc *dtcc;
 527         int i, l, r, timeo;
 528
 529         p = smalloc(READSTR);
 530
 531         ctlr = edev->ctlr;
 532         qlock(&ctlr->slock);
 533
 534         if(waserror()){
 535                 qunlock(&ctlr->slock);
 536                 free(p);
 537                 nexterror();
 538         }
 539
 540         csr32w(ctlr, Dtccr+4, 0);
 541         csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd);
 542         for(timeo = 0; timeo < 1000; timeo++){
 543                 if(!(csr32r(ctlr, Dtccr) & Cmd))
 544                         break;
 545                 delay(1);
 546         }
 547         if(csr32r(ctlr, Dtccr) & Cmd)
 548                 error(Eio);
 549         dtcc = ctlr->dtcc;
 550
 551         edev->oerrs = dtcc->txer;
 552         edev->crcs = dtcc->rxer;
 553         edev->frames = dtcc->fae;
 554         edev->buffs = dtcc->misspkt;
 555         edev->overflows = ctlr->txdu+ctlr->rdu;
 556
 557         if(n == 0){
 558                 qunlock(&ctlr->slock);
 559                 poperror();
 560                 free(p);
 561                 return 0;
 562         }
 563
 564         l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
 565         l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
 566         l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
 567         l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
 568         l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
 569         l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
 570         l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
 571         l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
 572         l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
 573         l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
 574         l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
 575         l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
 576         l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
 577
 578         l += snprint(p+l, READSTR-l, "serr: %ud\n", ctlr->serr);
 579         l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
 580
 581         l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
 582         l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
 583         l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
 584         l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
 585         l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
 586         l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
 587         l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
 588         l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
 589
 590         l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
 591         l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
 592         l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
 593
 594         if(ctlr->mii != nil && ctlr->mii->curphy != nil){
 595                 l += snprint(p+l, READSTR-l, "phy:   ");
 596                 for(i = 0; i < NMiiPhyr; i++){
 597                         if(i && ((i & 0x07) == 0))
 598                                 l += snprint(p+l, READSTR-l, "\n       ");
 599                         r = miimir(ctlr->mii, i);
 600                         l += snprint(p+l, READSTR-l, " %4.4ux", r);
 601                 }
 602                 snprint(p+l, READSTR-l, "\n");
 603         }
 604
 605         n = readstr(offset, a, n, p);
 606
 607         qunlock(&ctlr->slock);
 608         poperror();
 609         free(p);
 610
 611         return n;
 612 }
 613
 614 static void
 615 rtl8169halt(Ctlr* ctlr)
 616 {
 617         csr8w(ctlr, Cr, 0);
 618         csr16w(ctlr, Imr, 0);
 619         csr16w(ctlr, Isr, ~0);
 620 }
 621
 622 static int
 623 rtl8169reset(Ctlr* ctlr)
 624 {
 625         u32int r;
 626         int timeo;
 627
 628         /*
 629          * Soft reset the controller.
 630          */
 631         csr8w(ctlr, Cr, Rst);
 632         for(r = timeo = 0; timeo < 1000; timeo++){
 633                 r = csr8r(ctlr, Cr);
 634                 if(!(r & Rst))
 635                         break;
 636                 delay(1);
 637         }
 638         rtl8169halt(ctlr);
 639
 640         if(r & Rst)
 641                 return -1;
 642         return 0;
 643 }
 644
 645 static void
 646 rtl8169replenish(Ctlr* ctlr)
 647 {
 648         D *d;
 649         int x;
 650         Block *bp;
 651
 652         x = ctlr->rdt;
 653         while(NEXT(x, ctlr->nrd) != ctlr->rdh){
 654                 bp = iallocb(Mps);
 655                 if(bp == nil){
 656                         iprint("rtl8169: no available buffers\n");
 657                         break;
 658                 }
 659                 ctlr->rb[x] = bp;
 660                 ctlr->nrq++;
 661                 d = &ctlr->rd[x];
 662                 d->addrlo = PCIWADDR(bp->rp);
 663                 d->addrhi = 0;
 664                 coherence();
 665                 d->control = (d->control & Eor) | Own | BALLOC(bp);
 666                 x = NEXT(x, ctlr->nrd);
 667                 ctlr->rdt = x;
 668         }
 669 }
 670
 671 static int
 672 rtl8169init(Ether* edev)
 673 {
 674         int i;
 675         u32int r;
 676         Block *bp;
 677         Ctlr *ctlr;
 678         u16int cplusc;
 679
 680         ctlr = edev->ctlr;
 681         ilock(ctlr);
 682
 683         rtl8169reset(ctlr);
 684
 685         memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
 686         ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
 687         ctlr->td[ctlr->ntd-1].control = Eor;
 688         for(i = 0; i < ctlr->ntd; i++)
 689                 if(bp = ctlr->tb[i]){
 690                         ctlr->tb[i] = nil;
 691                         freeb(bp);
 692                 }
 693
 694         memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
 695         ctlr->rdh = ctlr->rdt = ctlr->nrq = 0;
 696         ctlr->rd[ctlr->nrd-1].control = Eor;
 697         for(i = 0; i < ctlr->nrd; i++)
 698                 if(bp = ctlr->rb[i]){
 699                         ctlr->rb[i] = nil;
 700                         freeb(bp);
 701                 }
 702
 703         rtl8169replenish(ctlr);
 704
 705         cplusc = csr16r(ctlr, Cplusc);
 706         cplusc &= ~(Endian|Rxchksum);
 707         cplusc |= Txenb|Mulrw;
 708         switch(ctlr->macv){
 709         case Macv40:
 710         case Macv44:
 711                 cplusc |= Macstatdis;
 712                 break;
 713         default:
 714                 cplusc |= Rxenb;
 715                 break;
 716         }
 717         csr16w(ctlr, Cplusc, cplusc);
 718
 719         csr32w(ctlr, Tnpds+4, 0);
 720         csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
 721         csr32w(ctlr, Rdsar+4, 0);
 722         csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
 723
 724         csr8w(ctlr, Cr, Te|Re);
 725
 726         csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
 727         ctlr->tcr = csr32r(ctlr, Tcr);
 728         switch(ctlr->macv){
 729         case Macv45:
 730                 ctlr->rcr = Rxfth256|Mrxdmaunlimited|Ab|Am|Apm;
 731                 break;
 732         default:
 733                 ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
 734                 break;
 735         }
 736         ctlr->mchash = 0;
 737         csr32w(ctlr, Mar0,   0);
 738         csr32w(ctlr, Mar0+4, 0);
 739         csr32w(ctlr, Rcr, ctlr->rcr);
 740
 741         /* maximum packet sizes, unlimited */
 742         csr8w(ctlr, Etx, 0x3f);
 743         csr16w(ctlr, Rms, 0x3fff);
 744
 745         csr16w(ctlr, Coal, 0);
 746
 747         /* no early rx interrupts */
 748         r = csr16r(ctlr, Mulint) & 0xF000;
 749         csr16w(ctlr, Mulint, r);
 750
 751         ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Rer|Rok|Tdu;
 752         csr16w(ctlr, Imr, ctlr->imr);
 753
 754         csr32w(ctlr, Mpc, 0);
 755
 756         iunlock(ctlr);
 757
 758         return 0;
 759 }
 760
 761 static void
 762 rtl8169reseter(void *arg)
 763 {
 764         Ether *edev;
 765         Ctlr *ctlr;
 766
 767         edev = arg;
 768
 769         for(;;){
 770                 rtl8169init(edev);
 771
 772                 ctlr = edev->ctlr;
 773                 qunlock(&ctlr->alock);
 774
 775                 while(waserror())
 776                         ;
 777                 sleep(&ctlr->reset, return0, nil);
 778                 poperror();
 779
 780                 qlock(&ctlr->alock);
 781         }
 782 }
 783
 784 static void
 785 rtl8169attach(Ether* edev)
 786 {
 787         int timeo;
 788         Ctlr *ctlr;
 789
 790         ctlr = edev->ctlr;
 791         qlock(&ctlr->alock);
 792         if(!ctlr->init){
 793                 ctlr->ntd = Ntd;
 794                 ctlr->nrd = Nrd;
 795                 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
 796                 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
 797                 ctlr->td = mallocalign(sizeof(D)*ctlr->ntd, 256, 0, 0);
 798                 ctlr->rd = mallocalign(sizeof(D)*ctlr->nrd, 256, 0, 0);
 799                 ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
 800                 if(ctlr->rb == nil || ctlr->rb == nil ||
 801                    ctlr->rd == nil || ctlr->rd == nil || ctlr->dtcc == nil){
 802                         free(ctlr->tb);
 803                         ctlr->tb = nil;
 804                         free(ctlr->rb);
 805                         ctlr->rb = nil;
 806                         free(ctlr->td);
 807                         ctlr->td = nil;
 808                         free(ctlr->rd);
 809                         ctlr->rd = nil;
 810                         free(ctlr->dtcc);
 811                         ctlr->dtcc = nil;
 812                         qunlock(&ctlr->alock);
 813                         error(Enomem);
 814                 }
 815                 ctlr->init = 1;
 816                 kproc("rtl8169", rtl8169reseter, edev);
 817
 818                 /* rtl8169reseter() does qunlock(&ctlr->alock) when complete */
 819                 qlock(&ctlr->alock);
 820         }
 821         qunlock(&ctlr->alock);
 822
 823         /*
 824          * Wait for link to be ready.
 825          */
 826         for(timeo = 0; timeo < 35; timeo++){
 827                 if(miistatus(ctlr->mii) == 0)
 828                         break;
 829                 delay(100);             /* print fewer miistatus messages */
 830         }
 831 }
 832
 833 static void
 834 rtl8169link(Ether* edev)
 835 {
 836         uint r;
 837         int limit;
 838         Ctlr *ctlr;
 839
 840         ctlr = edev->ctlr;
 841
 842         r = csr8r(ctlr, Phystatus);
 843         /*
 844          * Maybe the link changed - do we care very much?
 845          * Could stall transmits if no link, maybe?
 846          */
 847         edev->link = (r & Linksts) != 0;
 848
 849         limit = 256*1024;
 850         if(r & Speed10){
 851                 edev->mbps = 10;
 852                 limit = 65*1024;
 853         } else if(r & Speed100)
 854                 edev->mbps = 100;
 855         else if(r & Speed1000)
 856                 edev->mbps = 1000;
 857
 858         if(edev->oq != nil)
 859                 qsetlimit(edev->oq, limit);
 860 }
 861
 862 static void
 863 rtl8169transmit(Ether* edev)
 864 {
 865         D *d;
 866         Block *bp;
 867         Ctlr *ctlr;
 868         int x;
 869
 870         ctlr = edev->ctlr;
 871
 872         if(!canlock(ctlr))
 873                 return;
 874         for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
 875                 d = &ctlr->td[x];
 876                 if(d->control & Own)
 877                         break;
 878
 879                 /*
 880                  * Free it up.
 881                  * Need to clean the descriptor here? Not really.
 882                  * Simple freeb for now (no chain and freeblist).
 883                  * Use ntq count for now.
 884                  */
 885                 freeb(ctlr->tb[x]);
 886                 ctlr->tb[x] = nil;
 887                 ctlr->ntq--;
 888         }
 889         ctlr->tdh = x;
 890
 891         x = ctlr->tdt;
 892         while(ctlr->ntq < (ctlr->ntd-1)){
 893                 if((bp = qget(edev->oq)) == nil)
 894                         break;
 895
 896                 d = &ctlr->td[x];
 897                 d->addrlo = PCIWADDR(bp->rp);
 898                 d->addrhi = 0;
 899                 coherence();
 900                 d->control = (d->control & Eor) | Own | Fs | Ls | BLEN(bp);
 901
 902                 ctlr->tb[x] = bp;
 903                 ctlr->ntq++;
 904
 905                 x = NEXT(x, ctlr->ntd);
 906         }
 907         if(x != ctlr->tdt)
 908                 ctlr->tdt = x;
 909         else if(ctlr->ntq >= (ctlr->ntd-1))
 910                 ctlr->txdu++;
 911
 912         if(ctlr->ntq > 0){
 913                 coherence();
 914                 csr8w(ctlr, Tppoll, Npq);
 915         }
 916         unlock(ctlr);
 917 }
 918
 919 static void
 920 rtl8169receive(Ether* edev)
 921 {
 922         D *d;
 923         Block *bp;
 924         Ctlr *ctlr;
 925         u32int control;
 926         int x;
 927
 928         ctlr = edev->ctlr;
 929         if(ctlr->nrq < ctlr->nrd/2)
 930                 rtl8169replenish(ctlr);
 931
 932         for(x = ctlr->rdh; x != ctlr->rdt;){
 933                 d = &ctlr->rd[x];
 934                 if((control = d->control) & Own)
 935                         break;
 936
 937                 bp = ctlr->rb[x];
 938                 ctlr->rb[x] = nil;
 939                 ctlr->nrq--;
 940
 941                 x = NEXT(x, ctlr->nrd);
 942                 ctlr->rdh = x;
 943
 944                 if(ctlr->nrq < ctlr->nrd/2)
 945                         rtl8169replenish(ctlr);
 946
 947                 if((control & (Fs|Ls|Res)) == (Fs|Ls)){
 948                         bp->wp = bp->rp + (control & RxflMASK) - 4;
 949
 950                         if(control & Fovf)
 951                                 ctlr->fovf++;
 952                         if(control & Mar)
 953                                 ctlr->mcast++;
 954
 955                         switch(control & (Pid1|Pid0)){
 956                         default:
 957                                 break;
 958                         case Pid0:
 959                                 if(control & Tcpf){
 960                                         ctlr->tcpf++;
 961                                         break;
 962                                 }
 963                                 bp->flag |= Btcpck;
 964                                 break;
 965                         case Pid1:
 966                                 if(control & Udpf){
 967                                         ctlr->udpf++;
 968                                         break;
 969                                 }
 970                                 bp->flag |= Budpck;
 971                                 break;
 972                         case Pid1|Pid0:
 973                                 if(control & Ipf){
 974                                         ctlr->ipf++;
 975                                         break;
 976                                 }
 977                                 bp->flag |= Bipck;
 978                                 break;
 979                         }
 980                         etheriq(edev, bp);
 981                 }else{
 982                         if(!(control & Res))
 983                                 ctlr->frag++;
 984                         freeb(bp);
 985                 }
 986         }
 987 }
 988
 989 static void
 990 rtl8169restart(Ctlr *ctlr)
 991 {
 992         ctlr->imr = 0;
 993         rtl8169halt(ctlr);
 994         wakeup(&ctlr->reset);
 995 }
 996
 997 static void
 998 rtl8169interrupt(Ureg*, void* arg)
 999 {
1000         Ctlr *ctlr;
1001         Ether *edev;
1002         u32int isr;
1003
1004         edev = arg;
1005         ctlr = edev->ctlr;
1006
1007         while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
1008                 csr16w(ctlr, Isr, isr);
1009                 if((isr & ctlr->imr) == 0)
1010                         break;
1011
1012                 if(isr & Serr)
1013                         ctlr->serr++;
1014                 if(isr & Fovw)
1015                         ctlr->fovw++;
1016                 if(isr & Rer)
1017                         ctlr->rer++;
1018                 if(isr & Rdu)
1019                         ctlr->rdu++;
1020                 if(isr & Punlc)
1021                         ctlr->punlc++;
1022
1023                 if(isr & (Serr|Fovw)){
1024                         rtl8169restart(ctlr);
1025                         break;
1026                 }
1027
1028                 if(isr & (Punlc|Rdu|Rer|Rok))
1029                         rtl8169receive(edev);
1030
1031                 if(isr & (Tdu|Ter|Tok))
1032                         rtl8169transmit(edev);
1033
1034                 if(isr & Punlc)
1035                         rtl8169link(edev);
1036         }
1037 }
1038
1039 int
1040 vetmacv(Ctlr *ctlr, uint *macv)
1041 {
1042         *macv = csr32r(ctlr, Tcr) & HwveridMASK;
1043         switch(*macv){
1044         default:
1045                 return -1;
1046         case Macv01:
1047         case Macv02:
1048         case Macv03:
1049         case Macv04:
1050         case Macv05:
1051         case Macv07:
1052         case Macv07a:
1053         case Macv11:
1054         case Macv12:
1055         case Macv12a:
1056         case Macv13:
1057         case Macv14:
1058         case Macv15:
1059         case Macv25:
1060         case Macv26:
1061         case Macv27:
1062         case Macv28:
1063         case Macv29:
1064         case Macv30:
1065         case Macv39:
1066         case Macv40:
1067         case Macv42:
1068         case Macv44:
1069         case Macv45:
1070                 break;
1071         }
1072         return 0;
1073 }
1074
1075 static void
1076 rtl8169pci(void)
1077 {
1078         Pcidev *p;
1079         Ctlr *ctlr;
1080         int i, port, pcie;
1081         uint macv;
1082
1083         p = nil;
1084         while(p = pcimatch(p, 0, 0)){
1085                 if(p->ccrb != 0x02 || p->ccru != 0)
1086                         continue;
1087
1088                 pcie = 0;
1089                 switch(i = ((p->did<<16)|p->vid)){
1090                 default:
1091                         continue;
1092                 case Rtl8100e:                  /* RTL810[01]E ? */
1093                 case Rtl8168b:                  /* RTL8168B */
1094                         pcie = 1;
1095                         break;
1096                 case Rtl8169c:                  /* RTL8169C */
1097                 case Rtl8169sc:                 /* RTL8169SC */
1098                 case Rtl8169:                   /* RTL8169 */
1099                         break;
1100                 case (0xC107<<16)|0x1259:       /* Corega CG-LAPCIGT */
1101                         i = Rtl8169;
1102                         break;
1103                 }
1104
1105                 port = p->mem[0].bar & ~0x01;
1106                 if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
1107                         print("rtl8169: port %#ux in use\n", port);
1108                         continue;
1109                 }
1110                 ctlr = malloc(sizeof(Ctlr));
1111                 if(ctlr == nil){
1112                         print("rtl8169: can't allocate memory\n");
1113                         iofree(port);
1114                         continue;
1115                 }
1116                 ctlr->port = port;
1117                 ctlr->pcidev = p;
1118                 ctlr->pciv = i;
1119                 ctlr->pcie = pcie;
1120
1121                 if(vetmacv(ctlr, &macv) == -1){
1122                         iofree(port);
1123                         free(ctlr);
1124                         print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1125                         continue;
1126                 }
1127
1128                 if(pcigetpms(p) > 0){
1129                         pcisetpms(p, 0);
1130
1131                         for(i = 0; i < 6; i++)
1132                                 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1133                         pcicfgw8(p, PciINTL, p->intl);
1134                         pcicfgw8(p, PciLTR, p->ltr);
1135                         pcicfgw8(p, PciCLS, p->cls);
1136                         pcicfgw16(p, PciPCR, p->pcr);
1137                 }
1138
1139                 if(rtl8169reset(ctlr)){
1140                         iofree(port);
1141                         free(ctlr);
1142                         print("rtl8169: reset failed\n");
1143                         continue;
1144                 }
1145
1146                 /*
1147                  * Extract the chip hardware version,
1148                  * needed to configure each properly.
1149                  */
1150                 ctlr->macv = macv;
1151
1152                 rtl8169mii(ctlr);
1153
1154                 pcisetbme(p);
1155
1156                 if(rtl8169ctlrhead != nil)
1157                         rtl8169ctlrtail->next = ctlr;
1158                 else
1159                         rtl8169ctlrhead = ctlr;
1160                 rtl8169ctlrtail = ctlr;
1161         }
1162 }
1163
1164 static int
1165 rtl8169pnp(Ether* edev)
1166 {
1167         u32int r;
1168         Ctlr *ctlr;
1169         uchar ea[Eaddrlen];
1170         static int once;
1171
1172         if(once == 0){
1173                 once = 1;
1174                 rtl8169pci();
1175         }
1176
1177         /*
1178          * Any adapter matches if no edev->port is supplied,
1179          * otherwise the ports must match.
1180          */
1181         for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1182                 if(ctlr->active)
1183                         continue;
1184                 if(edev->port == 0 || edev->port == ctlr->port){
1185                         ctlr->active = 1;
1186                         break;
1187                 }
1188         }
1189         if(ctlr == nil)
1190                 return -1;
1191
1192         edev->ctlr = ctlr;
1193         edev->port = ctlr->port;
1194         edev->irq = ctlr->pcidev->intl;
1195         edev->tbdf = ctlr->pcidev->tbdf;
1196         edev->mbps = 100;
1197         edev->maxmtu = Mtu;
1198
1199         /*
1200          * Check if the adapter's station address is to be overridden.
1201          * If not, read it from the device and set in edev->ea.
1202          */
1203         memset(ea, 0, Eaddrlen);
1204         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1205                 r = csr32r(ctlr, Idr0);
1206                 edev->ea[0] = r;
1207                 edev->ea[1] = r>>8;
1208                 edev->ea[2] = r>>16;
1209                 edev->ea[3] = r>>24;
1210                 r = csr32r(ctlr, Idr0+4);
1211                 edev->ea[4] = r;
1212                 edev->ea[5] = r>>8;
1213         }
1214
1215         edev->attach = rtl8169attach;
1216         edev->transmit = rtl8169transmit;
1217         edev->ifstat = rtl8169ifstat;
1218
1219         edev->arg = edev;
1220         edev->promiscuous = rtl8169promiscuous;
1221         edev->multicast = rtl8169multicast;
1222
1223         rtl8169link(edev);
1224
1225         intrenable(edev->irq, rtl8169interrupt, edev, edev->tbdf, edev->name);
1226
1227         return 0;
1228 }
1229
1230 void
1231 ether8169link(void)
1232 {
1233         addethercard("rtl8169", rtl8169pnp);
1234 }