sys/src/9/pc/ether8169.c

   1 /*
   2  * Realtek RTL8110S/8169S Gigabit Ethernet Controllers.
   3  * Mostly there. There are some magic register values used
   4  * which are not described in any datasheet or driver but seem
   5  * to be necessary.
   6  * No tuning has been done. Only tested on an RTL8110S, there
   7  * are slight differences between the chips in the series so some
   8  * tweaks may be needed.
   9  */
  10 #include "u.h"
  11 #include "../port/lib.h"
  12 #include "mem.h"
  13 #include "dat.h"
  14 #include "fns.h"
  15 #include "io.h"
  16 #include "../port/error.h"
  17 #include "../port/netif.h"
  18
  19 #include "etherif.h"
  20 #include "ethermii.h"
  21
  22 enum {                                  /* registers */
  23         Idr0            = 0x00,         /* MAC address */
  24         Mar0            = 0x08,         /* Multicast address */
  25         Dtccr           = 0x10,         /* Dump Tally Counter Command */
  26         Tnpds           = 0x20,         /* Transmit Normal Priority Descriptors */
  27         Thpds           = 0x28,         /* Transmit High Priority Descriptors */
  28         Flash           = 0x30,         /* Flash Memory Read/Write */
  29         Erbcr           = 0x34,         /* Early Receive Byte Count */
  30         Ersr            = 0x36,         /* Early Receive Status */
  31         Cr              = 0x37,         /* Command Register */
  32         Tppoll          = 0x38,         /* Transmit Priority Polling */
  33         Imr             = 0x3C,         /* Interrupt Mask */
  34         Isr             = 0x3E,         /* Interrupt Status */
  35         Tcr             = 0x40,         /* Transmit Configuration */
  36         Rcr             = 0x44,         /* Receive Configuration */
  37         Tctr            = 0x48,         /* Timer Count */
  38         Mpc             = 0x4C,         /* Missed Packet Counter */
  39         Cr9346          = 0x50,         /* 9346 Command Register */
  40         Config0         = 0x51,         /* Configuration Register 0 */
  41         Config1         = 0x52,         /* Configuration Register 1 */
  42         Config2         = 0x53,         /* Configuration Register 2 */
  43         Config3         = 0x54,         /* Configuration Register 3 */
  44         Config4         = 0x55,         /* Configuration Register 4 */
  45         Config5         = 0x56,         /* Configuration Register 5 */
  46         Timerint        = 0x58,         /* Timer Interrupt */
  47         Mulint          = 0x5C,         /* Multiple Interrupt Select */
  48         Phyar           = 0x60,         /* PHY Access */
  49         Tbicsr0         = 0x64,         /* TBI Control and Status */
  50         Tbianar         = 0x68,         /* TBI Auto-Negotiation Advertisment */
  51         Tbilpar         = 0x6A,         /* TBI Auto-Negotiation Link Partner */
  52         Phystatus       = 0x6C,         /* PHY Status */
  53
  54         Rms             = 0xDA,         /* Receive Packet Maximum Size */
  55         Cplusc          = 0xE0,         /* C+ Command */
  56         Coal            = 0xE2,         /* Interrupt Mitigation (Coalesce) */
  57         Rdsar           = 0xE4,         /* Receive Descriptor Start Address */
  58         Etx             = 0xEC,         /* Early Transmit Threshold */
  59 };
  60
  61 enum {                                  /* Dtccr */
  62         Cmd             = 0x00000008,   /* Command */
  63 };
  64
  65 enum {                                  /* Cr */
  66         Te              = 0x04,         /* Transmitter Enable */
  67         Re              = 0x08,         /* Receiver Enable */
  68         Rst             = 0x10,         /* Software Reset */
  69 };
  70
  71 enum {                                  /* Tppoll */
  72         Fswint          = 0x01,         /* Forced Software Interrupt */
  73         Npq             = 0x40,         /* Normal Priority Queue polling */
  74         Hpq             = 0x80,         /* High Priority Queue polling */
  75 };
  76
  77 enum {                                  /* Imr/Isr */
  78         Rok             = 0x0001,       /* Receive OK */
  79         Rer             = 0x0002,       /* Receive Error */
  80         Tok             = 0x0004,       /* Transmit OK */
  81         Ter             = 0x0008,       /* Transmit Error */
  82         Rdu             = 0x0010,       /* Receive Descriptor Unavailable */
  83         Punlc           = 0x0020,       /* Packet Underrun or Link Change */
  84         Fovw            = 0x0040,       /* Receive FIFO Overflow */
  85         Tdu             = 0x0080,       /* Transmit Descriptor Unavailable */
  86         Swint           = 0x0100,       /* Software Interrupt */
  87         Timeout         = 0x4000,       /* Timer */
  88         Serr            = 0x8000,       /* System Error */
  89 };
  90
  91 enum {                                  /* Tcr */
  92         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
  93         MtxdmaMASK      = 0x00000700,
  94         Mtxdmaunlimited = 0x00000700,
  95         Acrc            = 0x00010000,   /* Append CRC (not) */
  96         Lbk0            = 0x00020000,   /* Loopback Test 0 */
  97         Lbk1            = 0x00040000,   /* Loopback Test 1 */
  98         Ifg2            = 0x00080000,   /* Interframe Gap 2 */
  99         HwveridSHIFT    = 23,           /* Hardware Version ID */
 100         HwveridMASK     = 0x7C800000,
 101         Macv01          = 0x00000000,   /* RTL8169 */
 102         Macv02          = 0x00800000,   /* RTL8169S/8110S */
 103         Macv03          = 0x04000000,   /* RTL8169S/8110S */
 104         Macv04          = 0x10000000,   /* RTL8169SB/8110SB */
 105         Macv05          = 0x18000000,   /* RTL8169SC/8110SC */
 106         Macv07          = 0x24800000,   /* RTL8102e */
 107         Macv07a         = 0x34800000,   /* RTL8102e */
 108         Macv11          = 0x30000000,   /* RTL8168B/8111B */
 109         Macv12          = 0x38000000,   /* RTL8169B/8111B */
 110         Macv12a         = 0x3c000000,   /* RTL8169C/8111C */
 111         Macv13          = 0x34000000,   /* RTL8101E */
 112         Macv14          = 0x30800000,   /* RTL8100E */
 113         Macv15          = 0x38800000,   /* RTL8100E */
 114 //      Macv19          = 0x3c000000,   /* dup Macv12a: RTL8111c-gr */
 115         Macv25          = 0x28000000,   /* RTL8168D */
 116         Macv26          = 0x48000000,   /* RTL8111/8168B */
 117         Ifg0            = 0x01000000,   /* Interframe Gap 0 */
 118         Ifg1            = 0x02000000,   /* Interframe Gap 1 */
 119 };
 120
 121 enum {                                  /* Rcr */
 122         Aap             = 0x00000001,   /* Accept All Packets */
 123         Apm             = 0x00000002,   /* Accept Physical Match */
 124         Am              = 0x00000004,   /* Accept Multicast */
 125         Ab              = 0x00000008,   /* Accept Broadcast */
 126         Ar              = 0x00000010,   /* Accept Runt */
 127         Aer             = 0x00000020,   /* Accept Error */
 128         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
 129         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 130         MrxdmaMASK      = 0x00000700,
 131         Mrxdmaunlimited = 0x00000700,
 132         RxfthSHIFT      = 13,           /* Receive Buffer Length */
 133         RxfthMASK       = 0x0000E000,
 134         Rxfth256        = 0x00008000,
 135         Rxfthnone       = 0x0000E000,
 136         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
 137         MulERINT        = 0x01000000,   /* Multiple Early Interrupt Select */
 138 };
 139
 140 enum {                                  /* Cr9346 */
 141         Eedo            = 0x01,         /* */
 142         Eedi            = 0x02,         /* */
 143         Eesk            = 0x04,         /* */
 144         Eecs            = 0x08,         /* */
 145         Eem0            = 0x40,         /* Operating Mode */
 146         Eem1            = 0x80,
 147 };
 148
 149 enum {                                  /* Phyar */
 150         DataMASK        = 0x0000FFFF,   /* 16-bit GMII/MII Register Data */
 151         DataSHIFT       = 0,
 152         RegaddrMASK     = 0x001F0000,   /* 5-bit GMII/MII Register Address */
 153         RegaddrSHIFT    = 16,
 154         Flag            = 0x80000000,   /* */
 155 };
 156
 157 enum {                                  /* Phystatus */
 158         Fd              = 0x01,         /* Full Duplex */
 159         Linksts         = 0x02,         /* Link Status */
 160         Speed10         = 0x04,         /* */
 161         Speed100        = 0x08,         /* */
 162         Speed1000       = 0x10,         /* */
 163         Rxflow          = 0x20,         /* */
 164         Txflow          = 0x40,         /* */
 165         Entbi           = 0x80,         /* */
 166 };
 167
 168 enum {                                  /* Cplusc */
 169         Txenb           = 0x0001,       /* enable C+ transmit mode */
 170         Rxenb           = 0x0002,       /* enable C+ receive mode */
 171         Mulrw           = 0x0008,       /* PCI Multiple R/W Enable */
 172         Dac             = 0x0010,       /* PCI Dual Address Cycle Enable */
 173         Rxchksum        = 0x0020,       /* Receive Checksum Offload Enable */
 174         Rxvlan          = 0x0040,       /* Receive VLAN De-tagging Enable */
 175         Endian          = 0x0200,       /* Endian Mode */
 176 };
 177
 178 typedef struct D D;                     /* Transmit/Receive Descriptor */
 179 struct D {
 180         u32int  control;
 181         u32int  vlan;
 182         u32int  addrlo;
 183         u32int  addrhi;
 184 };
 185
 186 enum {                                  /* Transmit Descriptor control */
 187         TxflMASK        = 0x0000FFFF,   /* Transmit Frame Length */
 188         TxflSHIFT       = 0,
 189         Tcps            = 0x00010000,   /* TCP Checksum Offload */
 190         Udpcs           = 0x00020000,   /* UDP Checksum Offload */
 191         Ipcs            = 0x00040000,   /* IP Checksum Offload */
 192         Lgsen           = 0x08000000,   /* TSO; WARNING: contains lark's vomit */
 193 };
 194
 195 enum {                                  /* Receive Descriptor control */
 196         RxflMASK        = 0x00001FFF,   /* Receive Frame Length */
 197         Tcpf            = 0x00004000,   /* TCP Checksum Failure */
 198         Udpf            = 0x00008000,   /* UDP Checksum Failure */
 199         Ipf             = 0x00010000,   /* IP Checksum Failure */
 200         Pid0            = 0x00020000,   /* Protocol ID0 */
 201         Pid1            = 0x00040000,   /* Protocol ID1 */
 202         Crce            = 0x00080000,   /* CRC Error */
 203         Runt            = 0x00100000,   /* Runt Packet */
 204         Res             = 0x00200000,   /* Receive Error Summary */
 205         Rwt             = 0x00400000,   /* Receive Watchdog Timer Expired */
 206         Fovf            = 0x00800000,   /* FIFO Overflow */
 207         Bovf            = 0x01000000,   /* Buffer Overflow */
 208         Bar             = 0x02000000,   /* Broadcast Address Received */
 209         Pam             = 0x04000000,   /* Physical Address Matched */
 210         Mar             = 0x08000000,   /* Multicast Address Received */
 211 };
 212
 213 enum {                                  /* General Descriptor control */
 214         Ls              = 0x10000000,   /* Last Segment Descriptor */
 215         Fs              = 0x20000000,   /* First Segment Descriptor */
 216         Eor             = 0x40000000,   /* End of Descriptor Ring */
 217         Own             = 0x80000000,   /* Ownership */
 218 };
 219
 220 /*
 221  */
 222 enum {                                  /* Ring sizes  (<= 1024) */
 223         Ntd             = 64,           /* Transmit Ring */
 224         Nrd             = 256,          /* Receive Ring */
 225
 226         Mtu             = ETHERMAXTU,
 227         Mps             = ROUNDUP(ETHERMAXTU+4, 128),
 228 };
 229
 230 typedef struct Dtcc Dtcc;
 231 struct Dtcc {
 232         u64int  txok;
 233         u64int  rxok;
 234         u64int  txer;
 235         u32int  rxer;
 236         u16int  misspkt;
 237         u16int  fae;
 238         u32int  tx1col;
 239         u32int  txmcol;
 240         u64int  rxokph;
 241         u64int  rxokbrd;
 242         u32int  rxokmu;
 243         u16int  txabt;
 244         u16int  txundrn;
 245 };
 246
 247 enum {                                          /* Variants */
 248         Rtl8100e        = (0x8136<<16)|0x10EC,  /* RTL810[01]E: pci -e */
 249         Rtl8169c        = (0x0116<<16)|0x16EC,  /* RTL8169C+ (USR997902) */
 250         Rtl8169sc       = (0x8167<<16)|0x10EC,  /* RTL8169SC */
 251         Rtl8168b        = (0x8168<<16)|0x10EC,  /* RTL8168B: pci-e */
 252         Rtl8169         = (0x8169<<16)|0x10EC,  /* RTL8169 */
 253 };
 254
 255 typedef struct Ctlr Ctlr;
 256 typedef struct Ctlr {
 257         Lock;
 258
 259         int     port;
 260         Pcidev* pcidev;
 261         Ctlr*   next;
 262         int     active;
 263
 264         QLock   alock;                  /* attach */
 265         int     init;                   /*  */
 266         Rendez  reset;
 267
 268         int     pciv;                   /*  */
 269         int     macv;                   /* MAC version */
 270         int     phyv;                   /* PHY version */
 271         int     pcie;                   /* flag: pci-express device? */
 272
 273         uvlong  mchash;                 /* multicast hash */
 274
 275         Mii*    mii;
 276
 277         D*      td;                     /* descriptor ring */
 278         Block** tb;                     /* transmit buffers */
 279         int     ntd;
 280
 281         int     tdh;                    /* head - producer index (host) */
 282         int     tdt;                    /* tail - consumer index (NIC) */
 283         int     ntq;
 284
 285         D*      rd;                     /* descriptor ring */
 286         Block** rb;                     /* receive buffers */
 287         int     nrd;
 288
 289         int     rdh;                    /* head - producer index (NIC) */
 290         int     rdt;                    /* tail - consumer index (host) */
 291         int     nrq;
 292
 293         int     tcr;                    /* transmit configuration register */
 294         int     rcr;                    /* receive configuration register */
 295         int     imr;
 296
 297         QLock   slock;                  /* statistics */
 298         Dtcc*   dtcc;
 299         uint    txdu;
 300         uint    tcpf;
 301         uint    udpf;
 302         uint    ipf;
 303         uint    fovf;
 304         uint    rer;
 305         uint    rdu;
 306         uint    punlc;
 307         uint    serr;
 308         uint    fovw;
 309         uint    mcast;
 310         uint    frag;                   /* partial packets; rb was too small */
 311 } Ctlr;
 312
 313 static Ctlr* rtl8169ctlrhead;
 314 static Ctlr* rtl8169ctlrtail;
 315
 316 #define csr8r(c, r)     (inb((c)->port+(r)))
 317 #define csr16r(c, r)    (ins((c)->port+(r)))
 318 #define csr32r(c, r)    (inl((c)->port+(r)))
 319 #define csr8w(c, r, b)  (outb((c)->port+(r), (u8int)(b)))
 320 #define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w)))
 321 #define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l)))
 322
 323 static int
 324 rtl8169miimir(Mii* mii, int pa, int ra)
 325 {
 326         uint r;
 327         int timeo;
 328         Ctlr *ctlr;
 329
 330         if(pa != 1)
 331                 return -1;
 332         ctlr = mii->ctlr;
 333
 334         r = (ra<<16) & RegaddrMASK;
 335         csr32w(ctlr, Phyar, r);
 336         delay(1);
 337         for(timeo = 0; timeo < 2000; timeo++){
 338                 if((r = csr32r(ctlr, Phyar)) & Flag)
 339                         break;
 340                 microdelay(100);
 341         }
 342         if(!(r & Flag))
 343                 return -1;
 344
 345         return (r & DataMASK)>>DataSHIFT;
 346 }
 347
 348 static int
 349 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
 350 {
 351         uint r;
 352         int timeo;
 353         Ctlr *ctlr;
 354
 355         if(pa != 1)
 356                 return -1;
 357         ctlr = mii->ctlr;
 358
 359         r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
 360         csr32w(ctlr, Phyar, r);
 361         delay(1);
 362         for(timeo = 0; timeo < 2000; timeo++){
 363                 if(!((r = csr32r(ctlr, Phyar)) & Flag))
 364                         break;
 365                 microdelay(100);
 366         }
 367         if(r & Flag)
 368                 return -1;
 369
 370         return 0;
 371 }
 372
 373 static int
 374 rtl8169mii(Ctlr* ctlr)
 375 {
 376         MiiPhy *phy;
 377
 378         /*
 379          * Link management.
 380          */
 381         if((ctlr->mii = malloc(sizeof(Mii))) == nil)
 382                 return -1;
 383         ctlr->mii->mir = rtl8169miimir;
 384         ctlr->mii->miw = rtl8169miimiw;
 385         ctlr->mii->ctlr = ctlr;
 386
 387         /*
 388          * Get rev number out of Phyidr2 so can config properly.
 389          * There's probably more special stuff for Macv0[234] needed here.
 390          */
 391         ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
 392         if(ctlr->macv == Macv02){
 393                 csr8w(ctlr, 0x82, 1);                           /* magic */
 394                 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);      /* magic */
 395         }
 396
 397         if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
 398                 free(ctlr->mii);
 399                 ctlr->mii = nil;
 400                 return -1;
 401         }
 402         print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 403                 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 404
 405         miiane(ctlr->mii, ~0, ~0, ~0);
 406
 407         return 0;
 408 }
 409
 410 static void
 411 rtl8169promiscuous(void* arg, int on)
 412 {
 413         Ether *edev;
 414         Ctlr * ctlr;
 415
 416         edev = arg;
 417         ctlr = edev->ctlr;
 418         ilock(ctlr);
 419         if(on)
 420                 ctlr->rcr |= Aap;
 421         else
 422                 ctlr->rcr &= ~Aap;
 423         csr32w(ctlr, Rcr, ctlr->rcr);
 424         iunlock(ctlr);
 425 }
 426
 427 enum {
 428         /* everyone else uses 0x04c11db7, but they both produce the same crc */
 429         Etherpolybe = 0x04c11db6,
 430         Bytemask = (1<<8) - 1,
 431 };
 432
 433 static ulong
 434 ethercrcbe(uchar *addr, long len)
 435 {
 436         int i, j;
 437         ulong c, crc, carry;
 438
 439         crc = ~0UL;
 440         for (i = 0; i < len; i++) {
 441                 c = addr[i];
 442                 for (j = 0; j < 8; j++) {
 443                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
 444                         crc <<= 1;
 445                         c >>= 1;
 446                         if (carry)
 447                                 crc = (crc ^ Etherpolybe) | carry;
 448                 }
 449         }
 450         return crc;
 451 }
 452
 453 static ulong
 454 swabl(ulong l)
 455 {
 456         return l>>24 | (l>>8) & (Bytemask<<8) |
 457                 (l<<8) & (Bytemask<<16) | l<<24;
 458 }
 459
 460 static void
 461 rtl8169multicast(void* ether, uchar *eaddr, int add)
 462 {
 463         Ether *edev;
 464         Ctlr *ctlr;
 465
 466         if (!add)
 467                 return; /* ok to keep receiving on old mcast addrs */
 468
 469         edev = ether;
 470         ctlr = edev->ctlr;
 471         ilock(ctlr);
 472
 473         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
 474
 475         ctlr->rcr |= Am;
 476         csr32w(ctlr, Rcr, ctlr->rcr);
 477
 478         /* pci-e variants reverse the order of the hash byte registers */
 479         if (ctlr->pcie) {
 480                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
 481                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
 482         } else {
 483                 csr32w(ctlr, Mar0,   ctlr->mchash);
 484                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
 485         }
 486
 487         iunlock(ctlr);
 488 }
 489
 490 static long
 491 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
 492 {
 493         char *p;
 494         Ctlr *ctlr;
 495         Dtcc *dtcc;
 496         int i, l, r, timeo;
 497
 498         p = smalloc(READSTR);
 499
 500         ctlr = edev->ctlr;
 501         qlock(&ctlr->slock);
 502
 503         if(waserror()){
 504                 qunlock(&ctlr->slock);
 505                 free(p);
 506                 nexterror();
 507         }
 508
 509         csr32w(ctlr, Dtccr+4, 0);
 510         csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd);
 511         for(timeo = 0; timeo < 1000; timeo++){
 512                 if(!(csr32r(ctlr, Dtccr) & Cmd))
 513                         break;
 514                 delay(1);
 515         }
 516         if(csr32r(ctlr, Dtccr) & Cmd)
 517                 error(Eio);
 518         dtcc = ctlr->dtcc;
 519
 520         edev->oerrs = dtcc->txer;
 521         edev->crcs = dtcc->rxer;
 522         edev->frames = dtcc->fae;
 523         edev->buffs = dtcc->misspkt;
 524         edev->overflows = ctlr->txdu+ctlr->rdu;
 525
 526         if(n == 0){
 527                 qunlock(&ctlr->slock);
 528                 poperror();
 529                 free(p);
 530                 return 0;
 531         }
 532
 533         l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
 534         l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
 535         l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
 536         l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
 537         l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
 538         l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
 539         l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
 540         l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
 541         l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
 542         l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
 543         l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
 544         l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
 545         l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
 546
 547         l += snprint(p+l, READSTR-l, "serr: %ud\n", ctlr->serr);
 548         l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
 549
 550         l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
 551         l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
 552         l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
 553         l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
 554         l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
 555         l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
 556         l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
 557         l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
 558
 559         l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
 560         l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
 561         l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
 562
 563         if(ctlr->mii != nil && ctlr->mii->curphy != nil){
 564                 l += snprint(p+l, READSTR, "phy:   ");
 565                 for(i = 0; i < NMiiPhyr; i++){
 566                         if(i && ((i & 0x07) == 0))
 567                                 l += snprint(p+l, READSTR-l, "\n       ");
 568                         r = miimir(ctlr->mii, i);
 569                         l += snprint(p+l, READSTR-l, " %4.4ux", r);
 570                 }
 571                 snprint(p+l, READSTR-l, "\n");
 572         }
 573
 574         n = readstr(offset, a, n, p);
 575
 576         qunlock(&ctlr->slock);
 577         poperror();
 578         free(p);
 579
 580         return n;
 581 }
 582
 583 static void
 584 rtl8169halt(Ctlr* ctlr)
 585 {
 586         csr8w(ctlr, Cr, 0);
 587         csr16w(ctlr, Imr, 0);
 588         csr16w(ctlr, Isr, ~0);
 589 }
 590
 591 static int
 592 rtl8169reset(Ctlr* ctlr)
 593 {
 594         u32int r;
 595         int timeo;
 596
 597         /*
 598          * Soft reset the controller.
 599          */
 600         csr8w(ctlr, Cr, Rst);
 601         for(r = timeo = 0; timeo < 1000; timeo++){
 602                 r = csr8r(ctlr, Cr);
 603                 if(!(r & Rst))
 604                         break;
 605                 delay(1);
 606         }
 607         rtl8169halt(ctlr);
 608
 609         if(r & Rst)
 610                 return -1;
 611         return 0;
 612 }
 613
 614 static void
 615 rtl8169replenish(Ctlr* ctlr)
 616 {
 617         D *d;
 618         int x;
 619         Block *bp;
 620
 621         x = ctlr->rdt;
 622         while(NEXT(x, ctlr->nrd) != ctlr->rdh){
 623                 bp = iallocb(Mps);
 624                 if(bp == nil){
 625                         iprint("rtl8169: no available buffers\n");
 626                         break;
 627                 }
 628                 ctlr->rb[x] = bp;
 629                 ctlr->nrq++;
 630                 d = &ctlr->rd[x];
 631                 d->addrlo = PCIWADDR(bp->rp);
 632                 d->addrhi = 0;
 633                 coherence();
 634                 d->control = (d->control & Eor) | Own | BALLOC(bp);
 635                 x = NEXT(x, ctlr->nrd);
 636                 ctlr->rdt = x;
 637         }
 638 }
 639
 640 static int
 641 rtl8169init(Ether* edev)
 642 {
 643         int i;
 644         u32int r;
 645         Block *bp;
 646         Ctlr *ctlr;
 647         u8int cplusc;
 648
 649         ctlr = edev->ctlr;
 650         ilock(ctlr);
 651
 652         rtl8169reset(ctlr);
 653
 654         memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
 655         ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
 656         ctlr->td[ctlr->ntd-1].control = Eor;
 657         for(i = 0; i < ctlr->ntd; i++)
 658                 if(bp = ctlr->tb[i]){
 659                         ctlr->tb[i] = nil;
 660                         freeb(bp);
 661                 }
 662
 663         memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
 664         ctlr->rdh = ctlr->rdt = ctlr->nrq = 0;
 665         ctlr->rd[ctlr->nrd-1].control = Eor;
 666         for(i = 0; i < ctlr->nrd; i++)
 667                 if(bp = ctlr->rb[i]){
 668                         ctlr->rb[i] = nil;
 669                         freeb(bp);
 670                 }
 671
 672         rtl8169replenish(ctlr);
 673
 674         cplusc = csr16r(ctlr, Cplusc);
 675         cplusc &= ~(Endian|Rxchksum);
 676         cplusc |= Txenb|Rxenb|Mulrw;
 677         csr16w(ctlr, Cplusc, cplusc);
 678
 679         csr32w(ctlr, Tnpds+4, 0);
 680         csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
 681         csr32w(ctlr, Rdsar+4, 0);
 682         csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
 683
 684         csr8w(ctlr, Cr, Te|Re);
 685
 686         csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
 687         ctlr->tcr = csr32r(ctlr, Tcr);
 688         ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
 689         ctlr->mchash = 0;
 690         csr32w(ctlr, Mar0,   0);
 691         csr32w(ctlr, Mar0+4, 0);
 692         csr32w(ctlr, Rcr, ctlr->rcr);
 693
 694         /* maximum packet sizes, unlimited */
 695         csr8w(ctlr, Etx, 0x3f);
 696         csr16w(ctlr, Rms, 0x3fff);
 697
 698         csr16w(ctlr, Coal, 0);
 699
 700         /* no early rx interrupts */
 701         r = csr16r(ctlr, Mulint) & 0xF000;
 702         csr16w(ctlr, Mulint, r);
 703
 704         ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Rer|Rok|Tdu;
 705         csr16w(ctlr, Imr, ctlr->imr);
 706
 707         csr32w(ctlr, Mpc, 0);
 708
 709         iunlock(ctlr);
 710
 711         return 0;
 712 }
 713
 714 static void
 715 rtl8169reseter(void *arg)
 716 {
 717         Ether *edev;
 718         Ctlr *ctlr;
 719
 720         edev = arg;
 721
 722         for(;;){
 723                 rtl8169init(edev);
 724
 725                 ctlr = edev->ctlr;
 726                 qunlock(&ctlr->alock);
 727
 728                 while(waserror())
 729                         ;
 730                 sleep(&ctlr->reset, return0, nil);
 731                 poperror();
 732
 733                 qlock(&ctlr->alock);
 734         }
 735 }
 736
 737 static void
 738 rtl8169attach(Ether* edev)
 739 {
 740         int timeo;
 741         Ctlr *ctlr;
 742
 743         ctlr = edev->ctlr;
 744         qlock(&ctlr->alock);
 745         if(!ctlr->init){
 746                 ctlr->ntd = Ntd;
 747                 ctlr->nrd = Nrd;
 748                 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
 749                 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
 750                 ctlr->td = mallocalign(sizeof(D)*ctlr->ntd, 256, 0, 0);
 751                 ctlr->rd = mallocalign(sizeof(D)*ctlr->nrd, 256, 0, 0);
 752                 ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
 753                 if(ctlr->rb == nil || ctlr->rb == nil ||
 754                    ctlr->rd == nil || ctlr->rd == nil || ctlr->dtcc == nil){
 755                         free(ctlr->tb);
 756                         ctlr->tb = nil;
 757                         free(ctlr->rb);
 758                         ctlr->rb = nil;
 759                         free(ctlr->td);
 760                         ctlr->td = nil;
 761                         free(ctlr->rd);
 762                         ctlr->rd = nil;
 763                         free(ctlr->dtcc);
 764                         ctlr->dtcc = nil;
 765                         qlock(&ctlr->alock);
 766                         error(Enomem);
 767                 }
 768                 ctlr->init = 1;
 769                 kproc("rtl8169", rtl8169reseter, edev);
 770                 qlock(&ctlr->alock);
 771         }
 772         qunlock(&ctlr->alock);
 773
 774         /*
 775          * Wait for link to be ready.
 776          */
 777         for(timeo = 0; timeo < 35; timeo++){
 778                 if(miistatus(ctlr->mii) == 0)
 779                         break;
 780                 delay(100);             /* print fewer miistatus messages */
 781         }
 782 }
 783
 784 static void
 785 rtl8169link(Ether* edev)
 786 {
 787         uint r;
 788         int limit;
 789         Ctlr *ctlr;
 790
 791         ctlr = edev->ctlr;
 792
 793         /*
 794          * Maybe the link changed - do we care very much?
 795          * Could stall transmits if no link, maybe?
 796          */
 797         if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
 798                 edev->link = 0;
 799                 return;
 800         }
 801         edev->link = 1;
 802
 803         limit = 256*1024;
 804         if(r & Speed10){
 805                 edev->mbps = 10;
 806                 limit = 65*1024;
 807         } else if(r & Speed100)
 808                 edev->mbps = 100;
 809         else if(r & Speed1000)
 810                 edev->mbps = 1000;
 811
 812         if(edev->oq != nil)
 813                 qsetlimit(edev->oq, limit);
 814 }
 815
 816 static void
 817 rtl8169transmit(Ether* edev)
 818 {
 819         D *d;
 820         Block *bp;
 821         Ctlr *ctlr;
 822         int x;
 823
 824         ctlr = edev->ctlr;
 825
 826         if(!canlock(ctlr))
 827                 return;
 828         for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
 829                 d = &ctlr->td[x];
 830                 if(d->control & Own)
 831                         break;
 832
 833                 /*
 834                  * Free it up.
 835                  * Need to clean the descriptor here? Not really.
 836                  * Simple freeb for now (no chain and freeblist).
 837                  * Use ntq count for now.
 838                  */
 839                 freeb(ctlr->tb[x]);
 840                 ctlr->tb[x] = nil;
 841                 ctlr->ntq--;
 842         }
 843         ctlr->tdh = x;
 844
 845         x = ctlr->tdt;
 846         while(ctlr->ntq < (ctlr->ntd-1)){
 847                 if((bp = qget(edev->oq)) == nil)
 848                         break;
 849
 850                 d = &ctlr->td[x];
 851                 d->addrlo = PCIWADDR(bp->rp);
 852                 d->addrhi = 0;
 853                 coherence();
 854                 d->control = (d->control & Eor) | Own | Fs | Ls | BLEN(bp);
 855
 856                 ctlr->tb[x] = bp;
 857                 ctlr->ntq++;
 858
 859                 x = NEXT(x, ctlr->ntd);
 860         }
 861         if(x != ctlr->tdt)
 862                 ctlr->tdt = x;
 863         else if(ctlr->ntq >= (ctlr->ntd-1))
 864                 ctlr->txdu++;
 865
 866         if(ctlr->ntq > 0){
 867                 coherence();
 868                 csr8w(ctlr, Tppoll, Npq);
 869         }
 870         unlock(ctlr);
 871 }
 872
 873 static void
 874 rtl8169receive(Ether* edev)
 875 {
 876         D *d;
 877         Block *bp;
 878         Ctlr *ctlr;
 879         u32int control;
 880         int x;
 881
 882         ctlr = edev->ctlr;
 883         x = ctlr->rdh;
 884         for(;;){
 885                 d = &ctlr->rd[x];
 886                 if((control = d->control) & Own)
 887                         break;
 888
 889                 bp = ctlr->rb[x];
 890                 ctlr->rb[x] = nil;
 891                 ctlr->nrq--;
 892
 893                 x = NEXT(x, ctlr->nrd);
 894                 ctlr->rdh = x;
 895
 896                 if(ctlr->nrq < ctlr->nrd/2)
 897                         rtl8169replenish(ctlr);
 898
 899                 if((control & (Fs|Ls|Res)) == (Fs|Ls)){
 900                         bp->wp = bp->rp + (control & RxflMASK) - 4;
 901
 902                         if(control & Fovf)
 903                                 ctlr->fovf++;
 904                         if(control & Mar)
 905                                 ctlr->mcast++;
 906
 907                         switch(control & (Pid1|Pid0)){
 908                         default:
 909                                 break;
 910                         case Pid0:
 911                                 if(control & Tcpf){
 912                                         ctlr->tcpf++;
 913                                         break;
 914                                 }
 915                                 bp->flag |= Btcpck;
 916                                 break;
 917                         case Pid1:
 918                                 if(control & Udpf){
 919                                         ctlr->udpf++;
 920                                         break;
 921                                 }
 922                                 bp->flag |= Budpck;
 923                                 break;
 924                         case Pid1|Pid0:
 925                                 if(control & Ipf){
 926                                         ctlr->ipf++;
 927                                         break;
 928                                 }
 929                                 bp->flag |= Bipck;
 930                                 break;
 931                         }
 932                         etheriq(edev, bp, 1);
 933                 }else{
 934                         if(!(control & Res))
 935                                 ctlr->frag++;
 936                         freeb(bp);
 937                 }
 938         }
 939 }
 940
 941 static void
 942 rtl8169restart(Ctlr *ctlr)
 943 {
 944         ctlr->imr = 0;
 945         rtl8169halt(ctlr);
 946         wakeup(&ctlr->reset);
 947 }
 948
 949 static void
 950 rtl8169interrupt(Ureg*, void* arg)
 951 {
 952         Ctlr *ctlr;
 953         Ether *edev;
 954         u32int isr;
 955
 956         edev = arg;
 957         ctlr = edev->ctlr;
 958
 959         while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
 960                 csr16w(ctlr, Isr, isr);
 961                 if((isr & ctlr->imr) == 0)
 962                         break;
 963
 964                 if(isr & Serr)
 965                         ctlr->serr++;
 966                 if(isr & Fovw)
 967                         ctlr->fovw++;
 968                 if(isr & Rer)
 969                         ctlr->rer++;
 970                 if(isr & Rdu)
 971                         ctlr->rdu++;
 972                 if(isr & Punlc)
 973                         ctlr->punlc++;
 974
 975                 if(isr & (Serr|Fovw)){
 976                         rtl8169restart(ctlr);
 977                         break;
 978                 }
 979
 980                 if(isr & (Punlc|Rdu|Rer|Rok))
 981                         rtl8169receive(edev);
 982
 983                 if(isr & (Tdu|Ter|Tok))
 984                         rtl8169transmit(edev);
 985
 986                 if(isr & Punlc)
 987                         rtl8169link(edev);
 988         }
 989 }
 990
 991 int
 992 vetmacv(Ctlr *ctlr, uint *macv)
 993 {
 994         *macv = csr32r(ctlr, Tcr) & HwveridMASK;
 995         switch(*macv){
 996         default:
 997                 return -1;
 998         case Macv01:
 999         case Macv02:
1000         case Macv03:
1001         case Macv04:
1002         case Macv05:
1003         case Macv07:
1004         case Macv07a:
1005         case Macv11:
1006         case Macv12:
1007         case Macv12a:
1008         case Macv13:
1009         case Macv14:
1010         case Macv15:
1011         case Macv25:
1012         case Macv26:
1013                 break;
1014         }
1015         return 0;
1016 }
1017
1018 static void
1019 rtl8169pci(void)
1020 {
1021         Pcidev *p;
1022         Ctlr *ctlr;
1023         int i, port, pcie;
1024         uint macv;
1025
1026         p = nil;
1027         while(p = pcimatch(p, 0, 0)){
1028                 if(p->ccrb != 0x02 || p->ccru != 0)
1029                         continue;
1030
1031                 pcie = 0;
1032                 switch(i = ((p->did<<16)|p->vid)){
1033                 default:
1034                         continue;
1035                 case Rtl8100e:                  /* RTL810[01]E ? */
1036                 case Rtl8168b:                  /* RTL8168B */
1037                         pcie = 1;
1038                         break;
1039                 case Rtl8169c:                  /* RTL8169C */
1040                 case Rtl8169sc:                 /* RTL8169SC */
1041                 case Rtl8169:                   /* RTL8169 */
1042                         break;
1043                 case (0xC107<<16)|0x1259:       /* Corega CG-LAPCIGT */
1044                         i = Rtl8169;
1045                         break;
1046                 }
1047
1048                 port = p->mem[0].bar & ~0x01;
1049                 if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
1050                         print("rtl8169: port %#ux in use\n", port);
1051                         continue;
1052                 }
1053                 ctlr = malloc(sizeof(Ctlr));
1054                 if(ctlr == nil){
1055                         print("rtl8169: can't allocate memory\n");
1056                         iofree(port);
1057                         continue;
1058                 }
1059                 ctlr->port = port;
1060                 ctlr->pcidev = p;
1061                 ctlr->pciv = i;
1062                 ctlr->pcie = pcie;
1063
1064                 if(vetmacv(ctlr, &macv) == -1){
1065                         iofree(port);
1066                         free(ctlr);
1067                         print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1068                         continue;
1069                 }
1070
1071                 if(pcigetpms(p) > 0){
1072                         pcisetpms(p, 0);
1073
1074                         for(i = 0; i < 6; i++)
1075                                 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1076                         pcicfgw8(p, PciINTL, p->intl);
1077                         pcicfgw8(p, PciLTR, p->ltr);
1078                         pcicfgw8(p, PciCLS, p->cls);
1079                         pcicfgw16(p, PciPCR, p->pcr);
1080                 }
1081
1082                 if(rtl8169reset(ctlr)){
1083                         iofree(port);
1084                         free(ctlr);
1085                         print("rtl8169: reset failed\n");
1086                         continue;
1087                 }
1088
1089                 /*
1090                  * Extract the chip hardware version,
1091                  * needed to configure each properly.
1092                  */
1093                 ctlr->macv = macv;
1094
1095                 rtl8169mii(ctlr);
1096
1097                 pcisetbme(p);
1098
1099                 if(rtl8169ctlrhead != nil)
1100                         rtl8169ctlrtail->next = ctlr;
1101                 else
1102                         rtl8169ctlrhead = ctlr;
1103                 rtl8169ctlrtail = ctlr;
1104         }
1105 }
1106
1107 static int
1108 rtl8169pnp(Ether* edev)
1109 {
1110         u32int r;
1111         Ctlr *ctlr;
1112         uchar ea[Eaddrlen];
1113         static int once;
1114
1115         if(once == 0){
1116                 once = 1;
1117                 rtl8169pci();
1118         }
1119
1120         /*
1121          * Any adapter matches if no edev->port is supplied,
1122          * otherwise the ports must match.
1123          */
1124         for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1125                 if(ctlr->active)
1126                         continue;
1127                 if(edev->port == 0 || edev->port == ctlr->port){
1128                         ctlr->active = 1;
1129                         break;
1130                 }
1131         }
1132         if(ctlr == nil)
1133                 return -1;
1134
1135         edev->ctlr = ctlr;
1136         edev->port = ctlr->port;
1137         edev->irq = ctlr->pcidev->intl;
1138         edev->tbdf = ctlr->pcidev->tbdf;
1139         edev->mbps = 100;
1140         edev->maxmtu = Mtu;
1141
1142         /*
1143          * Check if the adapter's station address is to be overridden.
1144          * If not, read it from the device and set in edev->ea.
1145          */
1146         memset(ea, 0, Eaddrlen);
1147         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1148                 r = csr32r(ctlr, Idr0);
1149                 edev->ea[0] = r;
1150                 edev->ea[1] = r>>8;
1151                 edev->ea[2] = r>>16;
1152                 edev->ea[3] = r>>24;
1153                 r = csr32r(ctlr, Idr0+4);
1154                 edev->ea[4] = r;
1155                 edev->ea[5] = r>>8;
1156         }
1157
1158         edev->attach = rtl8169attach;
1159         edev->transmit = rtl8169transmit;
1160         edev->interrupt = rtl8169interrupt;
1161         edev->ifstat = rtl8169ifstat;
1162
1163         edev->arg = edev;
1164         edev->promiscuous = rtl8169promiscuous;
1165         edev->multicast = rtl8169multicast;
1166
1167         rtl8169link(edev);
1168
1169         return 0;
1170 }
1171
1172 void
1173 ether8169link(void)
1174 {
1175         addethercard("rtl8169", rtl8169pnp);
1176 }