sys/src/9/pc/ether8169.c

   1 /*
   2  * Realtek RTL8110S/8169S Gigabit Ethernet Controllers.
   3  * Mostly there. There are some magic register values used
   4  * which are not described in any datasheet or driver but seem
   5  * to be necessary.
   6  * No tuning has been done. Only tested on an RTL8110S, there
   7  * are slight differences between the chips in the series so some
   8  * tweaks may be needed.
   9  */
  10 #include "u.h"
  11 #include "../port/lib.h"
  12 #include "mem.h"
  13 #include "dat.h"
  14 #include "fns.h"
  15 #include "io.h"
  16 #include "../port/error.h"
  17 #include "../port/netif.h"
  18 #include "../port/etherif.h"
  19 #include "../port/ethermii.h"
  20
  21 enum {                                  /* registers */
  22         Idr0            = 0x00,         /* MAC address */
  23         Mar0            = 0x08,         /* Multicast address */
  24         Dtccr           = 0x10,         /* Dump Tally Counter Command */
  25         Tnpds           = 0x20,         /* Transmit Normal Priority Descriptors */
  26         Thpds           = 0x28,         /* Transmit High Priority Descriptors */
  27         Flash           = 0x30,         /* Flash Memory Read/Write */
  28         Erbcr           = 0x34,         /* Early Receive Byte Count */
  29         Ersr            = 0x36,         /* Early Receive Status */
  30         Cr              = 0x37,         /* Command Register */
  31         Tppoll          = 0x38,         /* Transmit Priority Polling */
  32         Imr             = 0x3C,         /* Interrupt Mask */
  33         Isr             = 0x3E,         /* Interrupt Status */
  34         Tcr             = 0x40,         /* Transmit Configuration */
  35         Rcr             = 0x44,         /* Receive Configuration */
  36         Tctr            = 0x48,         /* Timer Count */
  37         Mpc             = 0x4C,         /* Missed Packet Counter */
  38         Cr9346          = 0x50,         /* 9346 Command Register */
  39         Config0         = 0x51,         /* Configuration Register 0 */
  40         Config1         = 0x52,         /* Configuration Register 1 */
  41         Config2         = 0x53,         /* Configuration Register 2 */
  42         Config3         = 0x54,         /* Configuration Register 3 */
  43         Config4         = 0x55,         /* Configuration Register 4 */
  44         Config5         = 0x56,         /* Configuration Register 5 */
  45         Timerint        = 0x58,         /* Timer Interrupt */
  46         Mulint          = 0x5C,         /* Multiple Interrupt Select */
  47         Phyar           = 0x60,         /* PHY Access */
  48         Tbicsr0         = 0x64,         /* TBI Control and Status */
  49         Tbianar         = 0x68,         /* TBI Auto-Negotiation Advertisment */
  50         Tbilpar         = 0x6A,         /* TBI Auto-Negotiation Link Partner */
  51         Phystatus       = 0x6C,         /* PHY Status */
  52         Pmch            = 0x6F,         /* power management */
  53         Ldps            = 0x82,         /* link down power saving */
  54
  55         Rms             = 0xDA,         /* Receive Packet Maximum Size */
  56         Cplusc          = 0xE0,         /* C+ Command */
  57         Coal            = 0xE2,         /* Interrupt Mitigation (Coalesce) */
  58         Rdsar           = 0xE4,         /* Receive Descriptor Start Address */
  59         Etx             = 0xEC,         /* Early Transmit Threshold */
  60 };
  61
  62 enum {                                  /* Dtccr */
  63         Cmd             = 0x00000008,   /* Command */
  64 };
  65
  66 enum {                                  /* Cr */
  67         Te              = 0x04,         /* Transmitter Enable */
  68         Re              = 0x08,         /* Receiver Enable */
  69         Rst             = 0x10,         /* Software Reset */
  70 };
  71
  72 enum {                                  /* Tppoll */
  73         Fswint          = 0x01,         /* Forced Software Interrupt */
  74         Npq             = 0x40,         /* Normal Priority Queue polling */
  75         Hpq             = 0x80,         /* High Priority Queue polling */
  76 };
  77
  78 enum {                                  /* Imr/Isr */
  79         Rok             = 0x0001,       /* Receive OK */
  80         Rer             = 0x0002,       /* Receive Error */
  81         Tok             = 0x0004,       /* Transmit OK */
  82         Ter             = 0x0008,       /* Transmit Error */
  83         Rdu             = 0x0010,       /* Receive Descriptor Unavailable */
  84         Punlc           = 0x0020,       /* Packet Underrun or Link Change */
  85         Fovw            = 0x0040,       /* Receive FIFO Overflow */
  86         Tdu             = 0x0080,       /* Transmit Descriptor Unavailable */
  87         Swint           = 0x0100,       /* Software Interrupt */
  88         Timeout         = 0x4000,       /* Timer */
  89         Serr            = 0x8000,       /* System Error */
  90 };
  91
  92 enum {                                  /* Tcr */
  93         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
  94         MtxdmaMASK      = 0x00000700,
  95         Mtxdmaunlimited = 0x00000700,
  96         Acrc            = 0x00010000,   /* Append CRC (not) */
  97         Lbk0            = 0x00020000,   /* Loopback Test 0 */
  98         Lbk1            = 0x00040000,   /* Loopback Test 1 */
  99         Ifg2            = 0x00080000,   /* Interframe Gap 2 */
 100         HwveridSHIFT    = 23,           /* Hardware Version ID */
 101         HwveridMASK     = 0x7C800000,
 102         Macv01          = 0x00000000,   /* RTL8169 */
 103         Macv02          = 0x00800000,   /* RTL8169S/8110S */
 104         Macv03          = 0x04000000,   /* RTL8169S/8110S */
 105         Macv04          = 0x10000000,   /* RTL8169SB/8110SB */
 106         Macv05          = 0x18000000,   /* RTL8169SC/8110SC */
 107         Macv07          = 0x24800000,   /* RTL8102e */
 108         Macv07a         = 0x34800000,   /* RTL8102e */
 109         Macv11          = 0x30000000,   /* RTL8168B/8111B */
 110         Macv12          = 0x38000000,   /* RTL8169B/8111B */
 111         Macv12a         = 0x3c000000,   /* RTL8169C/8111C */
 112         Macv13          = 0x34000000,   /* RTL8101E */
 113         Macv14          = 0x30800000,   /* RTL8100E */
 114         Macv15          = 0x38800000,   /* RTL8100E */
 115 //      Macv19          = 0x3c000000,   /* dup Macv12a: RTL8111c-gr */
 116         Macv25          = 0x28000000,   /* RTL8168D */
 117         Macv26          = 0x48000000,   /* RTL8111/8168B */
 118         Macv27          = 0x2c800000,   /* RTL8111e */
 119         Macv28          = 0x2c000000,   /* RTL8111/8168B */
 120         Macv29          = 0x40800000,   /* RTL8101/8102E */
 121         Macv30          = 0x24000000,   /* RTL8101E? (untested) */
 122         Macv39          = 0x44800000,   /* RTL8106E */
 123         Macv40          = 0x4c000000,   /* RTL8168G */
 124         Macv42          = 0x50800000,   /* RTL8168GU */
 125         Macv44          = 0x5c800000,   /* RTL8411B */
 126         Macv45          = 0x54000000,   /* RTL8111HN */
 127
 128         Ifg0            = 0x01000000,   /* Interframe Gap 0 */
 129         Ifg1            = 0x02000000,   /* Interframe Gap 1 */
 130 };
 131
 132 enum {                                  /* Rcr */
 133         Aap             = 0x00000001,   /* Accept All Packets */
 134         Apm             = 0x00000002,   /* Accept Physical Match */
 135         Am              = 0x00000004,   /* Accept Multicast */
 136         Ab              = 0x00000008,   /* Accept Broadcast */
 137         Ar              = 0x00000010,   /* Accept Runt */
 138         Aer             = 0x00000020,   /* Accept Error */
 139         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
 140         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 141         MrxdmaMASK      = 0x00000700,
 142         Mrxdmaunlimited = 0x00000700,
 143         RxfthSHIFT      = 13,           /* Receive Buffer Length */
 144         RxfthMASK       = 0x0000E000,
 145         Rxfth256        = 0x00008000,
 146         Rxfthnone       = 0x0000E000,
 147         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
 148         MulERINT        = 0x01000000,   /* Multiple Early Interrupt Select */
 149 };
 150
 151 enum {                                  /* Cr9346 */
 152         Eedo            = 0x01,         /* */
 153         Eedi            = 0x02,         /* */
 154         Eesk            = 0x04,         /* */
 155         Eecs            = 0x08,         /* */
 156         Eem0            = 0x40,         /* Operating Mode */
 157         Eem1            = 0x80,
 158 };
 159
 160 enum {                                  /* Phyar */
 161         DataMASK        = 0x0000FFFF,   /* 16-bit GMII/MII Register Data */
 162         DataSHIFT       = 0,
 163         RegaddrMASK     = 0x001F0000,   /* 5-bit GMII/MII Register Address */
 164         RegaddrSHIFT    = 16,
 165         Flag            = 0x80000000,   /* */
 166 };
 167
 168 enum {                                  /* Phystatus */
 169         Fd              = 0x01,         /* Full Duplex */
 170         Linksts         = 0x02,         /* Link Status */
 171         Speed10         = 0x04,         /* */
 172         Speed100        = 0x08,         /* */
 173         Speed1000       = 0x10,         /* */
 174         Rxflow          = 0x20,         /* */
 175         Txflow          = 0x40,         /* */
 176         Entbi           = 0x80,         /* */
 177 };
 178
 179 enum {                                  /* Cplusc */
 180         Txenb           = 0x0001,       /* enable C+ transmit mode */
 181         Rxenb           = 0x0002,       /* enable C+ receive mode */
 182         Mulrw           = 0x0008,       /* PCI Multiple R/W Enable */
 183         Dac             = 0x0010,       /* PCI Dual Address Cycle Enable */
 184         Rxchksum        = 0x0020,       /* Receive Checksum Offload Enable */
 185         Rxvlan          = 0x0040,       /* Receive VLAN De-tagging Enable */
 186         Macstatdis      = 0x0080,       /* Disable Mac Statistics */
 187         Endian          = 0x0200,       /* Endian Mode */
 188 };
 189
 190 typedef struct D D;                     /* Transmit/Receive Descriptor */
 191 struct D {
 192         u32int  control;
 193         u32int  vlan;
 194         u32int  addrlo;
 195         u32int  addrhi;
 196 };
 197
 198 enum {                                  /* Transmit Descriptor control */
 199         TxflMASK        = 0x0000FFFF,   /* Transmit Frame Length */
 200         TxflSHIFT       = 0,
 201         Tcps            = 0x00010000,   /* TCP Checksum Offload */
 202         Udpcs           = 0x00020000,   /* UDP Checksum Offload */
 203         Ipcs            = 0x00040000,   /* IP Checksum Offload */
 204         Lgsen           = 0x08000000,   /* TSO; WARNING: contains lark's vomit */
 205 };
 206
 207 enum {                                  /* Receive Descriptor control */
 208         RxflMASK        = 0x00001FFF,   /* Receive Frame Length */
 209         Tcpf            = 0x00004000,   /* TCP Checksum Failure */
 210         Udpf            = 0x00008000,   /* UDP Checksum Failure */
 211         Ipf             = 0x00010000,   /* IP Checksum Failure */
 212         Pid0            = 0x00020000,   /* Protocol ID0 */
 213         Pid1            = 0x00040000,   /* Protocol ID1 */
 214         Crce            = 0x00080000,   /* CRC Error */
 215         Runt            = 0x00100000,   /* Runt Packet */
 216         Res             = 0x00200000,   /* Receive Error Summary */
 217         Rwt             = 0x00400000,   /* Receive Watchdog Timer Expired */
 218         Fovf            = 0x00800000,   /* FIFO Overflow */
 219         Bovf            = 0x01000000,   /* Buffer Overflow */
 220         Bar             = 0x02000000,   /* Broadcast Address Received */
 221         Pam             = 0x04000000,   /* Physical Address Matched */
 222         Mar             = 0x08000000,   /* Multicast Address Received */
 223 };
 224
 225 enum {                                  /* General Descriptor control */
 226         Ls              = 0x10000000,   /* Last Segment Descriptor */
 227         Fs              = 0x20000000,   /* First Segment Descriptor */
 228         Eor             = 0x40000000,   /* End of Descriptor Ring */
 229         Own             = 0x80000000,   /* Ownership */
 230 };
 231
 232 /*
 233  */
 234 enum {                                  /* Ring sizes  (<= 1024) */
 235         Ntd             = 64,           /* Transmit Ring */
 236         Nrd             = 256,          /* Receive Ring */
 237
 238         Mtu             = ETHERMAXTU,
 239         Mps             = ROUNDUP(ETHERMAXTU+4, 128),
 240 };
 241
 242 typedef struct Dtcc Dtcc;
 243 struct Dtcc {
 244         u64int  txok;
 245         u64int  rxok;
 246         u64int  txer;
 247         u32int  rxer;
 248         u16int  misspkt;
 249         u16int  fae;
 250         u32int  tx1col;
 251         u32int  txmcol;
 252         u64int  rxokph;
 253         u64int  rxokbrd;
 254         u32int  rxokmu;
 255         u16int  txabt;
 256         u16int  txundrn;
 257 };
 258
 259 enum {                                          /* Variants */
 260         Rtl8100e        = (0x8136<<16)|0x10EC,  /* RTL810[01]E: pci -e */
 261         Rtl8169c        = (0x0116<<16)|0x16EC,  /* RTL8169C+ (USR997902) */
 262         Rtl8169sc       = (0x8167<<16)|0x10EC,  /* RTL8169SC */
 263         Rtl8168b        = (0x8168<<16)|0x10EC,  /* RTL8168B: pci-e */
 264         Rtl8169         = (0x8169<<16)|0x10EC,  /* RTL8169 */
 265 };
 266
 267 typedef struct Ctlr Ctlr;
 268 typedef struct Ctlr {
 269         Lock;
 270
 271         int     port;
 272         Pcidev* pcidev;
 273         Ctlr*   next;
 274         int     active;
 275
 276         QLock   alock;                  /* attach */
 277         int     init;                   /*  */
 278         Rendez  reset;
 279
 280         int     pciv;                   /*  */
 281         int     macv;                   /* MAC version */
 282         int     phyv;                   /* PHY version */
 283         int     pcie;                   /* flag: pci-express device? */
 284
 285         uvlong  mchash;                 /* multicast hash */
 286
 287         Mii*    mii;
 288
 289         D*      td;                     /* descriptor ring */
 290         Block** tb;                     /* transmit buffers */
 291         int     ntd;
 292
 293         int     tdh;                    /* head - producer index (host) */
 294         int     tdt;                    /* tail - consumer index (NIC) */
 295         int     ntq;
 296
 297         D*      rd;                     /* descriptor ring */
 298         Block** rb;                     /* receive buffers */
 299         int     nrd;
 300
 301         int     rdh;                    /* head - producer index (NIC) */
 302         int     rdt;                    /* tail - consumer index (host) */
 303         int     nrq;
 304
 305         int     tcr;                    /* transmit configuration register */
 306         int     rcr;                    /* receive configuration register */
 307         int     imr;
 308
 309         QLock   slock;                  /* statistics */
 310         Dtcc*   dtcc;
 311         uint    txdu;
 312         uint    tcpf;
 313         uint    udpf;
 314         uint    ipf;
 315         uint    fovf;
 316         uint    rer;
 317         uint    rdu;
 318         uint    punlc;
 319         uint    serr;
 320         uint    fovw;
 321         uint    mcast;
 322         uint    frag;                   /* partial packets; rb was too small */
 323 } Ctlr;
 324
 325 static Ctlr* rtl8169ctlrhead;
 326 static Ctlr* rtl8169ctlrtail;
 327
 328 #define csr8r(c, r)     (inb((c)->port+(r)))
 329 #define csr16r(c, r)    (ins((c)->port+(r)))
 330 #define csr32r(c, r)    (inl((c)->port+(r)))
 331 #define csr8w(c, r, b)  (outb((c)->port+(r), (u8int)(b)))
 332 #define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w)))
 333 #define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l)))
 334
 335 static int
 336 rtl8169miimir(Mii* mii, int pa, int ra)
 337 {
 338         uint r;
 339         int timeo;
 340         Ctlr *ctlr;
 341
 342         if(pa != 1)
 343                 return -1;
 344         ctlr = mii->ctlr;
 345
 346         r = (ra<<16) & RegaddrMASK;
 347         csr32w(ctlr, Phyar, r);
 348         delay(1);
 349         for(timeo = 0; timeo < 2000; timeo++){
 350                 if((r = csr32r(ctlr, Phyar)) & Flag)
 351                         break;
 352                 microdelay(100);
 353         }
 354         if(!(r & Flag))
 355                 return -1;
 356
 357         return (r & DataMASK)>>DataSHIFT;
 358 }
 359
 360 static int
 361 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
 362 {
 363         uint r;
 364         int timeo;
 365         Ctlr *ctlr;
 366
 367         if(pa != 1)
 368                 return -1;
 369         ctlr = mii->ctlr;
 370
 371         r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
 372         csr32w(ctlr, Phyar, r);
 373         delay(1);
 374         for(timeo = 0; timeo < 2000; timeo++){
 375                 if(!((r = csr32r(ctlr, Phyar)) & Flag))
 376                         break;
 377                 microdelay(100);
 378         }
 379         if(r & Flag)
 380                 return -1;
 381
 382         return 0;
 383 }
 384
 385 static int
 386 rtl8169mii(Ctlr* ctlr)
 387 {
 388         MiiPhy *phy;
 389
 390         /*
 391          * Link management.
 392          */
 393         if((ctlr->mii = malloc(sizeof(Mii))) == nil)
 394                 return -1;
 395         ctlr->mii->mir = rtl8169miimir;
 396         ctlr->mii->miw = rtl8169miimiw;
 397         ctlr->mii->ctlr = ctlr;
 398
 399         /*
 400          * PHY wakeup
 401          */
 402         switch(ctlr->macv){
 403         case Macv25:
 404         case Macv28:
 405         case Macv29:
 406         case Macv30:
 407                 csr8w(ctlr, Pmch, csr8r(ctlr, Pmch) | 0x80);
 408                 break;
 409         }
 410         rtl8169miimiw(ctlr->mii, 1, 0x1f, 0);
 411         rtl8169miimiw(ctlr->mii, 1, 0x0e, 0);
 412
 413         /*
 414          * Get rev number out of Phyidr2 so can config properly.
 415          * There's probably more special stuff for Macv0[234] needed here.
 416          */
 417         ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
 418         if(ctlr->macv == Macv02){
 419                 csr8w(ctlr, Ldps, 1);                           /* magic */
 420                 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);      /* magic */
 421         }
 422
 423         if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
 424                 free(ctlr->mii);
 425                 ctlr->mii = nil;
 426                 return -1;
 427         }
 428         print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 429                 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 430
 431         miireset(ctlr->mii);
 432
 433         microdelay(100);
 434
 435         miiane(ctlr->mii, ~0, ~0, ~0);
 436
 437         return 0;
 438 }
 439
 440 static void
 441 rtl8169promiscuous(void* arg, int on)
 442 {
 443         Ether *edev;
 444         Ctlr * ctlr;
 445
 446         edev = arg;
 447         ctlr = edev->ctlr;
 448         ilock(ctlr);
 449         if(on)
 450                 ctlr->rcr |= Aap;
 451         else
 452                 ctlr->rcr &= ~Aap;
 453         csr32w(ctlr, Rcr, ctlr->rcr);
 454         iunlock(ctlr);
 455 }
 456
 457 enum {
 458         /* everyone else uses 0x04c11db7, but they both produce the same crc */
 459         Etherpolybe = 0x04c11db6,
 460         Bytemask = (1<<8) - 1,
 461 };
 462
 463 static ulong
 464 ethercrcbe(uchar *addr, long len)
 465 {
 466         int i, j;
 467         ulong c, crc, carry;
 468
 469         crc = ~0UL;
 470         for (i = 0; i < len; i++) {
 471                 c = addr[i];
 472                 for (j = 0; j < 8; j++) {
 473                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
 474                         crc <<= 1;
 475                         c >>= 1;
 476                         if (carry)
 477                                 crc = (crc ^ Etherpolybe) | carry;
 478                 }
 479         }
 480         return crc;
 481 }
 482
 483 static ulong
 484 swabl(ulong l)
 485 {
 486         return l>>24 | (l>>8) & (Bytemask<<8) |
 487                 (l<<8) & (Bytemask<<16) | l<<24;
 488 }
 489
 490 static void
 491 rtl8169multicast(void* ether, uchar *eaddr, int add)
 492 {
 493         Ether *edev;
 494         Ctlr *ctlr;
 495
 496         if (!add)
 497                 return; /* ok to keep receiving on old mcast addrs */
 498
 499         edev = ether;
 500         ctlr = edev->ctlr;
 501         ilock(ctlr);
 502
 503         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
 504
 505         ctlr->rcr |= Am;
 506         csr32w(ctlr, Rcr, ctlr->rcr);
 507
 508         /* pci-e variants reverse the order of the hash byte registers */
 509         if (ctlr->pcie) {
 510                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
 511                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
 512         } else {
 513                 csr32w(ctlr, Mar0,   ctlr->mchash);
 514                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
 515         }
 516
 517         iunlock(ctlr);
 518 }
 519
 520 static long
 521 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
 522 {
 523         char *p;
 524         Ctlr *ctlr;
 525         Dtcc *dtcc;
 526         int i, l, r, timeo;
 527
 528         p = smalloc(READSTR);
 529
 530         ctlr = edev->ctlr;
 531         qlock(&ctlr->slock);
 532
 533         if(waserror()){
 534                 qunlock(&ctlr->slock);
 535                 free(p);
 536                 nexterror();
 537         }
 538
 539         csr32w(ctlr, Dtccr+4, 0);
 540         csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd);
 541         for(timeo = 0; timeo < 1000; timeo++){
 542                 if(!(csr32r(ctlr, Dtccr) & Cmd))
 543                         break;
 544                 delay(1);
 545         }
 546         if(csr32r(ctlr, Dtccr) & Cmd)
 547                 error(Eio);
 548         dtcc = ctlr->dtcc;
 549
 550         edev->oerrs = dtcc->txer;
 551         edev->crcs = dtcc->rxer;
 552         edev->frames = dtcc->fae;
 553         edev->buffs = dtcc->misspkt;
 554         edev->overflows = ctlr->txdu+ctlr->rdu;
 555
 556         if(n == 0){
 557                 qunlock(&ctlr->slock);
 558                 poperror();
 559                 free(p);
 560                 return 0;
 561         }
 562
 563         l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
 564         l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
 565         l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
 566         l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
 567         l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
 568         l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
 569         l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
 570         l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
 571         l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
 572         l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
 573         l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
 574         l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
 575         l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
 576
 577         l += snprint(p+l, READSTR-l, "serr: %ud\n", ctlr->serr);
 578         l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
 579
 580         l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
 581         l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
 582         l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
 583         l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
 584         l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
 585         l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
 586         l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
 587         l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
 588
 589         l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
 590         l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
 591         l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
 592
 593         if(ctlr->mii != nil && ctlr->mii->curphy != nil){
 594                 l += snprint(p+l, READSTR-l, "phy:   ");
 595                 for(i = 0; i < NMiiPhyr; i++){
 596                         if(i && ((i & 0x07) == 0))
 597                                 l += snprint(p+l, READSTR-l, "\n       ");
 598                         r = miimir(ctlr->mii, i);
 599                         l += snprint(p+l, READSTR-l, " %4.4ux", r);
 600                 }
 601                 snprint(p+l, READSTR-l, "\n");
 602         }
 603
 604         n = readstr(offset, a, n, p);
 605
 606         qunlock(&ctlr->slock);
 607         poperror();
 608         free(p);
 609
 610         return n;
 611 }
 612
 613 static void
 614 rtl8169halt(Ctlr* ctlr)
 615 {
 616         csr8w(ctlr, Cr, 0);
 617         csr16w(ctlr, Imr, 0);
 618         csr16w(ctlr, Isr, ~0);
 619 }
 620
 621 static int
 622 rtl8169reset(Ctlr* ctlr)
 623 {
 624         u32int r;
 625         int timeo;
 626
 627         /*
 628          * Soft reset the controller.
 629          */
 630         csr8w(ctlr, Cr, Rst);
 631         for(r = timeo = 0; timeo < 1000; timeo++){
 632                 r = csr8r(ctlr, Cr);
 633                 if(!(r & Rst))
 634                         break;
 635                 delay(1);
 636         }
 637         rtl8169halt(ctlr);
 638
 639         if(r & Rst)
 640                 return -1;
 641         return 0;
 642 }
 643
 644 static void
 645 rtl8169replenish(Ctlr* ctlr)
 646 {
 647         D *d;
 648         int x;
 649         Block *bp;
 650
 651         x = ctlr->rdt;
 652         while(NEXT(x, ctlr->nrd) != ctlr->rdh){
 653                 bp = iallocb(Mps);
 654                 if(bp == nil){
 655                         iprint("rtl8169: no available buffers\n");
 656                         break;
 657                 }
 658                 ctlr->rb[x] = bp;
 659                 ctlr->nrq++;
 660                 d = &ctlr->rd[x];
 661                 d->addrlo = PCIWADDR(bp->rp);
 662                 d->addrhi = 0;
 663                 coherence();
 664                 d->control = (d->control & Eor) | Own | BALLOC(bp);
 665                 x = NEXT(x, ctlr->nrd);
 666                 ctlr->rdt = x;
 667         }
 668 }
 669
 670 static int
 671 rtl8169init(Ether* edev)
 672 {
 673         int i;
 674         u32int r;
 675         Block *bp;
 676         Ctlr *ctlr;
 677         u16int cplusc;
 678
 679         ctlr = edev->ctlr;
 680         ilock(ctlr);
 681
 682         rtl8169reset(ctlr);
 683
 684         memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
 685         ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
 686         ctlr->td[ctlr->ntd-1].control = Eor;
 687         for(i = 0; i < ctlr->ntd; i++)
 688                 if(bp = ctlr->tb[i]){
 689                         ctlr->tb[i] = nil;
 690                         freeb(bp);
 691                 }
 692
 693         memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
 694         ctlr->rdh = ctlr->rdt = ctlr->nrq = 0;
 695         ctlr->rd[ctlr->nrd-1].control = Eor;
 696         for(i = 0; i < ctlr->nrd; i++)
 697                 if(bp = ctlr->rb[i]){
 698                         ctlr->rb[i] = nil;
 699                         freeb(bp);
 700                 }
 701
 702         rtl8169replenish(ctlr);
 703
 704         cplusc = csr16r(ctlr, Cplusc);
 705         cplusc &= ~(Endian|Rxchksum);
 706         cplusc |= Txenb|Mulrw;
 707         switch(ctlr->macv){
 708         case Macv40:
 709         case Macv44:
 710                 cplusc |= Macstatdis;
 711                 break;
 712         default:
 713                 cplusc |= Rxenb;
 714                 break;
 715         }
 716         csr16w(ctlr, Cplusc, cplusc);
 717
 718         csr32w(ctlr, Tnpds+4, 0);
 719         csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
 720         csr32w(ctlr, Rdsar+4, 0);
 721         csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
 722
 723         csr8w(ctlr, Cr, Te|Re);
 724
 725         csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
 726         ctlr->tcr = csr32r(ctlr, Tcr);
 727         switch(ctlr->macv){
 728         case Macv42:
 729         case Macv45:
 730                 ctlr->rcr = Rxfth256|Mrxdmaunlimited|Ab|Am|Apm;
 731                 break;
 732         default:
 733                 ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
 734                 break;
 735         }
 736         ctlr->mchash = 0;
 737         csr32w(ctlr, Mar0,   0);
 738         csr32w(ctlr, Mar0+4, 0);
 739         csr32w(ctlr, Rcr, ctlr->rcr);
 740
 741         /* maximum packet sizes, unlimited */
 742         csr8w(ctlr, Etx, 0x3f);
 743         csr16w(ctlr, Rms, 0x3fff);
 744
 745         csr16w(ctlr, Coal, 0);
 746
 747         /* no early rx interrupts */
 748         r = csr16r(ctlr, Mulint) & 0xF000;
 749         csr16w(ctlr, Mulint, r);
 750
 751         ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Rer|Rok|Tdu;
 752         csr16w(ctlr, Imr, ctlr->imr);
 753
 754         csr32w(ctlr, Mpc, 0);
 755
 756         iunlock(ctlr);
 757
 758         return 0;
 759 }
 760
 761 static void
 762 rtl8169reseter(void *arg)
 763 {
 764         Ether *edev;
 765         Ctlr *ctlr;
 766
 767         edev = arg;
 768
 769         for(;;){
 770                 rtl8169init(edev);
 771
 772                 ctlr = edev->ctlr;
 773                 qunlock(&ctlr->alock);
 774
 775                 while(waserror())
 776                         ;
 777                 sleep(&ctlr->reset, return0, nil);
 778                 poperror();
 779
 780                 qlock(&ctlr->alock);
 781         }
 782 }
 783
 784 static void
 785 rtl8169attach(Ether* edev)
 786 {
 787         int timeo;
 788         Ctlr *ctlr;
 789
 790         ctlr = edev->ctlr;
 791         qlock(&ctlr->alock);
 792         if(!ctlr->init){
 793                 ctlr->ntd = Ntd;
 794                 ctlr->nrd = Nrd;
 795                 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
 796                 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
 797                 ctlr->td = mallocalign(sizeof(D)*ctlr->ntd, 256, 0, 0);
 798                 ctlr->rd = mallocalign(sizeof(D)*ctlr->nrd, 256, 0, 0);
 799                 ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
 800                 if(ctlr->rb == nil || ctlr->rb == nil ||
 801                    ctlr->rd == nil || ctlr->rd == nil || ctlr->dtcc == nil){
 802                         free(ctlr->tb);
 803                         ctlr->tb = nil;
 804                         free(ctlr->rb);
 805                         ctlr->rb = nil;
 806                         free(ctlr->td);
 807                         ctlr->td = nil;
 808                         free(ctlr->rd);
 809                         ctlr->rd = nil;
 810                         free(ctlr->dtcc);
 811                         ctlr->dtcc = nil;
 812                         qunlock(&ctlr->alock);
 813                         error(Enomem);
 814                 }
 815                 ctlr->init = 1;
 816                 kproc("rtl8169", rtl8169reseter, edev);
 817
 818                 /* rtl8169reseter() does qunlock(&ctlr->alock) when complete */
 819                 qlock(&ctlr->alock);
 820         }
 821         qunlock(&ctlr->alock);
 822
 823         /*
 824          * Wait for link to be ready.
 825          */
 826         for(timeo = 0; timeo < 35; timeo++){
 827                 if(miistatus(ctlr->mii) == 0)
 828                         break;
 829                 delay(100);             /* print fewer miistatus messages */
 830         }
 831 }
 832
 833 static void
 834 rtl8169link(Ether* edev)
 835 {
 836         uint r;
 837         int limit;
 838         Ctlr *ctlr;
 839
 840         ctlr = edev->ctlr;
 841
 842         r = csr8r(ctlr, Phystatus);
 843         /*
 844          * Maybe the link changed - do we care very much?
 845          * Could stall transmits if no link, maybe?
 846          */
 847         edev->link = (r & Linksts) != 0;
 848
 849         limit = 256*1024;
 850         if(r & Speed10){
 851                 edev->mbps = 10;
 852                 limit = 65*1024;
 853         } else if(r & Speed100)
 854                 edev->mbps = 100;
 855         else if(r & Speed1000)
 856                 edev->mbps = 1000;
 857
 858         if(edev->oq != nil)
 859                 qsetlimit(edev->oq, limit);
 860 }
 861
 862 static void
 863 rtl8169transmit(Ether* edev)
 864 {
 865         D *d;
 866         Block *bp;
 867         Ctlr *ctlr;
 868         int x;
 869
 870         ctlr = edev->ctlr;
 871
 872         if(!canlock(ctlr))
 873                 return;
 874         for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
 875                 d = &ctlr->td[x];
 876                 if(d->control & Own)
 877                         break;
 878
 879                 /*
 880                  * Free it up.
 881                  * Need to clean the descriptor here? Not really.
 882                  * Simple freeb for now (no chain and freeblist).
 883                  * Use ntq count for now.
 884                  */
 885                 freeb(ctlr->tb[x]);
 886                 ctlr->tb[x] = nil;
 887                 ctlr->ntq--;
 888         }
 889         ctlr->tdh = x;
 890
 891         x = ctlr->tdt;
 892         while(ctlr->ntq < (ctlr->ntd-1)){
 893                 if((bp = qget(edev->oq)) == nil)
 894                         break;
 895
 896                 d = &ctlr->td[x];
 897                 d->addrlo = PCIWADDR(bp->rp);
 898                 d->addrhi = 0;
 899                 coherence();
 900                 d->control = (d->control & Eor) | Own | Fs | Ls | BLEN(bp);
 901
 902                 ctlr->tb[x] = bp;
 903                 ctlr->ntq++;
 904
 905                 x = NEXT(x, ctlr->ntd);
 906         }
 907         if(x != ctlr->tdt)
 908                 ctlr->tdt = x;
 909         else if(ctlr->ntq >= (ctlr->ntd-1))
 910                 ctlr->txdu++;
 911
 912         if(ctlr->ntq > 0){
 913                 coherence();
 914                 csr8w(ctlr, Tppoll, Npq);
 915         }
 916         unlock(ctlr);
 917 }
 918
 919 static void
 920 rtl8169receive(Ether* edev)
 921 {
 922         D *d;
 923         Block *bp;
 924         Ctlr *ctlr;
 925         u32int control;
 926         int x;
 927
 928         ctlr = edev->ctlr;
 929         if(ctlr->nrq < ctlr->nrd/2)
 930                 rtl8169replenish(ctlr);
 931
 932         for(x = ctlr->rdh; x != ctlr->rdt;){
 933                 d = &ctlr->rd[x];
 934                 if((control = d->control) & Own)
 935                         break;
 936
 937                 bp = ctlr->rb[x];
 938                 ctlr->rb[x] = nil;
 939                 ctlr->nrq--;
 940
 941                 x = NEXT(x, ctlr->nrd);
 942                 ctlr->rdh = x;
 943
 944                 if(ctlr->nrq < ctlr->nrd/2)
 945                         rtl8169replenish(ctlr);
 946
 947                 if((control & (Fs|Ls|Res)) == (Fs|Ls)){
 948                         bp->wp = bp->rp + (control & RxflMASK) - 4;
 949
 950                         if(control & Fovf)
 951                                 ctlr->fovf++;
 952                         if(control & Mar)
 953                                 ctlr->mcast++;
 954
 955                         switch(control & (Pid1|Pid0)){
 956                         default:
 957                                 break;
 958                         case Pid0:
 959                                 if(control & Tcpf){
 960                                         ctlr->tcpf++;
 961                                         break;
 962                                 }
 963                                 bp->flag |= Btcpck;
 964                                 break;
 965                         case Pid1:
 966                                 if(control & Udpf){
 967                                         ctlr->udpf++;
 968                                         break;
 969                                 }
 970                                 bp->flag |= Budpck;
 971                                 break;
 972                         case Pid1|Pid0:
 973                                 if(control & Ipf){
 974                                         ctlr->ipf++;
 975                                         break;
 976                                 }
 977                                 bp->flag |= Bipck;
 978                                 break;
 979                         }
 980                         etheriq(edev, bp);
 981                 }else{
 982                         if(!(control & Res))
 983                                 ctlr->frag++;
 984                         freeb(bp);
 985                 }
 986         }
 987 }
 988
 989 static void
 990 rtl8169restart(Ctlr *ctlr)
 991 {
 992         ctlr->imr = 0;
 993         rtl8169halt(ctlr);
 994         wakeup(&ctlr->reset);
 995 }
 996
 997 static void
 998 rtl8169interrupt(Ureg*, void* arg)
 999 {
1000         Ctlr *ctlr;
1001         Ether *edev;
1002         u32int isr;
1003
1004         edev = arg;
1005         ctlr = edev->ctlr;
1006
1007         while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
1008                 csr16w(ctlr, Isr, isr);
1009                 if((isr & ctlr->imr) == 0)
1010                         break;
1011
1012                 if(isr & Serr)
1013                         ctlr->serr++;
1014                 if(isr & Fovw)
1015                         ctlr->fovw++;
1016                 if(isr & Rer)
1017                         ctlr->rer++;
1018                 if(isr & Rdu)
1019                         ctlr->rdu++;
1020                 if(isr & Punlc)
1021                         ctlr->punlc++;
1022
1023                 if(isr & (Serr|Fovw)){
1024                         rtl8169restart(ctlr);
1025                         break;
1026                 }
1027
1028                 if(isr & (Punlc|Rdu|Rer|Rok))
1029                         rtl8169receive(edev);
1030
1031                 if(isr & (Tdu|Ter|Tok))
1032                         rtl8169transmit(edev);
1033
1034                 if(isr & Punlc)
1035                         rtl8169link(edev);
1036         }
1037 }
1038
1039 int
1040 vetmacv(Ctlr *ctlr, uint *macv)
1041 {
1042         *macv = csr32r(ctlr, Tcr) & HwveridMASK;
1043         switch(*macv){
1044         default:
1045                 return -1;
1046         case Macv01:
1047         case Macv02:
1048         case Macv03:
1049         case Macv04:
1050         case Macv05:
1051         case Macv07:
1052         case Macv07a:
1053         case Macv11:
1054         case Macv12:
1055         case Macv12a:
1056         case Macv13:
1057         case Macv14:
1058         case Macv15:
1059         case Macv25:
1060         case Macv26:
1061         case Macv27:
1062         case Macv28:
1063         case Macv29:
1064         case Macv30:
1065         case Macv39:
1066         case Macv40:
1067         case Macv42:
1068         case Macv44:
1069         case Macv45:
1070                 break;
1071         }
1072         return 0;
1073 }
1074
1075 static void
1076 rtl8169pci(void)
1077 {
1078         Pcidev *p;
1079         Ctlr *ctlr;
1080         int i, port, pcie;
1081         uint macv;
1082
1083         p = nil;
1084         while(p = pcimatch(p, 0, 0)){
1085                 if(p->ccrb != 0x02 || p->ccru != 0)
1086                         continue;
1087
1088                 pcie = 0;
1089                 switch(i = ((p->did<<16)|p->vid)){
1090                 default:
1091                         continue;
1092                 case Rtl8100e:                  /* RTL810[01]E ? */
1093                 case Rtl8168b:                  /* RTL8168B */
1094                         pcie = 1;
1095                         break;
1096                 case Rtl8169c:                  /* RTL8169C */
1097                 case Rtl8169sc:                 /* RTL8169SC */
1098                 case Rtl8169:                   /* RTL8169 */
1099                         break;
1100                 case (0xC107<<16)|0x1259:       /* Corega CG-LAPCIGT */
1101                         i = Rtl8169;
1102                         break;
1103                 }
1104
1105                 port = p->mem[0].bar & ~0x01;
1106                 if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
1107                         print("rtl8169: port %#ux in use\n", port);
1108                         continue;
1109                 }
1110                 ctlr = malloc(sizeof(Ctlr));
1111                 if(ctlr == nil){
1112                         print("rtl8169: can't allocate memory\n");
1113                         iofree(port);
1114                         continue;
1115                 }
1116                 ctlr->port = port;
1117                 ctlr->pcidev = p;
1118                 ctlr->pciv = i;
1119                 ctlr->pcie = pcie;
1120
1121                 pcienable(p);
1122                 if(vetmacv(ctlr, &macv) == -1){
1123                         pcidisable(p);
1124                         iofree(port);
1125                         free(ctlr);
1126                         print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1127                         continue;
1128                 }
1129
1130                 if(rtl8169reset(ctlr)){
1131                         pcidisable(p);
1132                         iofree(port);
1133                         free(ctlr);
1134                         print("rtl8169: reset failed\n");
1135                         continue;
1136                 }
1137
1138                 /*
1139                  * Extract the chip hardware version,
1140                  * needed to configure each properly.
1141                  */
1142                 ctlr->macv = macv;
1143
1144                 rtl8169mii(ctlr);
1145
1146                 pcisetbme(p);
1147
1148                 if(rtl8169ctlrhead != nil)
1149                         rtl8169ctlrtail->next = ctlr;
1150                 else
1151                         rtl8169ctlrhead = ctlr;
1152                 rtl8169ctlrtail = ctlr;
1153         }
1154 }
1155
1156 static int
1157 rtl8169pnp(Ether* edev)
1158 {
1159         u32int r;
1160         Ctlr *ctlr;
1161         uchar ea[Eaddrlen];
1162         static int once;
1163
1164         if(once == 0){
1165                 once = 1;
1166                 rtl8169pci();
1167         }
1168
1169         /*
1170          * Any adapter matches if no edev->port is supplied,
1171          * otherwise the ports must match.
1172          */
1173         for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1174                 if(ctlr->active)
1175                         continue;
1176                 if(edev->port == 0 || edev->port == ctlr->port){
1177                         ctlr->active = 1;
1178                         break;
1179                 }
1180         }
1181         if(ctlr == nil)
1182                 return -1;
1183
1184         edev->ctlr = ctlr;
1185         edev->port = ctlr->port;
1186         edev->irq = ctlr->pcidev->intl;
1187         edev->tbdf = ctlr->pcidev->tbdf;
1188         edev->mbps = 100;
1189         edev->maxmtu = Mtu;
1190
1191         /*
1192          * Check if the adapter's station address is to be overridden.
1193          * If not, read it from the device and set in edev->ea.
1194          */
1195         memset(ea, 0, Eaddrlen);
1196         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1197                 r = csr32r(ctlr, Idr0);
1198                 edev->ea[0] = r;
1199                 edev->ea[1] = r>>8;
1200                 edev->ea[2] = r>>16;
1201                 edev->ea[3] = r>>24;
1202                 r = csr32r(ctlr, Idr0+4);
1203                 edev->ea[4] = r;
1204                 edev->ea[5] = r>>8;
1205         }
1206
1207         edev->attach = rtl8169attach;
1208         edev->transmit = rtl8169transmit;
1209         edev->ifstat = rtl8169ifstat;
1210
1211         edev->arg = edev;
1212         edev->promiscuous = rtl8169promiscuous;
1213         edev->multicast = rtl8169multicast;
1214
1215         rtl8169link(edev);
1216
1217         intrenable(edev->irq, rtl8169interrupt, edev, edev->tbdf, edev->name);
1218
1219         return 0;
1220 }
1221
1222 void
1223 ether8169link(void)
1224 {
1225         addethercard("rtl8169", rtl8169pnp);
1226 }