sys/src/9/pc/ether8169.c

   1 /*
   2  * Realtek RTL8110S/8169S Gigabit Ethernet Controllers.
   3  * Mostly there. There are some magic register values used
   4  * which are not described in any datasheet or driver but seem
   5  * to be necessary.
   6  * No tuning has been done. Only tested on an RTL8110S, there
   7  * are slight differences between the chips in the series so some
   8  * tweaks may be needed.
   9  */
  10 #include "u.h"
  11 #include "../port/lib.h"
  12 #include "mem.h"
  13 #include "dat.h"
  14 #include "fns.h"
  15 #include "io.h"
  16 #include "../port/error.h"
  17 #include "../port/netif.h"
  18
  19 #include "etherif.h"
  20 #include "ethermii.h"
  21
  22 enum {                                  /* registers */
  23         Idr0            = 0x00,         /* MAC address */
  24         Mar0            = 0x08,         /* Multicast address */
  25         Dtccr           = 0x10,         /* Dump Tally Counter Command */
  26         Tnpds           = 0x20,         /* Transmit Normal Priority Descriptors */
  27         Thpds           = 0x28,         /* Transmit High Priority Descriptors */
  28         Flash           = 0x30,         /* Flash Memory Read/Write */
  29         Erbcr           = 0x34,         /* Early Receive Byte Count */
  30         Ersr            = 0x36,         /* Early Receive Status */
  31         Cr              = 0x37,         /* Command Register */
  32         Tppoll          = 0x38,         /* Transmit Priority Polling */
  33         Imr             = 0x3C,         /* Interrupt Mask */
  34         Isr             = 0x3E,         /* Interrupt Status */
  35         Tcr             = 0x40,         /* Transmit Configuration */
  36         Rcr             = 0x44,         /* Receive Configuration */
  37         Tctr            = 0x48,         /* Timer Count */
  38         Mpc             = 0x4C,         /* Missed Packet Counter */
  39         Cr9346          = 0x50,         /* 9346 Command Register */
  40         Config0         = 0x51,         /* Configuration Register 0 */
  41         Config1         = 0x52,         /* Configuration Register 1 */
  42         Config2         = 0x53,         /* Configuration Register 2 */
  43         Config3         = 0x54,         /* Configuration Register 3 */
  44         Config4         = 0x55,         /* Configuration Register 4 */
  45         Config5         = 0x56,         /* Configuration Register 5 */
  46         Timerint        = 0x58,         /* Timer Interrupt */
  47         Mulint          = 0x5C,         /* Multiple Interrupt Select */
  48         Phyar           = 0x60,         /* PHY Access */
  49         Tbicsr0         = 0x64,         /* TBI Control and Status */
  50         Tbianar         = 0x68,         /* TBI Auto-Negotiation Advertisment */
  51         Tbilpar         = 0x6A,         /* TBI Auto-Negotiation Link Partner */
  52         Phystatus       = 0x6C,         /* PHY Status */
  53         Pmch            = 0x6F,         /* power management */
  54         Ldps            = 0x82,         /* link down power saving */
  55
  56         Rms             = 0xDA,         /* Receive Packet Maximum Size */
  57         Cplusc          = 0xE0,         /* C+ Command */
  58         Coal            = 0xE2,         /* Interrupt Mitigation (Coalesce) */
  59         Rdsar           = 0xE4,         /* Receive Descriptor Start Address */
  60         Etx             = 0xEC,         /* Early Transmit Threshold */
  61 };
  62
  63 enum {                                  /* Dtccr */
  64         Cmd             = 0x00000008,   /* Command */
  65 };
  66
  67 enum {                                  /* Cr */
  68         Te              = 0x04,         /* Transmitter Enable */
  69         Re              = 0x08,         /* Receiver Enable */
  70         Rst             = 0x10,         /* Software Reset */
  71 };
  72
  73 enum {                                  /* Tppoll */
  74         Fswint          = 0x01,         /* Forced Software Interrupt */
  75         Npq             = 0x40,         /* Normal Priority Queue polling */
  76         Hpq             = 0x80,         /* High Priority Queue polling */
  77 };
  78
  79 enum {                                  /* Imr/Isr */
  80         Rok             = 0x0001,       /* Receive OK */
  81         Rer             = 0x0002,       /* Receive Error */
  82         Tok             = 0x0004,       /* Transmit OK */
  83         Ter             = 0x0008,       /* Transmit Error */
  84         Rdu             = 0x0010,       /* Receive Descriptor Unavailable */
  85         Punlc           = 0x0020,       /* Packet Underrun or Link Change */
  86         Fovw            = 0x0040,       /* Receive FIFO Overflow */
  87         Tdu             = 0x0080,       /* Transmit Descriptor Unavailable */
  88         Swint           = 0x0100,       /* Software Interrupt */
  89         Timeout         = 0x4000,       /* Timer */
  90         Serr            = 0x8000,       /* System Error */
  91 };
  92
  93 enum {                                  /* Tcr */
  94         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
  95         MtxdmaMASK      = 0x00000700,
  96         Mtxdmaunlimited = 0x00000700,
  97         Acrc            = 0x00010000,   /* Append CRC (not) */
  98         Lbk0            = 0x00020000,   /* Loopback Test 0 */
  99         Lbk1            = 0x00040000,   /* Loopback Test 1 */
 100         Ifg2            = 0x00080000,   /* Interframe Gap 2 */
 101         HwveridSHIFT    = 23,           /* Hardware Version ID */
 102         HwveridMASK     = 0x7C800000,
 103         Macv01          = 0x00000000,   /* RTL8169 */
 104         Macv02          = 0x00800000,   /* RTL8169S/8110S */
 105         Macv03          = 0x04000000,   /* RTL8169S/8110S */
 106         Macv04          = 0x10000000,   /* RTL8169SB/8110SB */
 107         Macv05          = 0x18000000,   /* RTL8169SC/8110SC */
 108         Macv07          = 0x24800000,   /* RTL8102e */
 109         Macv07a         = 0x34800000,   /* RTL8102e */
 110         Macv11          = 0x30000000,   /* RTL8168B/8111B */
 111         Macv12          = 0x38000000,   /* RTL8169B/8111B */
 112         Macv12a         = 0x3c000000,   /* RTL8169C/8111C */
 113         Macv13          = 0x34000000,   /* RTL8101E */
 114         Macv14          = 0x30800000,   /* RTL8100E */
 115         Macv15          = 0x38800000,   /* RTL8100E */
 116 //      Macv19          = 0x3c000000,   /* dup Macv12a: RTL8111c-gr */
 117         Macv25          = 0x28000000,   /* RTL8168D */
 118         Macv26          = 0x48000000,   /* RTL8111/8168B */
 119         Macv27          = 0x2c800000,   /* RTL8111e */
 120         Macv28          = 0x2c000000,   /* RTL8111/8168B */
 121         Macv29          = 0x40800000,   /* RTL8101/8102E */
 122         Macv30          = 0x24000000,   /* RTL8101E? (untested) */
 123         Macv40          = 0x4c000000,   /* RTL8168G */
 124         Macv44          = 0x5c800000,   /* RTL8411B */
 125         Ifg0            = 0x01000000,   /* Interframe Gap 0 */
 126         Ifg1            = 0x02000000,   /* Interframe Gap 1 */
 127 };
 128
 129 enum {                                  /* Rcr */
 130         Aap             = 0x00000001,   /* Accept All Packets */
 131         Apm             = 0x00000002,   /* Accept Physical Match */
 132         Am              = 0x00000004,   /* Accept Multicast */
 133         Ab              = 0x00000008,   /* Accept Broadcast */
 134         Ar              = 0x00000010,   /* Accept Runt */
 135         Aer             = 0x00000020,   /* Accept Error */
 136         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
 137         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 138         MrxdmaMASK      = 0x00000700,
 139         Mrxdmaunlimited = 0x00000700,
 140         RxfthSHIFT      = 13,           /* Receive Buffer Length */
 141         RxfthMASK       = 0x0000E000,
 142         Rxfth256        = 0x00008000,
 143         Rxfthnone       = 0x0000E000,
 144         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
 145         MulERINT        = 0x01000000,   /* Multiple Early Interrupt Select */
 146 };
 147
 148 enum {                                  /* Cr9346 */
 149         Eedo            = 0x01,         /* */
 150         Eedi            = 0x02,         /* */
 151         Eesk            = 0x04,         /* */
 152         Eecs            = 0x08,         /* */
 153         Eem0            = 0x40,         /* Operating Mode */
 154         Eem1            = 0x80,
 155 };
 156
 157 enum {                                  /* Phyar */
 158         DataMASK        = 0x0000FFFF,   /* 16-bit GMII/MII Register Data */
 159         DataSHIFT       = 0,
 160         RegaddrMASK     = 0x001F0000,   /* 5-bit GMII/MII Register Address */
 161         RegaddrSHIFT    = 16,
 162         Flag            = 0x80000000,   /* */
 163 };
 164
 165 enum {                                  /* Phystatus */
 166         Fd              = 0x01,         /* Full Duplex */
 167         Linksts         = 0x02,         /* Link Status */
 168         Speed10         = 0x04,         /* */
 169         Speed100        = 0x08,         /* */
 170         Speed1000       = 0x10,         /* */
 171         Rxflow          = 0x20,         /* */
 172         Txflow          = 0x40,         /* */
 173         Entbi           = 0x80,         /* */
 174 };
 175
 176 enum {                                  /* Cplusc */
 177         Txenb           = 0x0001,       /* enable C+ transmit mode */
 178         Rxenb           = 0x0002,       /* enable C+ receive mode */
 179         Mulrw           = 0x0008,       /* PCI Multiple R/W Enable */
 180         Dac             = 0x0010,       /* PCI Dual Address Cycle Enable */
 181         Rxchksum        = 0x0020,       /* Receive Checksum Offload Enable */
 182         Rxvlan          = 0x0040,       /* Receive VLAN De-tagging Enable */
 183         Macstatdis      = 0x0080,       /* Disable Mac Statistics */
 184         Endian          = 0x0200,       /* Endian Mode */
 185 };
 186
 187 typedef struct D D;                     /* Transmit/Receive Descriptor */
 188 struct D {
 189         u32int  control;
 190         u32int  vlan;
 191         u32int  addrlo;
 192         u32int  addrhi;
 193 };
 194
 195 enum {                                  /* Transmit Descriptor control */
 196         TxflMASK        = 0x0000FFFF,   /* Transmit Frame Length */
 197         TxflSHIFT       = 0,
 198         Tcps            = 0x00010000,   /* TCP Checksum Offload */
 199         Udpcs           = 0x00020000,   /* UDP Checksum Offload */
 200         Ipcs            = 0x00040000,   /* IP Checksum Offload */
 201         Lgsen           = 0x08000000,   /* TSO; WARNING: contains lark's vomit */
 202 };
 203
 204 enum {                                  /* Receive Descriptor control */
 205         RxflMASK        = 0x00001FFF,   /* Receive Frame Length */
 206         Tcpf            = 0x00004000,   /* TCP Checksum Failure */
 207         Udpf            = 0x00008000,   /* UDP Checksum Failure */
 208         Ipf             = 0x00010000,   /* IP Checksum Failure */
 209         Pid0            = 0x00020000,   /* Protocol ID0 */
 210         Pid1            = 0x00040000,   /* Protocol ID1 */
 211         Crce            = 0x00080000,   /* CRC Error */
 212         Runt            = 0x00100000,   /* Runt Packet */
 213         Res             = 0x00200000,   /* Receive Error Summary */
 214         Rwt             = 0x00400000,   /* Receive Watchdog Timer Expired */
 215         Fovf            = 0x00800000,   /* FIFO Overflow */
 216         Bovf            = 0x01000000,   /* Buffer Overflow */
 217         Bar             = 0x02000000,   /* Broadcast Address Received */
 218         Pam             = 0x04000000,   /* Physical Address Matched */
 219         Mar             = 0x08000000,   /* Multicast Address Received */
 220 };
 221
 222 enum {                                  /* General Descriptor control */
 223         Ls              = 0x10000000,   /* Last Segment Descriptor */
 224         Fs              = 0x20000000,   /* First Segment Descriptor */
 225         Eor             = 0x40000000,   /* End of Descriptor Ring */
 226         Own             = 0x80000000,   /* Ownership */
 227 };
 228
 229 /*
 230  */
 231 enum {                                  /* Ring sizes  (<= 1024) */
 232         Ntd             = 64,           /* Transmit Ring */
 233         Nrd             = 256,          /* Receive Ring */
 234
 235         Mtu             = ETHERMAXTU,
 236         Mps             = ROUNDUP(ETHERMAXTU+4, 128),
 237 };
 238
 239 typedef struct Dtcc Dtcc;
 240 struct Dtcc {
 241         u64int  txok;
 242         u64int  rxok;
 243         u64int  txer;
 244         u32int  rxer;
 245         u16int  misspkt;
 246         u16int  fae;
 247         u32int  tx1col;
 248         u32int  txmcol;
 249         u64int  rxokph;
 250         u64int  rxokbrd;
 251         u32int  rxokmu;
 252         u16int  txabt;
 253         u16int  txundrn;
 254 };
 255
 256 enum {                                          /* Variants */
 257         Rtl8100e        = (0x8136<<16)|0x10EC,  /* RTL810[01]E: pci -e */
 258         Rtl8169c        = (0x0116<<16)|0x16EC,  /* RTL8169C+ (USR997902) */
 259         Rtl8169sc       = (0x8167<<16)|0x10EC,  /* RTL8169SC */
 260         Rtl8168b        = (0x8168<<16)|0x10EC,  /* RTL8168B: pci-e */
 261         Rtl8169         = (0x8169<<16)|0x10EC,  /* RTL8169 */
 262 };
 263
 264 typedef struct Ctlr Ctlr;
 265 typedef struct Ctlr {
 266         Lock;
 267
 268         int     port;
 269         Pcidev* pcidev;
 270         Ctlr*   next;
 271         int     active;
 272
 273         QLock   alock;                  /* attach */
 274         int     init;                   /*  */
 275         Rendez  reset;
 276
 277         int     pciv;                   /*  */
 278         int     macv;                   /* MAC version */
 279         int     phyv;                   /* PHY version */
 280         int     pcie;                   /* flag: pci-express device? */
 281
 282         uvlong  mchash;                 /* multicast hash */
 283
 284         Mii*    mii;
 285
 286         D*      td;                     /* descriptor ring */
 287         Block** tb;                     /* transmit buffers */
 288         int     ntd;
 289
 290         int     tdh;                    /* head - producer index (host) */
 291         int     tdt;                    /* tail - consumer index (NIC) */
 292         int     ntq;
 293
 294         D*      rd;                     /* descriptor ring */
 295         Block** rb;                     /* receive buffers */
 296         int     nrd;
 297
 298         int     rdh;                    /* head - producer index (NIC) */
 299         int     rdt;                    /* tail - consumer index (host) */
 300         int     nrq;
 301
 302         int     tcr;                    /* transmit configuration register */
 303         int     rcr;                    /* receive configuration register */
 304         int     imr;
 305
 306         QLock   slock;                  /* statistics */
 307         Dtcc*   dtcc;
 308         uint    txdu;
 309         uint    tcpf;
 310         uint    udpf;
 311         uint    ipf;
 312         uint    fovf;
 313         uint    rer;
 314         uint    rdu;
 315         uint    punlc;
 316         uint    serr;
 317         uint    fovw;
 318         uint    mcast;
 319         uint    frag;                   /* partial packets; rb was too small */
 320 } Ctlr;
 321
 322 static Ctlr* rtl8169ctlrhead;
 323 static Ctlr* rtl8169ctlrtail;
 324
 325 #define csr8r(c, r)     (inb((c)->port+(r)))
 326 #define csr16r(c, r)    (ins((c)->port+(r)))
 327 #define csr32r(c, r)    (inl((c)->port+(r)))
 328 #define csr8w(c, r, b)  (outb((c)->port+(r), (u8int)(b)))
 329 #define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w)))
 330 #define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l)))
 331
 332 static int
 333 rtl8169miimir(Mii* mii, int pa, int ra)
 334 {
 335         uint r;
 336         int timeo;
 337         Ctlr *ctlr;
 338
 339         if(pa != 1)
 340                 return -1;
 341         ctlr = mii->ctlr;
 342
 343         r = (ra<<16) & RegaddrMASK;
 344         csr32w(ctlr, Phyar, r);
 345         delay(1);
 346         for(timeo = 0; timeo < 2000; timeo++){
 347                 if((r = csr32r(ctlr, Phyar)) & Flag)
 348                         break;
 349                 microdelay(100);
 350         }
 351         if(!(r & Flag))
 352                 return -1;
 353
 354         return (r & DataMASK)>>DataSHIFT;
 355 }
 356
 357 static int
 358 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
 359 {
 360         uint r;
 361         int timeo;
 362         Ctlr *ctlr;
 363
 364         if(pa != 1)
 365                 return -1;
 366         ctlr = mii->ctlr;
 367
 368         r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
 369         csr32w(ctlr, Phyar, r);
 370         delay(1);
 371         for(timeo = 0; timeo < 2000; timeo++){
 372                 if(!((r = csr32r(ctlr, Phyar)) & Flag))
 373                         break;
 374                 microdelay(100);
 375         }
 376         if(r & Flag)
 377                 return -1;
 378
 379         return 0;
 380 }
 381
 382 static int
 383 rtl8169mii(Ctlr* ctlr)
 384 {
 385         MiiPhy *phy;
 386
 387         /*
 388          * Link management.
 389          */
 390         if((ctlr->mii = malloc(sizeof(Mii))) == nil)
 391                 return -1;
 392         ctlr->mii->mir = rtl8169miimir;
 393         ctlr->mii->miw = rtl8169miimiw;
 394         ctlr->mii->ctlr = ctlr;
 395
 396         /*
 397          * PHY wakeup
 398          */
 399         switch(ctlr->macv){
 400         case Macv25:
 401         case Macv28:
 402         case Macv29:
 403         case Macv30:
 404                 csr8w(ctlr, Pmch, csr8r(ctlr, Pmch) | 0x80);
 405                 break;
 406         }
 407         rtl8169miimiw(ctlr->mii, 1, 0x1f, 0);
 408         rtl8169miimiw(ctlr->mii, 1, 0x0e, 0);
 409
 410         /*
 411          * Get rev number out of Phyidr2 so can config properly.
 412          * There's probably more special stuff for Macv0[234] needed here.
 413          */
 414         ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
 415         if(ctlr->macv == Macv02){
 416                 csr8w(ctlr, Ldps, 1);                           /* magic */
 417                 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);      /* magic */
 418         }
 419
 420         if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
 421                 free(ctlr->mii);
 422                 ctlr->mii = nil;
 423                 return -1;
 424         }
 425         print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 426                 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 427
 428         miireset(ctlr->mii);
 429
 430         microdelay(100);
 431
 432         miiane(ctlr->mii, ~0, ~0, ~0);
 433
 434         return 0;
 435 }
 436
 437 static void
 438 rtl8169promiscuous(void* arg, int on)
 439 {
 440         Ether *edev;
 441         Ctlr * ctlr;
 442
 443         edev = arg;
 444         ctlr = edev->ctlr;
 445         ilock(ctlr);
 446         if(on)
 447                 ctlr->rcr |= Aap;
 448         else
 449                 ctlr->rcr &= ~Aap;
 450         csr32w(ctlr, Rcr, ctlr->rcr);
 451         iunlock(ctlr);
 452 }
 453
 454 enum {
 455         /* everyone else uses 0x04c11db7, but they both produce the same crc */
 456         Etherpolybe = 0x04c11db6,
 457         Bytemask = (1<<8) - 1,
 458 };
 459
 460 static ulong
 461 ethercrcbe(uchar *addr, long len)
 462 {
 463         int i, j;
 464         ulong c, crc, carry;
 465
 466         crc = ~0UL;
 467         for (i = 0; i < len; i++) {
 468                 c = addr[i];
 469                 for (j = 0; j < 8; j++) {
 470                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
 471                         crc <<= 1;
 472                         c >>= 1;
 473                         if (carry)
 474                                 crc = (crc ^ Etherpolybe) | carry;
 475                 }
 476         }
 477         return crc;
 478 }
 479
 480 static ulong
 481 swabl(ulong l)
 482 {
 483         return l>>24 | (l>>8) & (Bytemask<<8) |
 484                 (l<<8) & (Bytemask<<16) | l<<24;
 485 }
 486
 487 static void
 488 rtl8169multicast(void* ether, uchar *eaddr, int add)
 489 {
 490         Ether *edev;
 491         Ctlr *ctlr;
 492
 493         if (!add)
 494                 return; /* ok to keep receiving on old mcast addrs */
 495
 496         edev = ether;
 497         ctlr = edev->ctlr;
 498         ilock(ctlr);
 499
 500         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
 501
 502         ctlr->rcr |= Am;
 503         csr32w(ctlr, Rcr, ctlr->rcr);
 504
 505         /* pci-e variants reverse the order of the hash byte registers */
 506         if (ctlr->pcie) {
 507                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
 508                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
 509         } else {
 510                 csr32w(ctlr, Mar0,   ctlr->mchash);
 511                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
 512         }
 513
 514         iunlock(ctlr);
 515 }
 516
 517 static long
 518 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
 519 {
 520         char *p;
 521         Ctlr *ctlr;
 522         Dtcc *dtcc;
 523         int i, l, r, timeo;
 524
 525         p = smalloc(READSTR);
 526
 527         ctlr = edev->ctlr;
 528         qlock(&ctlr->slock);
 529
 530         if(waserror()){
 531                 qunlock(&ctlr->slock);
 532                 free(p);
 533                 nexterror();
 534         }
 535
 536         csr32w(ctlr, Dtccr+4, 0);
 537         csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd);
 538         for(timeo = 0; timeo < 1000; timeo++){
 539                 if(!(csr32r(ctlr, Dtccr) & Cmd))
 540                         break;
 541                 delay(1);
 542         }
 543         if(csr32r(ctlr, Dtccr) & Cmd)
 544                 error(Eio);
 545         dtcc = ctlr->dtcc;
 546
 547         edev->oerrs = dtcc->txer;
 548         edev->crcs = dtcc->rxer;
 549         edev->frames = dtcc->fae;
 550         edev->buffs = dtcc->misspkt;
 551         edev->overflows = ctlr->txdu+ctlr->rdu;
 552
 553         if(n == 0){
 554                 qunlock(&ctlr->slock);
 555                 poperror();
 556                 free(p);
 557                 return 0;
 558         }
 559
 560         l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
 561         l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
 562         l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
 563         l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
 564         l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
 565         l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
 566         l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
 567         l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
 568         l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
 569         l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
 570         l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
 571         l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
 572         l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
 573
 574         l += snprint(p+l, READSTR-l, "serr: %ud\n", ctlr->serr);
 575         l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
 576
 577         l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
 578         l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
 579         l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
 580         l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
 581         l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
 582         l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
 583         l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
 584         l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
 585
 586         l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
 587         l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
 588         l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
 589
 590         if(ctlr->mii != nil && ctlr->mii->curphy != nil){
 591                 l += snprint(p+l, READSTR-l, "phy:   ");
 592                 for(i = 0; i < NMiiPhyr; i++){
 593                         if(i && ((i & 0x07) == 0))
 594                                 l += snprint(p+l, READSTR-l, "\n       ");
 595                         r = miimir(ctlr->mii, i);
 596                         l += snprint(p+l, READSTR-l, " %4.4ux", r);
 597                 }
 598                 snprint(p+l, READSTR-l, "\n");
 599         }
 600
 601         n = readstr(offset, a, n, p);
 602
 603         qunlock(&ctlr->slock);
 604         poperror();
 605         free(p);
 606
 607         return n;
 608 }
 609
 610 static void
 611 rtl8169halt(Ctlr* ctlr)
 612 {
 613         csr8w(ctlr, Cr, 0);
 614         csr16w(ctlr, Imr, 0);
 615         csr16w(ctlr, Isr, ~0);
 616 }
 617
 618 static int
 619 rtl8169reset(Ctlr* ctlr)
 620 {
 621         u32int r;
 622         int timeo;
 623
 624         /*
 625          * Soft reset the controller.
 626          */
 627         csr8w(ctlr, Cr, Rst);
 628         for(r = timeo = 0; timeo < 1000; timeo++){
 629                 r = csr8r(ctlr, Cr);
 630                 if(!(r & Rst))
 631                         break;
 632                 delay(1);
 633         }
 634         rtl8169halt(ctlr);
 635
 636         if(r & Rst)
 637                 return -1;
 638         return 0;
 639 }
 640
 641 static void
 642 rtl8169replenish(Ctlr* ctlr)
 643 {
 644         D *d;
 645         int x;
 646         Block *bp;
 647
 648         x = ctlr->rdt;
 649         while(NEXT(x, ctlr->nrd) != ctlr->rdh){
 650                 bp = iallocb(Mps);
 651                 if(bp == nil){
 652                         iprint("rtl8169: no available buffers\n");
 653                         break;
 654                 }
 655                 ctlr->rb[x] = bp;
 656                 ctlr->nrq++;
 657                 d = &ctlr->rd[x];
 658                 d->addrlo = PCIWADDR(bp->rp);
 659                 d->addrhi = 0;
 660                 coherence();
 661                 d->control = (d->control & Eor) | Own | BALLOC(bp);
 662                 x = NEXT(x, ctlr->nrd);
 663                 ctlr->rdt = x;
 664         }
 665 }
 666
 667 static int
 668 rtl8169init(Ether* edev)
 669 {
 670         int i;
 671         u32int r;
 672         Block *bp;
 673         Ctlr *ctlr;
 674         u16int cplusc;
 675
 676         ctlr = edev->ctlr;
 677         ilock(ctlr);
 678
 679         rtl8169reset(ctlr);
 680
 681         memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
 682         ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
 683         ctlr->td[ctlr->ntd-1].control = Eor;
 684         for(i = 0; i < ctlr->ntd; i++)
 685                 if(bp = ctlr->tb[i]){
 686                         ctlr->tb[i] = nil;
 687                         freeb(bp);
 688                 }
 689
 690         memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
 691         ctlr->rdh = ctlr->rdt = ctlr->nrq = 0;
 692         ctlr->rd[ctlr->nrd-1].control = Eor;
 693         for(i = 0; i < ctlr->nrd; i++)
 694                 if(bp = ctlr->rb[i]){
 695                         ctlr->rb[i] = nil;
 696                         freeb(bp);
 697                 }
 698
 699         rtl8169replenish(ctlr);
 700
 701         cplusc = csr16r(ctlr, Cplusc);
 702         cplusc &= ~(Endian|Rxchksum);
 703         cplusc |= Txenb|Mulrw;
 704         switch(ctlr->macv){
 705         case Macv40:
 706         case Macv44:
 707                 cplusc |= Macstatdis;
 708                 break;
 709         default:
 710                 cplusc |= Rxenb;
 711                 break;
 712         }
 713         csr16w(ctlr, Cplusc, cplusc);
 714
 715         csr32w(ctlr, Tnpds+4, 0);
 716         csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
 717         csr32w(ctlr, Rdsar+4, 0);
 718         csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
 719
 720         csr8w(ctlr, Cr, Te|Re);
 721
 722         csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
 723         ctlr->tcr = csr32r(ctlr, Tcr);
 724         ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
 725         ctlr->mchash = 0;
 726         csr32w(ctlr, Mar0,   0);
 727         csr32w(ctlr, Mar0+4, 0);
 728         csr32w(ctlr, Rcr, ctlr->rcr);
 729
 730         /* maximum packet sizes, unlimited */
 731         csr8w(ctlr, Etx, 0x3f);
 732         csr16w(ctlr, Rms, 0x3fff);
 733
 734         csr16w(ctlr, Coal, 0);
 735
 736         /* no early rx interrupts */
 737         r = csr16r(ctlr, Mulint) & 0xF000;
 738         csr16w(ctlr, Mulint, r);
 739
 740         ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Rer|Rok|Tdu;
 741         csr16w(ctlr, Imr, ctlr->imr);
 742
 743         csr32w(ctlr, Mpc, 0);
 744
 745         iunlock(ctlr);
 746
 747         return 0;
 748 }
 749
 750 static void
 751 rtl8169reseter(void *arg)
 752 {
 753         Ether *edev;
 754         Ctlr *ctlr;
 755
 756         edev = arg;
 757
 758         for(;;){
 759                 rtl8169init(edev);
 760
 761                 ctlr = edev->ctlr;
 762                 qunlock(&ctlr->alock);
 763
 764                 while(waserror())
 765                         ;
 766                 sleep(&ctlr->reset, return0, nil);
 767                 poperror();
 768
 769                 qlock(&ctlr->alock);
 770         }
 771 }
 772
 773 static void
 774 rtl8169attach(Ether* edev)
 775 {
 776         int timeo;
 777         Ctlr *ctlr;
 778
 779         ctlr = edev->ctlr;
 780         qlock(&ctlr->alock);
 781         if(!ctlr->init){
 782                 ctlr->ntd = Ntd;
 783                 ctlr->nrd = Nrd;
 784                 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
 785                 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
 786                 ctlr->td = mallocalign(sizeof(D)*ctlr->ntd, 256, 0, 0);
 787                 ctlr->rd = mallocalign(sizeof(D)*ctlr->nrd, 256, 0, 0);
 788                 ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
 789                 if(ctlr->rb == nil || ctlr->rb == nil ||
 790                    ctlr->rd == nil || ctlr->rd == nil || ctlr->dtcc == nil){
 791                         free(ctlr->tb);
 792                         ctlr->tb = nil;
 793                         free(ctlr->rb);
 794                         ctlr->rb = nil;
 795                         free(ctlr->td);
 796                         ctlr->td = nil;
 797                         free(ctlr->rd);
 798                         ctlr->rd = nil;
 799                         free(ctlr->dtcc);
 800                         ctlr->dtcc = nil;
 801                         qunlock(&ctlr->alock);
 802                         error(Enomem);
 803                 }
 804                 ctlr->init = 1;
 805                 kproc("rtl8169", rtl8169reseter, edev);
 806
 807                 /* rtl8169reseter() does qunlock(&ctlr->alock) when complete */
 808                 qlock(&ctlr->alock);
 809         }
 810         qunlock(&ctlr->alock);
 811
 812         /*
 813          * Wait for link to be ready.
 814          */
 815         for(timeo = 0; timeo < 35; timeo++){
 816                 if(miistatus(ctlr->mii) == 0)
 817                         break;
 818                 delay(100);             /* print fewer miistatus messages */
 819         }
 820 }
 821
 822 static void
 823 rtl8169link(Ether* edev)
 824 {
 825         uint r;
 826         int limit;
 827         Ctlr *ctlr;
 828
 829         ctlr = edev->ctlr;
 830
 831         /*
 832          * Maybe the link changed - do we care very much?
 833          * Could stall transmits if no link, maybe?
 834          */
 835         if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
 836                 edev->link = 0;
 837                 return;
 838         }
 839         edev->link = 1;
 840
 841         limit = 256*1024;
 842         if(r & Speed10){
 843                 edev->mbps = 10;
 844                 limit = 65*1024;
 845         } else if(r & Speed100)
 846                 edev->mbps = 100;
 847         else if(r & Speed1000)
 848                 edev->mbps = 1000;
 849
 850         if(edev->oq != nil)
 851                 qsetlimit(edev->oq, limit);
 852 }
 853
 854 static void
 855 rtl8169transmit(Ether* edev)
 856 {
 857         D *d;
 858         Block *bp;
 859         Ctlr *ctlr;
 860         int x;
 861
 862         ctlr = edev->ctlr;
 863
 864         if(!canlock(ctlr))
 865                 return;
 866         for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
 867                 d = &ctlr->td[x];
 868                 if(d->control & Own)
 869                         break;
 870
 871                 /*
 872                  * Free it up.
 873                  * Need to clean the descriptor here? Not really.
 874                  * Simple freeb for now (no chain and freeblist).
 875                  * Use ntq count for now.
 876                  */
 877                 freeb(ctlr->tb[x]);
 878                 ctlr->tb[x] = nil;
 879                 ctlr->ntq--;
 880         }
 881         ctlr->tdh = x;
 882
 883         x = ctlr->tdt;
 884         while(ctlr->ntq < (ctlr->ntd-1)){
 885                 if((bp = qget(edev->oq)) == nil)
 886                         break;
 887
 888                 d = &ctlr->td[x];
 889                 d->addrlo = PCIWADDR(bp->rp);
 890                 d->addrhi = 0;
 891                 coherence();
 892                 d->control = (d->control & Eor) | Own | Fs | Ls | BLEN(bp);
 893
 894                 ctlr->tb[x] = bp;
 895                 ctlr->ntq++;
 896
 897                 x = NEXT(x, ctlr->ntd);
 898         }
 899         if(x != ctlr->tdt)
 900                 ctlr->tdt = x;
 901         else if(ctlr->ntq >= (ctlr->ntd-1))
 902                 ctlr->txdu++;
 903
 904         if(ctlr->ntq > 0){
 905                 coherence();
 906                 csr8w(ctlr, Tppoll, Npq);
 907         }
 908         unlock(ctlr);
 909 }
 910
 911 static void
 912 rtl8169receive(Ether* edev)
 913 {
 914         D *d;
 915         Block *bp;
 916         Ctlr *ctlr;
 917         u32int control;
 918         int x;
 919
 920         ctlr = edev->ctlr;
 921         x = ctlr->rdh;
 922         for(;;){
 923                 d = &ctlr->rd[x];
 924                 if((control = d->control) & Own)
 925                         break;
 926
 927                 bp = ctlr->rb[x];
 928                 ctlr->rb[x] = nil;
 929                 ctlr->nrq--;
 930
 931                 x = NEXT(x, ctlr->nrd);
 932                 ctlr->rdh = x;
 933
 934                 if(ctlr->nrq < ctlr->nrd/2)
 935                         rtl8169replenish(ctlr);
 936
 937                 if((control & (Fs|Ls|Res)) == (Fs|Ls)){
 938                         bp->wp = bp->rp + (control & RxflMASK) - 4;
 939
 940                         if(control & Fovf)
 941                                 ctlr->fovf++;
 942                         if(control & Mar)
 943                                 ctlr->mcast++;
 944
 945                         switch(control & (Pid1|Pid0)){
 946                         default:
 947                                 break;
 948                         case Pid0:
 949                                 if(control & Tcpf){
 950                                         ctlr->tcpf++;
 951                                         break;
 952                                 }
 953                                 bp->flag |= Btcpck;
 954                                 break;
 955                         case Pid1:
 956                                 if(control & Udpf){
 957                                         ctlr->udpf++;
 958                                         break;
 959                                 }
 960                                 bp->flag |= Budpck;
 961                                 break;
 962                         case Pid1|Pid0:
 963                                 if(control & Ipf){
 964                                         ctlr->ipf++;
 965                                         break;
 966                                 }
 967                                 bp->flag |= Bipck;
 968                                 break;
 969                         }
 970                         etheriq(edev, bp, 1);
 971                 }else{
 972                         if(!(control & Res))
 973                                 ctlr->frag++;
 974                         freeb(bp);
 975                 }
 976         }
 977 }
 978
 979 static void
 980 rtl8169restart(Ctlr *ctlr)
 981 {
 982         ctlr->imr = 0;
 983         rtl8169halt(ctlr);
 984         wakeup(&ctlr->reset);
 985 }
 986
 987 static void
 988 rtl8169interrupt(Ureg*, void* arg)
 989 {
 990         Ctlr *ctlr;
 991         Ether *edev;
 992         u32int isr;
 993
 994         edev = arg;
 995         ctlr = edev->ctlr;
 996
 997         while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
 998                 csr16w(ctlr, Isr, isr);
 999                 if((isr & ctlr->imr) == 0)
1000                         break;
1001
1002                 if(isr & Serr)
1003                         ctlr->serr++;
1004                 if(isr & Fovw)
1005                         ctlr->fovw++;
1006                 if(isr & Rer)
1007                         ctlr->rer++;
1008                 if(isr & Rdu)
1009                         ctlr->rdu++;
1010                 if(isr & Punlc)
1011                         ctlr->punlc++;
1012
1013                 if(isr & (Serr|Fovw)){
1014                         rtl8169restart(ctlr);
1015                         break;
1016                 }
1017
1018                 if(isr & (Punlc|Rdu|Rer|Rok))
1019                         rtl8169receive(edev);
1020
1021                 if(isr & (Tdu|Ter|Tok))
1022                         rtl8169transmit(edev);
1023
1024                 if(isr & Punlc)
1025                         rtl8169link(edev);
1026         }
1027 }
1028
1029 int
1030 vetmacv(Ctlr *ctlr, uint *macv)
1031 {
1032         *macv = csr32r(ctlr, Tcr) & HwveridMASK;
1033         switch(*macv){
1034         default:
1035                 return -1;
1036         case Macv01:
1037         case Macv02:
1038         case Macv03:
1039         case Macv04:
1040         case Macv05:
1041         case Macv07:
1042         case Macv07a:
1043         case Macv11:
1044         case Macv12:
1045         case Macv12a:
1046         case Macv13:
1047         case Macv14:
1048         case Macv15:
1049         case Macv25:
1050         case Macv26:
1051         case Macv27:
1052         case Macv28:
1053         case Macv29:
1054         case Macv30:
1055         case Macv40:
1056         case Macv44:
1057                 break;
1058         }
1059         return 0;
1060 }
1061
1062 static void
1063 rtl8169pci(void)
1064 {
1065         Pcidev *p;
1066         Ctlr *ctlr;
1067         int i, port, pcie;
1068         uint macv;
1069
1070         p = nil;
1071         while(p = pcimatch(p, 0, 0)){
1072                 if(p->ccrb != 0x02 || p->ccru != 0)
1073                         continue;
1074
1075                 pcie = 0;
1076                 switch(i = ((p->did<<16)|p->vid)){
1077                 default:
1078                         continue;
1079                 case Rtl8100e:                  /* RTL810[01]E ? */
1080                 case Rtl8168b:                  /* RTL8168B */
1081                         pcie = 1;
1082                         break;
1083                 case Rtl8169c:                  /* RTL8169C */
1084                 case Rtl8169sc:                 /* RTL8169SC */
1085                 case Rtl8169:                   /* RTL8169 */
1086                         break;
1087                 case (0xC107<<16)|0x1259:       /* Corega CG-LAPCIGT */
1088                         i = Rtl8169;
1089                         break;
1090                 }
1091
1092                 port = p->mem[0].bar & ~0x01;
1093                 if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
1094                         print("rtl8169: port %#ux in use\n", port);
1095                         continue;
1096                 }
1097                 ctlr = malloc(sizeof(Ctlr));
1098                 if(ctlr == nil){
1099                         print("rtl8169: can't allocate memory\n");
1100                         iofree(port);
1101                         continue;
1102                 }
1103                 ctlr->port = port;
1104                 ctlr->pcidev = p;
1105                 ctlr->pciv = i;
1106                 ctlr->pcie = pcie;
1107
1108                 if(vetmacv(ctlr, &macv) == -1){
1109                         iofree(port);
1110                         free(ctlr);
1111                         print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1112                         continue;
1113                 }
1114
1115                 if(pcigetpms(p) > 0){
1116                         pcisetpms(p, 0);
1117
1118                         for(i = 0; i < 6; i++)
1119                                 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1120                         pcicfgw8(p, PciINTL, p->intl);
1121                         pcicfgw8(p, PciLTR, p->ltr);
1122                         pcicfgw8(p, PciCLS, p->cls);
1123                         pcicfgw16(p, PciPCR, p->pcr);
1124                 }
1125
1126                 if(rtl8169reset(ctlr)){
1127                         iofree(port);
1128                         free(ctlr);
1129                         print("rtl8169: reset failed\n");
1130                         continue;
1131                 }
1132
1133                 /*
1134                  * Extract the chip hardware version,
1135                  * needed to configure each properly.
1136                  */
1137                 ctlr->macv = macv;
1138
1139                 rtl8169mii(ctlr);
1140
1141                 pcisetbme(p);
1142
1143                 if(rtl8169ctlrhead != nil)
1144                         rtl8169ctlrtail->next = ctlr;
1145                 else
1146                         rtl8169ctlrhead = ctlr;
1147                 rtl8169ctlrtail = ctlr;
1148         }
1149 }
1150
1151 static int
1152 rtl8169pnp(Ether* edev)
1153 {
1154         u32int r;
1155         Ctlr *ctlr;
1156         uchar ea[Eaddrlen];
1157         static int once;
1158
1159         if(once == 0){
1160                 once = 1;
1161                 rtl8169pci();
1162         }
1163
1164         /*
1165          * Any adapter matches if no edev->port is supplied,
1166          * otherwise the ports must match.
1167          */
1168         for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1169                 if(ctlr->active)
1170                         continue;
1171                 if(edev->port == 0 || edev->port == ctlr->port){
1172                         ctlr->active = 1;
1173                         break;
1174                 }
1175         }
1176         if(ctlr == nil)
1177                 return -1;
1178
1179         edev->ctlr = ctlr;
1180         edev->port = ctlr->port;
1181         edev->irq = ctlr->pcidev->intl;
1182         edev->tbdf = ctlr->pcidev->tbdf;
1183         edev->mbps = 100;
1184         edev->maxmtu = Mtu;
1185
1186         /*
1187          * Check if the adapter's station address is to be overridden.
1188          * If not, read it from the device and set in edev->ea.
1189          */
1190         memset(ea, 0, Eaddrlen);
1191         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1192                 r = csr32r(ctlr, Idr0);
1193                 edev->ea[0] = r;
1194                 edev->ea[1] = r>>8;
1195                 edev->ea[2] = r>>16;
1196                 edev->ea[3] = r>>24;
1197                 r = csr32r(ctlr, Idr0+4);
1198                 edev->ea[4] = r;
1199                 edev->ea[5] = r>>8;
1200         }
1201
1202         edev->attach = rtl8169attach;
1203         edev->transmit = rtl8169transmit;
1204         edev->interrupt = rtl8169interrupt;
1205         edev->ifstat = rtl8169ifstat;
1206
1207         edev->arg = edev;
1208         edev->promiscuous = rtl8169promiscuous;
1209         edev->multicast = rtl8169multicast;
1210
1211         rtl8169link(edev);
1212
1213         return 0;
1214 }
1215
1216 void
1217 ether8169link(void)
1218 {
1219         addethercard("rtl8169", rtl8169pnp);
1220 }