sys/src/9/pc/ether8139.c

   1 /*
   2  * Realtek 8139 (but not the 8129).
   3  * Error recovery for the various over/under -flow conditions
   4  * may need work.
   5  */
   6 #include "u.h"
   7 #include "../port/lib.h"
   8 #include "mem.h"
   9 #include "dat.h"
  10 #include "fns.h"
  11 #include "io.h"
  12 #include "../port/error.h"
  13 #include "../port/netif.h"
  14 #include "../port/etherif.h"
  15
  16 enum {                                  /* registers */
  17         Idr0            = 0x0000,       /* MAC address */
  18         Mar0            = 0x0008,       /* Multicast address */
  19         Tsd0            = 0x0010,       /* Transmit Status Descriptor0 */
  20         Tsad0           = 0x0020,       /* Transmit Start Address Descriptor0 */
  21         Rbstart         = 0x0030,       /* Receive Buffer Start Address */
  22         Erbcr           = 0x0034,       /* Early Receive Byte Count */
  23         Ersr            = 0x0036,       /* Early Receive Status */
  24         Cr              = 0x0037,       /* Command Register */
  25         Capr            = 0x0038,       /* Current Address of Packet Read */
  26         Cbr             = 0x003A,       /* Current Buffer Address */
  27         Imr             = 0x003C,       /* Interrupt Mask */
  28         Isr             = 0x003E,       /* Interrupt Status */
  29         Tcr             = 0x0040,       /* Transmit Configuration */
  30         Rcr             = 0x0044,       /* Receive Configuration */
  31         Tctr            = 0x0048,       /* Timer Count */
  32         Mpc             = 0x004C,       /* Missed Packet Counter */
  33         Cr9346          = 0x0050,       /* 9346 Command Register */
  34         Config0         = 0x0051,       /* Configuration Register 0 */
  35         Config1         = 0x0052,       /* Configuration Register 1 */
  36         TimerInt        = 0x0054,       /* Timer Interrupt */
  37         Msr             = 0x0058,       /* Media Status */
  38         Config3         = 0x0059,       /* Configuration Register 3 */
  39         Config4         = 0x005A,       /* Configuration Register 4 */
  40         Mulint          = 0x005C,       /* Multiple Interrupt Select */
  41         RerID           = 0x005E,       /* PCI Revision ID */
  42         Tsad            = 0x0060,       /* Transmit Status of all Descriptors */
  43
  44         Bmcr            = 0x0062,       /* Basic Mode Control */
  45         Bmsr            = 0x0064,       /* Basic Mode Status */
  46         Anar            = 0x0066,       /* Auto-Negotiation Advertisment */
  47         Anlpar          = 0x0068,       /* Auto-Negotiation Link Partner */
  48         Aner            = 0x006A,       /* Auto-Negotiation Expansion */
  49         Dis             = 0x006C,       /* Disconnect Counter */
  50         Fcsc            = 0x006E,       /* False Carrier Sense Counter */
  51         Nwaytr          = 0x0070,       /* N-way Test */
  52         Rec             = 0x0072,       /* RX_ER Counter */
  53         Cscr            = 0x0074,       /* CS Configuration */
  54         Phy1parm        = 0x0078,       /* PHY Parameter 1 */
  55         Twparm          = 0x007C,       /* Twister Parameter */
  56         Phy2parm        = 0x0080,       /* PHY Parameter 2 */
  57 };
  58
  59 enum {                                  /* Cr */
  60         Bufe            = 0x01,         /* Rx Buffer Empty */
  61         Te              = 0x04,         /* Transmitter Enable */
  62         Re              = 0x08,         /* Receiver Enable */
  63         Rst             = 0x10,         /* Software Reset */
  64 };
  65
  66 enum {                                  /* Imr/Isr */
  67         Rok             = 0x0001,       /* Receive OK */
  68         Rer             = 0x0002,       /* Receive Error */
  69         Tok             = 0x0004,       /* Transmit OK */
  70         Ter             = 0x0008,       /* Transmit Error */
  71         Rxovw           = 0x0010,       /* Receive Buffer Overflow */
  72         PunLc           = 0x0020,       /* Packet Underrun or Link Change */
  73         Fovw            = 0x0040,       /* Receive FIFO Overflow */
  74         Clc             = 0x2000,       /* Cable Length Change */
  75         Timerbit        = 0x4000,       /* Timer */
  76         Serr            = 0x8000,       /* System Error */
  77 };
  78
  79 enum {                                  /* Tcr */
  80         Clrabt          = 0x00000001,   /* Clear Abort */
  81         TxrrSHIFT       = 4,            /* Transmit Retry Count */
  82         TxrrMASK        = 0x000000F0,
  83         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
  84         MtxdmaMASK      = 0x00000700,
  85         Mtxdma2048      = 0x00000700,
  86         Acrc            = 0x00010000,   /* Append CRC (not) */
  87         LbkSHIFT        = 17,           /* Loopback Test */
  88         LbkMASK         = 0x00060000,
  89         Rtl8139ArevG    = 0x00800000,   /* RTL8139A Rev. G ID */
  90         IfgSHIFT        = 24,           /* Interframe Gap */
  91         IfgMASK         = 0x03000000,
  92         HwveridSHIFT    = 26,           /* Hardware Version ID */
  93         HwveridMASK     = 0x7C000000,
  94 };
  95
  96 enum {                                  /* Rcr */
  97         Aap             = 0x00000001,   /* Accept All Packets */
  98         Apm             = 0x00000002,   /* Accept Physical Match */
  99         Am              = 0x00000004,   /* Accept Multicast */
 100         Ab              = 0x00000008,   /* Accept Broadcast */
 101         Ar              = 0x00000010,   /* Accept Runt */
 102         Aer             = 0x00000020,   /* Accept Error */
 103         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
 104         Wrap            = 0x00000080,   /* Rx Buffer Wrap Control */
 105         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 106         MrxdmaMASK      = 0x00000700,
 107         Mrxdmaunlimited = 0x00000700,
 108         RblenSHIFT      = 11,           /* Receive Buffer Length */
 109         RblenMASK       = 0x00001800,
 110         Rblen8K         = 0x00000000,   /* 8KB+16 */
 111         Rblen16K        = 0x00000800,   /* 16KB+16 */
 112         Rblen32K        = 0x00001000,   /* 32KB+16 */
 113         Rblen64K        = 0x00001800,   /* 64KB+16 */
 114         RxfthSHIFT      = 13,           /* Receive Buffer Length */
 115         RxfthMASK       = 0x0000E000,
 116         Rxfth256        = 0x00008000,
 117         Rxfthnone       = 0x0000E000,
 118         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
 119         MulERINT        = 0x00020000,   /* Multiple Early Interrupt Select */
 120         ErxthSHIFT      = 24,           /* Early Rx Threshold */
 121         ErxthMASK       = 0x0F000000,
 122         Erxthnone       = 0x00000000,
 123 };
 124
 125 enum {                                  /* Received Packet Status */
 126         Rcok            = 0x0001,       /* Receive Completed OK */
 127         Fae             = 0x0002,       /* Frame Alignment Error */
 128         Crc             = 0x0004,       /* CRC Error */
 129         Long            = 0x0008,       /* Long Packet */
 130         Runt            = 0x0010,       /* Runt Packet Received */
 131         Ise             = 0x0020,       /* Invalid Symbol Error */
 132         Bar             = 0x2000,       /* Broadcast Address Received */
 133         Pam             = 0x4000,       /* Physical Address Matched */
 134         Mar             = 0x8000,       /* Multicast Address Received */
 135 };
 136
 137 enum {                                  /* Media Status Register */
 138         Rxpf            = 0x01,         /* Pause Flag */
 139         Txpf            = 0x02,         /* Pause Flag */
 140         Linkb           = 0x04,         /* Inverse of Link Status */
 141         Speed10         = 0x08,         /* 10Mbps */
 142         Auxstatus       = 0x10,         /* Aux. Power Present Status */
 143         Rxfce           = 0x40,         /* Receive Flow Control Enable */
 144         Txfce           = 0x80,         /* Transmit Flow Control Enable */
 145 };
 146
 147 typedef struct Td Td;
 148 struct Td {                     /* Soft Transmit Descriptor */
 149         int     tsd;
 150         int     tsad;
 151         uchar*  data;
 152         Block*  bp;
 153 };
 154
 155 enum {                                  /* Tsd0 */
 156         SizeSHIFT       = 0,            /* Descriptor Size */
 157         SizeMASK        = 0x00001FFF,
 158         Own             = 0x00002000,
 159         Tun             = 0x00004000,   /* Transmit FIFO Underrun */
 160         Tcok            = 0x00008000,   /* Transmit COmpleted OK */
 161         EtxthSHIFT      = 16,           /* Early Tx Threshold */
 162         EtxthMASK       = 0x001F0000,
 163         NccSHIFT        = 24,           /* Number of Collisions Count */
 164         NccMASK         = 0x0F000000,
 165         Cdh             = 0x10000000,   /* CD Heartbeat */
 166         Owc             = 0x20000000,   /* Out of Window Collision */
 167         Tabt            = 0x40000000,   /* Transmit Abort */
 168         Crs             = 0x80000000,   /* Carrier Sense Lost */
 169 };
 170
 171 enum {
 172         Rblen           = Rblen64K,     /* Receive Buffer Length */
 173         Ntd             = 4,            /* Number of Transmit Descriptors */
 174         Tdbsz           = ROUNDUP(sizeof(Etherpkt), 4),
 175 };
 176
 177 typedef struct Ctlr Ctlr;
 178 typedef struct Ctlr {
 179         int     port;
 180         Pcidev* pcidev;
 181         Ctlr*   next;
 182         int     active;
 183         int     id;
 184
 185         QLock   alock;                  /* attach */
 186         Lock    ilock;                  /* init */
 187         void*   alloc;                  /* base of per-Ctlr allocated data */
 188
 189         int     pcie;                   /* flag: pci-express device? */
 190
 191         uvlong  mchash;                 /* multicast hash */
 192
 193         int     rcr;                    /* receive configuration register */
 194         uchar*  rbstart;                /* receive buffer */
 195         int     rblen;                  /* receive buffer length */
 196         int     ierrs;                  /* receive errors */
 197
 198         Lock    tlock;                  /* transmit */
 199         Td      td[Ntd];
 200         int     ntd;                    /* descriptors active */
 201         int     tdh;                    /* host index into td */
 202         int     tdi;                    /* interface index into td */
 203         int     etxth;                  /* early transmit threshold */
 204         int     taligned;               /* packet required no alignment */
 205         int     tunaligned;             /* packet required alignment */
 206
 207         int     dis;                    /* disconnect counter */
 208         int     fcsc;                   /* false carrier sense counter */
 209         int     rec;                    /* RX_ER counter */
 210         uint    mcast;
 211 } Ctlr;
 212
 213 static Ctlr* ctlrhead;
 214 static Ctlr* ctlrtail;
 215
 216 #define csr8r(c, r)     (inb((c)->port+(r)))
 217 #define csr16r(c, r)    (ins((c)->port+(r)))
 218 #define csr32r(c, r)    (inl((c)->port+(r)))
 219 #define csr8w(c, r, b)  (outb((c)->port+(r), (int)(b)))
 220 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
 221 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
 222
 223 static void
 224 rtl8139promiscuous(void* arg, int on)
 225 {
 226         Ether *edev;
 227         Ctlr * ctlr;
 228
 229         edev = arg;
 230         ctlr = edev->ctlr;
 231         ilock(&ctlr->ilock);
 232
 233         if(on)
 234                 ctlr->rcr |= Aap;
 235         else
 236                 ctlr->rcr &= ~Aap;
 237         csr32w(ctlr, Rcr, ctlr->rcr);
 238         iunlock(&ctlr->ilock);
 239 }
 240
 241 enum {
 242         /* everyone else uses 0x04c11db7, but they both produce the same crc */
 243         Etherpolybe = 0x04c11db6,
 244         Bytemask = (1<<8) - 1,
 245 };
 246
 247 static ulong
 248 ethercrcbe(uchar *addr, long len)
 249 {
 250         int i, j;
 251         ulong c, crc, carry;
 252
 253         crc = ~0UL;
 254         for (i = 0; i < len; i++) {
 255                 c = addr[i];
 256                 for (j = 0; j < 8; j++) {
 257                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
 258                         crc <<= 1;
 259                         c >>= 1;
 260                         if (carry)
 261                                 crc = (crc ^ Etherpolybe) | carry;
 262                 }
 263         }
 264         return crc;
 265 }
 266
 267 static ulong
 268 swabl(ulong l)
 269 {
 270         return l>>24 | (l>>8) & (Bytemask<<8) |
 271                 (l<<8) & (Bytemask<<16) | l<<24;
 272 }
 273
 274 static void
 275 rtl8139multicast(void* ether, uchar *eaddr, int add)
 276 {
 277         Ether *edev;
 278         Ctlr *ctlr;
 279
 280         if (!add)
 281                 return; /* ok to keep receiving on old mcast addrs */
 282
 283         edev = ether;
 284         ctlr = edev->ctlr;
 285         ilock(&ctlr->ilock);
 286
 287         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
 288
 289         ctlr->rcr |= Am;
 290         csr32w(ctlr, Rcr, ctlr->rcr);
 291
 292         /* pci-e variants reverse the order of the hash byte registers */
 293         if (0 && ctlr->pcie) {
 294                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
 295                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
 296         } else {
 297                 csr32w(ctlr, Mar0,   ctlr->mchash);
 298                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
 299         }
 300
 301         iunlock(&ctlr->ilock);
 302 }
 303
 304 static long
 305 rtl8139ifstat(Ether* edev, void* a, long n, ulong offset)
 306 {
 307         int l;
 308         char *p;
 309         Ctlr *ctlr;
 310
 311         ctlr = edev->ctlr;
 312         p = smalloc(READSTR);
 313         l = snprint(p, READSTR, "rcr %#8.8ux\n", ctlr->rcr);
 314         l += snprint(p+l, READSTR-l, "multicast %ud\n", ctlr->mcast);
 315         l += snprint(p+l, READSTR-l, "ierrs %d\n", ctlr->ierrs);
 316         l += snprint(p+l, READSTR-l, "etxth %d\n", ctlr->etxth);
 317         l += snprint(p+l, READSTR-l, "taligned %d\n", ctlr->taligned);
 318         l += snprint(p+l, READSTR-l, "tunaligned %d\n", ctlr->tunaligned);
 319         ctlr->dis += csr16r(ctlr, Dis);
 320         l += snprint(p+l, READSTR-l, "dis %d\n", ctlr->dis);
 321         ctlr->fcsc += csr16r(ctlr, Fcsc);
 322         l += snprint(p+l, READSTR-l, "fcscnt %d\n", ctlr->fcsc);
 323         ctlr->rec += csr16r(ctlr, Rec);
 324         l += snprint(p+l, READSTR-l, "rec %d\n", ctlr->rec);
 325
 326         l += snprint(p+l, READSTR-l, "Tcr %#8.8lux\n", csr32r(ctlr, Tcr));
 327         l += snprint(p+l, READSTR-l, "Config0 %#2.2ux\n", csr8r(ctlr, Config0));
 328         l += snprint(p+l, READSTR-l, "Config1 %#2.2ux\n", csr8r(ctlr, Config1));
 329         l += snprint(p+l, READSTR-l, "Msr %#2.2ux\n", csr8r(ctlr, Msr));
 330         l += snprint(p+l, READSTR-l, "Config3 %#2.2ux\n", csr8r(ctlr, Config3));
 331         l += snprint(p+l, READSTR-l, "Config4 %#2.2ux\n", csr8r(ctlr, Config4));
 332
 333         l += snprint(p+l, READSTR-l, "Bmcr %#4.4ux\n", csr16r(ctlr, Bmcr));
 334         l += snprint(p+l, READSTR-l, "Bmsr %#4.4ux\n", csr16r(ctlr, Bmsr));
 335         l += snprint(p+l, READSTR-l, "Anar %#4.4ux\n", csr16r(ctlr, Anar));
 336         l += snprint(p+l, READSTR-l, "Anlpar %#4.4ux\n", csr16r(ctlr, Anlpar));
 337         l += snprint(p+l, READSTR-l, "Aner %#4.4ux\n", csr16r(ctlr, Aner));
 338         l += snprint(p+l, READSTR-l, "Nwaytr %#4.4ux\n", csr16r(ctlr, Nwaytr));
 339         snprint(p+l, READSTR-l, "Cscr %#4.4ux\n", csr16r(ctlr, Cscr));
 340         n = readstr(offset, a, n, p);
 341         free(p);
 342
 343         return n;
 344 }
 345
 346 static int
 347 rtl8139reset(Ctlr* ctlr)
 348 {
 349         int timeo;
 350
 351         /*
 352          * Soft reset the controller.
 353          */
 354         csr8w(ctlr, Cr, Rst);
 355         for(timeo = 0; timeo < 1000; timeo++){
 356                 if(!(csr8r(ctlr, Cr) & Rst))
 357                         return 0;
 358                 delay(1);
 359         }
 360
 361         return -1;
 362 }
 363
 364 static void
 365 rtl8139halt(Ctlr* ctlr)
 366 {
 367         int i;
 368
 369         csr8w(ctlr, Cr, 0);
 370         csr16w(ctlr, Imr, 0);
 371         csr16w(ctlr, Isr, ~0);
 372
 373         for(i = 0; i < Ntd; i++){
 374                 if(ctlr->td[i].bp == nil)
 375                         continue;
 376                 freeb(ctlr->td[i].bp);
 377                 ctlr->td[i].bp = nil;
 378         }
 379 }
 380
 381 static void
 382 rtl8139init(Ether* edev)
 383 {
 384         int i;
 385         ulong r;
 386         Ctlr *ctlr;
 387         uchar *alloc;
 388
 389         ctlr = edev->ctlr;
 390         ilock(&ctlr->ilock);
 391
 392         rtl8139halt(ctlr);
 393
 394         /*
 395          * MAC Address.
 396          */
 397         r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
 398         csr32w(ctlr, Idr0, r);
 399         r = (edev->ea[5]<<8)|edev->ea[4];
 400         csr32w(ctlr, Idr0+4, r);
 401
 402         /*
 403          * Receiver
 404          */
 405         alloc = ctlr->alloc;
 406         ctlr->rbstart = alloc;
 407         alloc += ctlr->rblen+16;
 408         memset(ctlr->rbstart, 0, ctlr->rblen+16);
 409         csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
 410         ctlr->rcr = Rxfth256|Rblen|Mrxdmaunlimited|Ab|Am|Apm;
 411
 412         /*
 413          * Transmitter.
 414          */
 415         for(i = 0; i < Ntd; i++){
 416                 ctlr->td[i].tsd = Tsd0+i*4;
 417                 ctlr->td[i].tsad = Tsad0+i*4;
 418                 ctlr->td[i].data = alloc;
 419                 alloc += Tdbsz;
 420                 ctlr->td[i].bp = nil;
 421         }
 422         ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
 423         ctlr->etxth = 128/32;
 424
 425         /*
 426          * Interrupts.
 427          */
 428         csr32w(ctlr, TimerInt, 0);
 429         csr16w(ctlr, Imr, Serr|Timerbit|Fovw|PunLc|Rxovw|Ter|Tok|Rer|Rok);
 430         csr32w(ctlr, Mpc, 0);
 431
 432         /*
 433          * Enable receiver/transmitter.
 434          * Need to enable before writing the Rcr or it won't take.
 435          */
 436         csr8w(ctlr, Cr, Te|Re);
 437         csr32w(ctlr, Tcr, Mtxdma2048);
 438         csr32w(ctlr, Rcr, ctlr->rcr);
 439         csr32w(ctlr, Mar0,   0);
 440         csr32w(ctlr, Mar0+4, 0);
 441         ctlr->mchash = 0;
 442
 443         iunlock(&ctlr->ilock);
 444 }
 445
 446 static void
 447 rtl8139attach(Ether* edev)
 448 {
 449         Ctlr *ctlr;
 450
 451         ctlr = edev->ctlr;
 452         qlock(&ctlr->alock);
 453         if(ctlr->alloc == nil){
 454                 ctlr->rblen = 1<<((Rblen>>RblenSHIFT)+13);
 455                 ctlr->alloc = mallocalign(ctlr->rblen+16 + Ntd*Tdbsz, 32, 0, 0);
 456                 if(ctlr->alloc == nil){
 457                         qunlock(&ctlr->alock);
 458                         error(Enomem);
 459                 }
 460                 rtl8139init(edev);
 461         }
 462         qunlock(&ctlr->alock);
 463 }
 464
 465 static void
 466 rtl8139txstart(Ether* edev)
 467 {
 468         Td *td;
 469         int size;
 470         Block *bp;
 471         Ctlr *ctlr;
 472
 473         ctlr = edev->ctlr;
 474         while(ctlr->ntd < Ntd){
 475                 bp = qget(edev->oq);
 476                 if(bp == nil)
 477                         break;
 478                 size = BLEN(bp);
 479
 480                 td = &ctlr->td[ctlr->tdh];
 481                 if(((uintptr)bp->rp) & 0x03){
 482                         memmove(td->data, bp->rp, size);
 483                         freeb(bp);
 484                         csr32w(ctlr, td->tsad, PCIWADDR(td->data));
 485                         ctlr->tunaligned++;
 486                 }
 487                 else{
 488                         td->bp = bp;
 489                         csr32w(ctlr, td->tsad, PCIWADDR(bp->rp));
 490                         ctlr->taligned++;
 491                 }
 492                 csr32w(ctlr, td->tsd, (ctlr->etxth<<EtxthSHIFT)|size);
 493
 494                 ctlr->ntd++;
 495                 ctlr->tdh = NEXT(ctlr->tdh, Ntd);
 496         }
 497 }
 498
 499 static void
 500 rtl8139transmit(Ether* edev)
 501 {
 502         Ctlr *ctlr;
 503
 504         ctlr = edev->ctlr;
 505         ilock(&ctlr->tlock);
 506         rtl8139txstart(edev);
 507         iunlock(&ctlr->tlock);
 508 }
 509
 510 static void
 511 rtl8139receive(Ether* edev)
 512 {
 513         Block *bp;
 514         Ctlr *ctlr;
 515         ushort capr;
 516         uchar cr, *p;
 517         int l, length, status;
 518
 519         ctlr = edev->ctlr;
 520
 521         /*
 522          * Capr is where the host is reading from,
 523          * Cbr is where the NIC is currently writing.
 524          */
 525         capr = (csr16r(ctlr, Capr)+16) % ctlr->rblen;
 526         while(!(csr8r(ctlr, Cr) & Bufe)){
 527                 p = ctlr->rbstart+capr;
 528
 529                 /*
 530                  * Apparently the packet length may be 0xFFF0 if
 531                  * the NIC is still copying the packet into memory.
 532                  */
 533                 length = (*(p+3)<<8)|*(p+2);
 534                 if(length == 0xFFF0)
 535                         break;
 536                 status = (*(p+1)<<8)|*p;
 537
 538                 if(!(status & Rcok)){
 539                         if(status & (Ise|Fae))
 540                                 edev->frames++;
 541                         if(status & Crc)
 542                                 edev->crcs++;
 543                         if(status & (Runt|Long))
 544                                 edev->buffs++;
 545
 546                         /*
 547                          * Reset the receiver.
 548                          * Also may have to restore the multicast list
 549                          * here too if it ever gets used.
 550                          */
 551                         cr = csr8r(ctlr, Cr);
 552                         csr8w(ctlr, Cr, cr & ~Re);
 553                         csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
 554                         csr8w(ctlr, Cr, cr);
 555                         csr32w(ctlr, Rcr, ctlr->rcr);
 556
 557                         continue;
 558                 }
 559
 560                 /*
 561                  * Receive Completed OK.
 562                  * Very simplistic; there are ways this could be done
 563                  * without copying, but the juice probably isn't worth
 564                  * the squeeze.
 565                  * The packet length includes a 4 byte CRC on the end.
 566                  */
 567                 capr = (capr+4) % ctlr->rblen;
 568                 p = ctlr->rbstart+capr;
 569                 capr = (capr+length) % ctlr->rblen;
 570                 if(status & Mar)
 571                         ctlr->mcast++;
 572
 573                 if((bp = iallocb(length)) != nil){
 574                         if(p+length >= ctlr->rbstart+ctlr->rblen){
 575                                 l = ctlr->rbstart+ctlr->rblen - p;
 576                                 memmove(bp->wp, p, l);
 577                                 bp->wp += l;
 578                                 length -= l;
 579                                 p = ctlr->rbstart;
 580                         }
 581                         if(length > 0){
 582                                 memmove(bp->wp, p, length);
 583                                 bp->wp += length;
 584                         }
 585                         bp->wp -= 4;
 586                         etheriq(edev, bp);
 587                 }
 588
 589                 capr = ROUNDUP(capr, 4);
 590                 csr16w(ctlr, Capr, capr-16);
 591         }
 592 }
 593
 594 static void
 595 rtl8139interrupt(Ureg*, void* arg)
 596 {
 597         Td *td;
 598         Ctlr *ctlr;
 599         Ether *edev;
 600         int isr, msr, tsd;
 601
 602         edev = arg;
 603         ctlr = edev->ctlr;
 604
 605         while((isr = csr16r(ctlr, Isr)) != 0){
 606                 csr16w(ctlr, Isr, isr);
 607                 if(isr & (Fovw|PunLc|Rxovw|Rer|Rok)){
 608                         rtl8139receive(edev);
 609                         if(!(isr & Rok))
 610                                 ctlr->ierrs++;
 611                         isr &= ~(Fovw|Rxovw|Rer|Rok);
 612                 }
 613
 614                 if(isr & (Ter|Tok)){
 615                         ilock(&ctlr->tlock);
 616                         while(ctlr->ntd){
 617                                 td = &ctlr->td[ctlr->tdi];
 618                                 tsd = csr32r(ctlr, td->tsd);
 619                                 if(!(tsd & (Tabt|Tun|Tcok)))
 620                                         break;
 621
 622                                 if(!(tsd & Tcok)){
 623                                         if(tsd & Tun){
 624                                                 if(ctlr->etxth < ETHERMAXTU/32)
 625                                                         ctlr->etxth++;
 626                                         }
 627                                         edev->oerrs++;
 628                                 }
 629
 630                                 if(td->bp != nil){
 631                                         freeb(td->bp);
 632                                         td->bp = nil;
 633                                 }
 634
 635                                 ctlr->ntd--;
 636                                 ctlr->tdi = NEXT(ctlr->tdi, Ntd);
 637                         }
 638                         rtl8139txstart(edev);
 639                         iunlock(&ctlr->tlock);
 640                         isr &= ~(Ter|Tok);
 641                 }
 642
 643                 if(isr & PunLc){
 644                         /*
 645                          * Maybe the link changed - do we care very much?
 646                          */
 647                         msr = csr8r(ctlr, Msr);
 648                         if(!(msr & Linkb)){
 649                                 if(!(msr & Speed10) && edev->mbps != 100){
 650                                         edev->mbps = 100;
 651                                         qsetlimit(edev->oq, 256*1024);
 652                                 }
 653                                 else if((msr & Speed10) && edev->mbps != 10){
 654                                         edev->mbps = 10;
 655                                         qsetlimit(edev->oq, 65*1024);
 656                                 }
 657                         }
 658                         isr &= ~(Clc|PunLc);
 659                 }
 660
 661                 /*
 662                  * Only Serr|Timerbit should be left by now.
 663                  * Should anything be done to tidy up? TimerInt isn't
 664                  * used so that can be cleared. A PCI bus error is indicated
 665                  * by Serr, that's pretty serious; is there anyhing to do
 666                  * other than try to reinitialise the chip?
 667                  */
 668                 if((isr & (Serr|Timerbit)) != 0){
 669                         iprint("rtl8139interrupt: imr %#4.4ux isr %#4.4ux\n",
 670                                 csr16r(ctlr, Imr), isr);
 671                         if(isr & Timerbit)
 672                                 csr32w(ctlr, TimerInt, 0);
 673                         if(isr & Serr)
 674                                 rtl8139init(edev);
 675                 }
 676         }
 677 }
 678
 679 static Ctlr*
 680 rtl8139match(Ether* edev, int id)
 681 {
 682         Pcidev *p;
 683         Ctlr *ctlr;
 684         int port;
 685
 686         /*
 687          * Any adapter matches if no edev->port is supplied,
 688          * otherwise the ports must match.
 689          */
 690         for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
 691                 if(ctlr->active)
 692                         continue;
 693                 p = ctlr->pcidev;
 694                 if(((p->did<<16)|p->vid) != id)
 695                         continue;
 696                 port = p->mem[0].bar & ~0x01;
 697                 if(edev->port != 0 && edev->port != port)
 698                         continue;
 699
 700                 if(ioalloc(port, p->mem[0].size, 0, "rtl8139") < 0){
 701                         print("rtl8139: port %#ux in use\n", port);
 702                         continue;
 703                 }
 704                 pcienable(p);
 705                 ctlr->port = port;
 706                 if(rtl8139reset(ctlr)) {
 707                         pcidisable(p);
 708                         iofree(port);
 709                         continue;
 710                 }
 711                 pcisetbme(p);
 712
 713                 ctlr->active = 1;
 714                 return ctlr;
 715         }
 716         return nil;
 717 }
 718
 719 static struct {
 720         char*   name;
 721         int     id;
 722 } rtl8139pci[] = {
 723         { "rtl8139",    (0x8139<<16)|0x10EC, }, /* generic */
 724         { "smc1211",    (0x1211<<16)|0x1113, }, /* SMC EZ-Card */
 725         { "dfe-538tx",  (0x1300<<16)|0x1186, }, /* D-Link DFE-538TX */
 726         { "dfe-560txd", (0x1340<<16)|0x1186, }, /* D-Link DFE-560TXD */
 727         { nil },
 728 };
 729
 730 static int
 731 rtl8139pnp(Ether* edev)
 732 {
 733         int i, id;
 734         Pcidev *p;
 735         Ctlr *ctlr;
 736         uchar ea[Eaddrlen];
 737
 738         /*
 739          * Make a list of all ethernet controllers
 740          * if not already done.
 741          */
 742         if(ctlrhead == nil){
 743                 p = nil;
 744                 while(p = pcimatch(p, 0, 0)){
 745                         if(p->ccrb != 0x02 || p->ccru != 0)
 746                                 continue;
 747                         ctlr = malloc(sizeof(Ctlr));
 748                         if(ctlr == nil){
 749                                 print("rtl8139: can't allocate memory\n");
 750                                 continue;
 751                         }
 752                         ctlr->pcidev = p;
 753                         ctlr->id = (p->did<<16)|p->vid;
 754
 755                         if(ctlrhead != nil)
 756                                 ctlrtail->next = ctlr;
 757                         else
 758                                 ctlrhead = ctlr;
 759                         ctlrtail = ctlr;
 760                 }
 761         }
 762
 763         /*
 764          * Is it an RTL8139 under a different name?
 765          * Normally a search is made through all the found controllers
 766          * for one which matches any of the known vid+did pairs.
 767          * If a vid+did pair is specified a search is made for that
 768          * specific controller only.
 769          */
 770         id = 0;
 771         for(i = 0; i < edev->nopt; i++){
 772                 if(cistrncmp(edev->opt[i], "id=", 3) == 0)
 773                         id = strtol(&edev->opt[i][3], nil, 0);
 774         }
 775
 776         ctlr = nil;
 777         if(id != 0)
 778                 ctlr = rtl8139match(edev, id);
 779         else for(i = 0; rtl8139pci[i].name; i++){
 780                 if((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != nil)
 781                         break;
 782         }
 783         if(ctlr == nil)
 784                 return -1;
 785
 786         edev->ctlr = ctlr;
 787         edev->port = ctlr->port;
 788         edev->irq = ctlr->pcidev->intl;
 789         edev->tbdf = ctlr->pcidev->tbdf;
 790
 791         /*
 792          * Check if the adapter's station address is to be overridden.
 793          * If not, read it from the device and set in edev->ea.
 794          */
 795         memset(ea, 0, Eaddrlen);
 796         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
 797                 i = csr32r(ctlr, Idr0);
 798                 edev->ea[0] = i;
 799                 edev->ea[1] = i>>8;
 800                 edev->ea[2] = i>>16;
 801                 edev->ea[3] = i>>24;
 802                 i = csr32r(ctlr, Idr0+4);
 803                 edev->ea[4] = i;
 804                 edev->ea[5] = i>>8;
 805         }
 806
 807         edev->attach = rtl8139attach;
 808         edev->transmit = rtl8139transmit;
 809         edev->ifstat = rtl8139ifstat;
 810
 811         edev->arg = edev;
 812         edev->promiscuous = rtl8139promiscuous;
 813         edev->multicast = rtl8139multicast;
 814 //      edev->shutdown = rtl8139shutdown;
 815
 816         intrenable(edev->irq, rtl8139interrupt, edev, edev->tbdf, edev->name);
 817
 818         /*
 819          * This should be much more dynamic but will do for now.
 820          */
 821         if((csr8r(ctlr, Msr) & (Speed10|Linkb)) == 0)
 822                 edev->mbps = 100;
 823
 824         return 0;
 825 }
 826
 827 void
 828 ether8139link(void)
 829 {
 830         addethercard("rtl8139", rtl8139pnp);
 831 }