sys/src/9/pc/ether79c970.c

   1 /*
   2  * AMD79C970
   3  * PCnet-PCI Single-Chip Ethernet Controller for PCI Local Bus
   4  * To do:
   5  *      finish this rewrite
   6  */
   7 #include "u.h"
   8 #include "../port/lib.h"
   9 #include "mem.h"
  10 #include "dat.h"
  11 #include "fns.h"
  12 #include "io.h"
  13 #include "../port/error.h"
  14 #include "../port/netif.h"
  15
  16 #include "etherif.h"
  17
  18 enum {
  19         Lognrdre        = 6,
  20         Nrdre           = (1<<Lognrdre),/* receive descriptor ring entries */
  21         Logntdre        = 4,
  22         Ntdre           = (1<<Logntdre),/* transmit descriptor ring entries */
  23
  24         Rbsize          = ETHERMAXTU+4, /* ring buffer size (+4 for CRC) */
  25 };
  26
  27 enum {                                  /* DWIO I/O resource map */
  28         Aprom           = 0x0000,       /* physical address */
  29         Rdp             = 0x0010,       /* register data port */
  30         Rap             = 0x0014,       /* register address port */
  31         Sreset          = 0x0018,       /* software reset */
  32         Bdp             = 0x001C,       /* bus configuration register data port */
  33 };
  34
  35 enum {                                  /* CSR0 */
  36         Init            = 0x0001,       /* begin initialisation */
  37         Strt            = 0x0002,       /* enable chip */
  38         Stop            = 0x0004,       /* disable chip */
  39         Tdmd            = 0x0008,       /* transmit demand */
  40         Txon            = 0x0010,       /* transmitter on */
  41         Rxon            = 0x0020,       /* receiver on */
  42         Iena            = 0x0040,       /* interrupt enable */
  43         Intr            = 0x0080,       /* interrupt flag */
  44         Idon            = 0x0100,       /* initialisation done */
  45         Tint            = 0x0200,       /* transmit interrupt */
  46         Rint            = 0x0400,       /* receive interrupt */
  47         Merr            = 0x0800,       /* memory error */
  48         Miss            = 0x1000,       /* missed frame */
  49         Cerr            = 0x2000,       /* collision */
  50         Babl            = 0x4000,       /* transmitter timeout */
  51         Err             = 0x8000,       /* Babl|Cerr|Miss|Merr */
  52 };
  53
  54 enum {                                  /* CSR3 */
  55         Bswp            = 0x0004,       /* byte swap */
  56         Emba            = 0x0008,       /* enable modified back-off algorithm */
  57         Dxmt2pd         = 0x0010,       /* disable transmit two part deferral */
  58         Lappen          = 0x0020,       /* look-ahead packet processing enable */
  59 };
  60
  61 enum {                                  /* CSR4 */
  62         ApadXmt         = 0x0800,       /* auto pad transmit */
  63 };
  64
  65 enum {                                  /* CSR15 */
  66         Prom            = 0x8000,       /* promiscuous mode */
  67 };
  68
  69 typedef struct Iblock Iblock;
  70 struct Iblock {                 /* Initialisation Block */
  71         ushort  mode;
  72         uchar   rlen;                   /* upper 4 bits */
  73         uchar   tlen;                   /* upper 4 bits */
  74         uchar   padr[6];
  75         uchar   res[2];
  76         uchar   ladr[8];
  77         ulong   rdra;
  78         ulong   tdra;
  79 };
  80
  81 typedef struct Dre Dre;
  82 struct Dre {                    /* descriptor ring entry */
  83         ulong   addr;
  84         ulong   md1;                    /* status|bcnt */
  85         ulong   md2;                    /* rcc|rpc|mcnt */
  86         ulong   aux;
  87 };
  88
  89
  90 enum {                                  /* md1 */
  91         Enp             = 0x01000000,   /* end of packet */
  92         Stp             = 0x02000000,   /* start of packet */
  93         RxBuff          = 0x04000000,   /* buffer error */
  94         Def             = 0x04000000,   /* deferred */
  95         Crc             = 0x08000000,   /* CRC error */
  96         One             = 0x08000000,   /* one retry needed */
  97         Oflo            = 0x10000000,   /* overflow error */
  98         More            = 0x10000000,   /* more than one retry needed */
  99         Fram            = 0x20000000,   /* framing error */
 100         RxErr           = 0x40000000,   /* Fram|Oflo|Crc|RxBuff */
 101         TxErr           = 0x40000000,   /* Uflo|Lcol|Lcar|Rtry */
 102         Own             = 0x80000000,
 103 };
 104
 105 enum {                                  /* md2 */
 106         Rtry            = 0x04000000,   /* failed after repeated retries */
 107         Lcar            = 0x08000000,   /* loss of carrier */
 108         Lcol            = 0x10000000,   /* late collision */
 109         Uflo            = 0x40000000,   /* underflow error */
 110         TxBuff          = 0x80000000,   /* buffer error */
 111 };
 112
 113 typedef struct Ctlr Ctlr;
 114 struct Ctlr {
 115         Lock;
 116         int     port;
 117         Pcidev* pcidev;
 118         Ctlr*   next;
 119         int     active;
 120
 121         int     init;                   /* initialisation in progress */
 122         Iblock  iblock;
 123
 124         Block** rb;
 125         Dre*    rdr;                    /* receive descriptor ring */
 126         int     rdrx;
 127
 128         Block** tb;
 129         Dre*    tdr;                    /* transmit descriptor ring */
 130         int     tdrh;                   /* host index into tdr */
 131         int     tdri;                   /* interface index into tdr */
 132         int     ntq;                    /* descriptors active */
 133
 134         ulong   rxbuff;                 /* receive statistics */
 135         ulong   crc;
 136         ulong   oflo;
 137         ulong   fram;
 138
 139         ulong   rtry;                   /* transmit statistics */
 140         ulong   lcar;
 141         ulong   lcol;
 142         ulong   uflo;
 143         ulong   txbuff;
 144
 145         ulong   merr;                   /* bobf is such a whiner */
 146         ulong   miss;
 147         ulong   babl;
 148
 149         int     (*ior)(Ctlr*, int);
 150         void    (*iow)(Ctlr*, int, int);
 151 };
 152
 153 static Ctlr* ctlrhead;
 154 static Ctlr* ctlrtail;
 155
 156 /*
 157  * The Rdp, Rap, Sreset, Bdp ports are 32-bit port offset in the enumeration above.
 158  * To get to 16-bit offsets, scale down with 0x10 staying the same.
 159  */
 160 static int
 161 io16r(Ctlr *c, int r)
 162 {
 163         if(r >= Rdp)
 164                 r = (r-Rdp)/2+Rdp;
 165         return ins(c->port+r);
 166 }
 167
 168 static void
 169 io16w(Ctlr *c, int r, int v)
 170 {
 171         if(r >= Rdp)
 172                 r = (r-Rdp)/2+Rdp;
 173         outs(c->port+r, v);
 174 }
 175
 176 static int
 177 io32r(Ctlr *c, int r)
 178 {
 179         return inl(c->port+r);
 180 }
 181
 182 static void
 183 io32w(Ctlr *c, int r, int v)
 184 {
 185         outl(c->port+r, v);
 186 }
 187
 188 static void
 189 attach(Ether*)
 190 {
 191 }
 192
 193 static long
 194 ifstat(Ether* ether, void* a, long n, ulong offset)
 195 {
 196         char *p;
 197         int len;
 198         Ctlr *ctlr;
 199
 200         ctlr = ether->ctlr;
 201
 202         ether->crcs = ctlr->crc;
 203         ether->frames = ctlr->fram;
 204         ether->buffs = ctlr->rxbuff+ctlr->txbuff;
 205         ether->overflows = ctlr->oflo;
 206
 207         if(n == 0)
 208                 return 0;
 209
 210         p = smalloc(READSTR);
 211         len = snprint(p, READSTR, "Rxbuff: %ld\n", ctlr->rxbuff);
 212         len += snprint(p+len, READSTR-len, "Crc: %ld\n", ctlr->crc);
 213         len += snprint(p+len, READSTR-len, "Oflo: %ld\n", ctlr->oflo);
 214         len += snprint(p+len, READSTR-len, "Fram: %ld\n", ctlr->fram);
 215         len += snprint(p+len, READSTR-len, "Rtry: %ld\n", ctlr->rtry);
 216         len += snprint(p+len, READSTR-len, "Lcar: %ld\n", ctlr->lcar);
 217         len += snprint(p+len, READSTR-len, "Lcol: %ld\n", ctlr->lcol);
 218         len += snprint(p+len, READSTR-len, "Uflo: %ld\n", ctlr->uflo);
 219         len += snprint(p+len, READSTR-len, "Txbuff: %ld\n", ctlr->txbuff);
 220         len += snprint(p+len, READSTR-len, "Merr: %ld\n", ctlr->merr);
 221         len += snprint(p+len, READSTR-len, "Miss: %ld\n", ctlr->miss);
 222         snprint(p+len, READSTR-len, "Babl: %ld\n", ctlr->babl);
 223
 224         n = readstr(offset, a, n, p);
 225         free(p);
 226
 227         return n;
 228 }
 229
 230 static void
 231 ringinit(Ctlr* ctlr)
 232 {
 233         Block *bp;
 234         Dre *dre;
 235         int i;
 236
 237         /*
 238          * Initialise the receive and transmit buffer rings.
 239          * The ring entries must be aligned on 16-byte boundaries.
 240          *
 241          * This routine is protected by ctlr->init.
 242          */
 243         if(ctlr->rb == nil)
 244                 ctlr->rb = malloc(Nrdre*sizeof(Block*));
 245         if(ctlr->rdr == 0){
 246                 ctlr->rdr = xspanalloc(Nrdre*sizeof(Dre), 0x10, 0);
 247                 for(i=0; i<Nrdre; i++){
 248                         bp = iallocb(Rbsize);
 249                         if(bp == nil)
 250                                 panic("can't allocate ethernet receive ring");
 251                         ctlr->rb[i] = bp;
 252                         dre = &ctlr->rdr[i];
 253                         dre->addr = PADDR(bp->rp);
 254                         dre->md2 = 0;
 255                         dre->md1 = Own|(-Rbsize & 0xFFFF);
 256                         dre->aux = 0;
 257                 }
 258         }
 259         ctlr->rdrx = 0;
 260
 261         if(ctlr->tb == nil)
 262                 ctlr->tb = malloc(Ntdre*sizeof(Block*));
 263         if(ctlr->tdr == 0)
 264                 ctlr->tdr = xspanalloc(Ntdre*sizeof(Dre), 0x10, 0);
 265         memset(ctlr->tdr, 0, Ntdre*sizeof(Dre));
 266         ctlr->tdrh = ctlr->tdri = 0;
 267 }
 268
 269 static void
 270 promiscuous(void* arg, int on)
 271 {
 272         Ether *ether;
 273         int x;
 274         Ctlr *ctlr;
 275
 276         ether = arg;
 277         ctlr = ether->ctlr;
 278
 279         /*
 280          * Put the chip into promiscuous mode. First must wait until
 281          * anyone transmitting is done, then stop the chip and put
 282          * it in promiscuous mode. Restarting is made harder by the chip
 283          * reloading the transmit and receive descriptor pointers with their
 284          * base addresses when Strt is set (unlike the older Lance chip),
 285          * so the rings must be re-initialised.
 286          */
 287         ilock(ctlr);
 288         if(ctlr->init){
 289                 iunlock(ctlr);
 290                 return;
 291         }
 292         ctlr->init = 1;
 293         iunlock(ctlr);
 294
 295         while(ctlr->ntq)
 296                 ;
 297
 298         ctlr->iow(ctlr, Rdp, Stop);
 299
 300         ctlr->iow(ctlr, Rap, 15);
 301         x = ctlr->ior(ctlr, Rdp) & ~Prom;
 302         if(on)
 303                 x |= Prom;
 304         ctlr->iow(ctlr, Rdp, x);
 305         ctlr->iow(ctlr, Rap, 0);
 306
 307         ringinit(ctlr);
 308
 309         ilock(ctlr);
 310         ctlr->init = 0;
 311         ctlr->iow(ctlr, Rdp, Iena|Strt);
 312         iunlock(ctlr);
 313 }
 314
 315 static void
 316 multicast(void* arg, uchar*, int)
 317 {
 318         promiscuous(arg, 1);
 319 }
 320
 321 static void
 322 txstart(Ether* ether)
 323 {
 324         Ctlr *ctlr;
 325         Block *bp;
 326         Dre *dre;
 327         int i;
 328
 329         ctlr = ether->ctlr;
 330
 331         if(ctlr->init)
 332                 return;
 333
 334         while(ctlr->ntq < (Ntdre-1)){
 335                 bp = qget(ether->oq);
 336                 if(bp == nil)
 337                         break;
 338
 339                 /*
 340                  * Give ownership of the descriptor to the chip,
 341                  * increment the software ring descriptor pointer
 342                  * and tell the chip to poll.
 343                  * There's no need to pad to ETHERMINTU
 344                  * here as ApadXmt is set in CSR4.
 345                  */
 346                 i = ctlr->tdrh;
 347                 if(ctlr->tb[i] != nil)
 348                         break;
 349                 dre = &ctlr->tdr[i];
 350                 ctlr->tb[i] = bp;
 351                 dre->addr = PADDR(bp->rp);
 352                 dre->md2 = 0;
 353                 dre->md1 = Own|Stp|Enp|(-BLEN(bp) & 0xFFFF);
 354                 ctlr->ntq++;
 355                 ctlr->iow(ctlr, Rdp, Iena|Tdmd);
 356                 ctlr->tdrh = NEXT(ctlr->tdrh, Ntdre);
 357         }
 358 }
 359
 360 static void
 361 transmit(Ether* ether)
 362 {
 363         Ctlr *ctlr;
 364
 365         ctlr = ether->ctlr;
 366         ilock(ctlr);
 367         txstart(ether);
 368         iunlock(ctlr);
 369 }
 370
 371 static void
 372 interrupt(Ureg*, void* arg)
 373 {
 374         Ctlr *ctlr;
 375         Ether *ether;
 376         int csr0, len, i;
 377         Dre *dre;
 378         Block *bp, *bb;
 379
 380         ether = arg;
 381         ctlr = ether->ctlr;
 382
 383         /*
 384          * Acknowledge all interrupts and whine about those that shouldn't
 385          * happen.
 386          */
 387 intrloop:
 388         csr0 = ctlr->ior(ctlr, Rdp) & 0xFFFF;
 389         ctlr->iow(ctlr, Rdp, Babl|Cerr|Miss|Merr|Rint|Tint|Iena);
 390         if(csr0 & Merr)
 391                 ctlr->merr++;
 392         if(csr0 & Miss)
 393                 ctlr->miss++;
 394         if(csr0 & Babl)
 395                 ctlr->babl++;
 396         //if(csr0 & (Babl|Miss|Merr))
 397         //      print("#l%d: csr0 = 0x%uX\n", ether->ctlrno, csr0);
 398         if(!(csr0 & (Rint|Tint)))
 399                 return;
 400
 401         /*
 402          * Receiver interrupt: run round the descriptor ring logging
 403          * errors and passing valid receive data up to the higher levels
 404          * until a descriptor is encountered still owned by the chip.
 405          */
 406         if(csr0 & Rint){
 407                 ilock(ctlr);
 408                 i = ctlr->rdrx;
 409                 dre = &ctlr->rdr[i];
 410                 while(!(dre->md1 & Own)){
 411                         if(dre->md1 & RxErr){
 412                                 if(dre->md1 & RxBuff)
 413                                         ctlr->rxbuff++;
 414                                 if(dre->md1 & Crc)
 415                                         ctlr->crc++;
 416                                 if(dre->md1 & Oflo)
 417                                         ctlr->oflo++;
 418                                 if(dre->md1 & Fram)
 419                                         ctlr->fram++;
 420                         }
 421                         else if(bp = iallocb(Rbsize)){
 422                                 bb = ctlr->rb[i];
 423                                 ctlr->rb[i] = bp;
 424                                 if(bb != nil){
 425                                         len = (dre->md2 & 0x0FFF)-4;
 426                                         bb->wp = bb->rp+len;
 427                                         etheriq(ether, bb, 1);
 428                                 }
 429                                 dre->addr = PADDR(bp->rp);
 430                         }
 431
 432                         /*
 433                          * Finished with this descriptor, reinitialise it,
 434                          * give it back to the chip, then on to the next...
 435                          */
 436                         dre->md2 = 0;
 437                         dre->md1 = Own|(-Rbsize & 0xFFFF);
 438
 439                         i = ctlr->rdrx = NEXT(ctlr->rdrx, Nrdre);
 440                         dre = &ctlr->rdr[i];
 441                 }
 442                 iunlock(ctlr);
 443         }
 444
 445         /*
 446          * Transmitter interrupt: wakeup anyone waiting for a free descriptor.
 447          */
 448         if(csr0 & Tint){
 449                 ilock(ctlr);
 450                 while(ctlr->ntq){
 451                         i = ctlr->tdri;
 452                         dre = &ctlr->tdr[i];
 453                         if(dre->md1 & Own)
 454                                 break;
 455
 456                         if(dre->md1 & TxErr){
 457                                 if(dre->md2 & Rtry)
 458                                         ctlr->rtry++;
 459                                 if(dre->md2 & Lcar)
 460                                         ctlr->lcar++;
 461                                 if(dre->md2 & Lcol)
 462                                         ctlr->lcol++;
 463                                 if(dre->md2 & Uflo)
 464                                         ctlr->uflo++;
 465                                 if(dre->md2 & TxBuff)
 466                                         ctlr->txbuff++;
 467                                 ether->oerrs++;
 468                         }
 469                         bp = ctlr->tb[i];
 470                         if(bp != nil){
 471                                 ctlr->tb[i] = nil;
 472                                 freeb(bp);
 473                         }
 474
 475                         ctlr->ntq--;
 476                         ctlr->tdri = NEXT(ctlr->tdri, Ntdre);
 477                 }
 478                 txstart(ether);
 479                 iunlock(ctlr);
 480         }
 481         goto intrloop;
 482 }
 483
 484 static void
 485 amd79c970pci(void)
 486 {
 487         int port;
 488         Ctlr *ctlr;
 489         Pcidev *p;
 490
 491         p = nil;
 492         while(p = pcimatch(p, 0x1022, 0x2000)){
 493                 port = p->mem[0].bar & ~0x01;
 494                 if(ioalloc(port, p->mem[0].size, 0, "amd79c970") < 0){
 495                         print("amd79c970: port 0x%uX in use\n", port);
 496                         continue;
 497                 }
 498                 ctlr = malloc(sizeof(Ctlr));
 499                 if(ctlr == nil){
 500                         print("amd79c970: can't allocate memory\n");
 501                         iofree(port);
 502                         continue;
 503                 }
 504                 ctlr->port = p->mem[0].bar & ~0x01;
 505                 ctlr->pcidev = p;
 506
 507                 if(ctlrhead != nil)
 508                         ctlrtail->next = ctlr;
 509                 else
 510                         ctlrhead = ctlr;
 511                 ctlrtail = ctlr;
 512         }
 513 }
 514
 515 static int
 516 reset(Ether* ether)
 517 {
 518         int x;
 519         uchar ea[Eaddrlen];
 520         Ctlr *ctlr;
 521
 522         if(ctlrhead == nil)
 523                 amd79c970pci();
 524
 525         /*
 526          * Any adapter matches if no port is supplied,
 527          * otherwise the ports must match.
 528          */
 529         for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
 530                 if(ctlr->active)
 531                         continue;
 532                 if(ether->port == 0 || ether->port == ctlr->port){
 533                         ctlr->active = 1;
 534                         break;
 535                 }
 536         }
 537         if(ctlr == nil)
 538                 return -1;
 539
 540         /*
 541          * Allocate a controller structure and start to initialise it.
 542          */
 543         ether->ctlr = ctlr;
 544         ether->port = ctlr->port;
 545         ether->irq = ctlr->pcidev->intl;
 546         ether->tbdf = ctlr->pcidev->tbdf;
 547         pcisetbme(ctlr->pcidev);
 548         ilock(ctlr);
 549         ctlr->init = 1;
 550
 551         io32r(ctlr, Sreset);
 552         io16r(ctlr, Sreset);
 553
 554         if(io16w(ctlr, Rap, 0), io16r(ctlr, Rdp) == 4){
 555                 ctlr->ior = io16r;
 556                 ctlr->iow = io16w;
 557         }else if(io32w(ctlr, Rap, 0), io32r(ctlr, Rdp) == 4){
 558                 ctlr->ior = io32r;
 559                 ctlr->iow = io32w;
 560         }else{
 561                 print("#l%d: card doesn't talk right\n", ether->ctlrno);
 562                 iunlock(ctlr);
 563                 return -1;
 564         }
 565
 566         ctlr->iow(ctlr, Rap, 88);
 567         x = ctlr->ior(ctlr, Rdp);
 568         ctlr->iow(ctlr, Rap, 89);
 569         x |= ctlr->ior(ctlr, Rdp)<<16;
 570
 571         switch(x&0xFFFFFFF){
 572         case 0x2420003: /* PCnet/PCI 79C970 */
 573         case 0x2621003: /* PCnet/PCI II 79C970A */
 574         case 0x2625003: /* PCnet-FAST III 79C973 */
 575                 break;
 576         default:
 577                 print("#l%d: unknown PCnet card version 0x%.7ux\n",
 578                         ether->ctlrno, x&0xFFFFFFF);
 579                 iunlock(ctlr);
 580                 return -1;
 581         }
 582
 583         /*
 584          * Set the software style in BCR20 to be PCnet-PCI to ensure 32-bit access.
 585          * Set the auto pad transmit in CSR4.
 586          */
 587         ctlr->iow(ctlr, Rap, 20);
 588         ctlr->iow(ctlr, Bdp, 0x0002);
 589
 590         ctlr->iow(ctlr, Rap, 4);
 591         x = ctlr->ior(ctlr, Rdp) & 0xFFFF;
 592         ctlr->iow(ctlr, Rdp, ApadXmt|x);
 593
 594         ctlr->iow(ctlr, Rap, 0);
 595
 596         /*
 597          * Check if the adapter's station address is to be overridden.
 598          * If not, read it from the I/O-space and set in ether->ea prior to
 599          * loading the station address in the initialisation block.
 600          */
 601         memset(ea, 0, Eaddrlen);
 602         if(!memcmp(ea, ether->ea, Eaddrlen)){
 603                 x = ctlr->ior(ctlr, Aprom);
 604                 ether->ea[0] = x;
 605                 ether->ea[1] = x>>8;
 606                 if(ctlr->ior == io16r)
 607                         x = ctlr->ior(ctlr, Aprom+2);
 608                 else
 609                         x >>= 16;
 610                 ether->ea[2] = x;
 611                 ether->ea[3] = x>>8;
 612                 x = ctlr->ior(ctlr, Aprom+4);
 613                 ether->ea[4] = x;
 614                 ether->ea[5] = x>>8;
 615         }
 616
 617         /*
 618          * Start to fill in the initialisation block
 619          * (must be DWORD aligned).
 620          */
 621         ctlr->iblock.rlen = Lognrdre<<4;
 622         ctlr->iblock.tlen = Logntdre<<4;
 623         memmove(ctlr->iblock.padr, ether->ea, sizeof(ctlr->iblock.padr));
 624
 625         ringinit(ctlr);
 626         ctlr->iblock.rdra = PADDR(ctlr->rdr);
 627         ctlr->iblock.tdra = PADDR(ctlr->tdr);
 628
 629         /*
 630          * Point the chip at the initialisation block and tell it to go.
 631          * Mask the Idon interrupt and poll for completion. Strt and interrupt
 632          * enables will be set later when attaching to the network.
 633          */
 634         x = PADDR(&ctlr->iblock);
 635         ctlr->iow(ctlr, Rap, 1);
 636         ctlr->iow(ctlr, Rdp, x & 0xFFFF);
 637         ctlr->iow(ctlr, Rap, 2);
 638         ctlr->iow(ctlr, Rdp, (x>>16) & 0xFFFF);
 639         ctlr->iow(ctlr, Rap, 3);
 640         ctlr->iow(ctlr, Rdp, Idon);
 641         ctlr->iow(ctlr, Rap, 0);
 642         ctlr->iow(ctlr, Rdp, Init);
 643
 644         while(!(ctlr->ior(ctlr, Rdp) & Idon))
 645                 ;
 646
 647         /*
 648          * We used to set CSR0 to Idon|Stop here, and then
 649          * in attach change it to Iena|Strt.  Apparently the simulated
 650          * 79C970 in VMware never enables after a write of Idon|Stop,
 651          * so we enable the device here now.
 652          */
 653         ctlr->iow(ctlr, Rdp, Iena|Strt);
 654         ctlr->init = 0;
 655         iunlock(ctlr);
 656
 657         /*
 658          * Linkage to the generic ethernet driver.
 659          */
 660         ether->attach = attach;
 661         ether->transmit = transmit;
 662         ether->interrupt = interrupt;
 663         ether->ifstat = ifstat;
 664
 665         ether->arg = ether;
 666         ether->promiscuous = promiscuous;
 667         ether->multicast = multicast;
 668 //      ether->shutdown = shutdown;
 669
 670         return 0;
 671 }
 672
 673 void
 674 ether79c970link(void)
 675 {
 676         addethercard("AMD79C970",  reset);
 677 }