2 #include "../port/lib.h"
7 typedef struct DMAport DMAport;
8 typedef struct DMA DMA;
9 typedef struct DMAxfer DMAxfer;
12 * state of a dma transfer
16 ulong bpa; /* bounce buffer physical address */
17 void* bva; /* bounce buffer virtual address */
18 int blen; /* bounce buffer length */
19 void* va; /* virtual address destination/src */
20 long len; /* bytes to be transferred */
25 * the dma controllers. the first half of this structure specifies
26 * the I/O ports used by the DMA controllers.
30 uchar addr[4]; /* current address (4 channels) */
31 uchar count[4]; /* current count (4 channels) */
32 uchar page[4]; /* page registers (4 channels) */
33 uchar cmd; /* command status register */
34 uchar req; /* request registers */
35 uchar sbm; /* single bit mask register */
36 uchar mode; /* mode register */
37 uchar cbp; /* clear byte pointer */
38 uchar mc; /* master clear */
39 uchar cmask; /* clear mask register */
40 uchar wam; /* write all mask register bit */
52 { 0x00, 0x02, 0x04, 0x06,
53 0x01, 0x03, 0x05, 0x07,
54 0x87, 0x83, 0x81, 0x82,
55 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
58 { 0xc0, 0xc4, 0xc8, 0xcc,
59 0xc2, 0xc6, 0xca, 0xce,
60 0x8f, 0x8b, 0x89, 0x8a,
61 0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde,
66 static void* i8237bva[2];
70 * DMA must be in the first 16MB. This gets called early by the
71 * initialisation routines of any devices which require DMA to ensure
72 * the allocated bounce buffers are below the 16MB limit.
84 bva = xspanalloc(64*1024*i8237dma, 0, 64*1024);
85 if(bva == nil || PADDR(bva)+64*1024*i8237dma > 16*MB){
87 * This will panic with the current
88 * implementation of xspanalloc().
97 i8237bva[1] = ((uchar*)i8237bva[0])+64*1024;
101 * DMA must be in the first 16MB. This gets called early by the
102 * initialisation routines of any devices which require DMA to ensure
103 * the allocated bounce buffers are below the 16MB limit.
106 dmainit(int chan, int maxtransfer)
113 if(ioalloc(0x00, 0x10, 0, "dma") < 0
114 || ioalloc(0x80, 0x10, 0, "dma") < 0
115 || ioalloc(0xd0, 0x10, 0, "dma") < 0)
120 if(maxtransfer > 64*1024)
121 maxtransfer = 64*1024;
123 dp = &dma[(chan>>2)&1];
127 if(xp->blen < maxtransfer)
132 if(i8237used >= i8237dma || i8237bva[i8237used] == nil){
133 print("no i8237 DMA bounce buffer < 16MB\n");
136 xp->bva = i8237bva[i8237used++];
137 xp->bpa = PADDR(xp->bva);
138 xp->blen = maxtransfer;
151 dp = &dma[(chan>>2)&1];
163 dp = &dma[(chan>>2)&1];
166 retval = inb(dp->count[chan]);
167 retval |= inb(dp->count[chan]) << 8;
169 return ((retval<<dp->shift)+1) & 0xFFFF;
173 * setup a dma transfer. if the destination is not in kernel
174 * memory, allocate a page for the transfer.
176 * we assume BIOS has set up the command register before we
179 * return the updated transfer length (we can't transfer across 64k
183 dmasetup(int chan, void *va, long len, int flags)
190 dp = &dma[(chan>>2)&1];
195 * if this isn't kernel memory or crossing 64k boundary or above 16 meg
196 * use the bounce buffer.
199 || ((pa=PADDR(va))&0xFFFF0000) != ((pa+len)&0xFFFF0000)
205 if(!(flags & DMAREAD))
206 memmove(xp->bva, va, len);
215 mode = ((flags & DMAREAD) ? 0x44 : 0x48) | /* read or write */
216 ((flags & DMALOOP) ? 0x10 : 0) | /* auto init mode */
220 * this setup must be atomic
223 outb(dp->mode, mode);
224 outb(dp->page[chan], pa>>16);
225 outb(dp->cbp, 0); /* set count & address to their first byte */
226 outb(dp->addr[chan], pa>>dp->shift); /* set address */
227 outb(dp->addr[chan], pa>>(8+dp->shift));
228 outb(dp->count[chan], (len>>dp->shift)-1); /* set count */
229 outb(dp->count[chan], ((len>>dp->shift)-1)>>8);
230 outb(dp->sbm, chan); /* enable the channel */
241 dp = &dma[(chan>>2)&1];
244 return inb(dp->cmd) & (1<<chan);
248 * this must be called after a dma has been completed.
250 * if a page has been allocated for the dma,
251 * copy the data into the actual destination
260 dp = &dma[(chan>>2)&1];
264 * disable the channel
267 outb(dp->sbm, 4|chan);
271 if(xp->len == 0 || !(xp->flags & DMAREAD))
275 * copy out of temporary page
277 memmove(xp->va, xp->bva, xp->len);