2 #include "../port/lib.h"
8 #include "../port/error.h"
10 /* this driver doesn't implement the management interrupts. we
11 * leave the LM78 interrupts set to whatever the BIOS did. we do
12 * allow reading and writing the the readouts and alarm values.
13 * Read(2)ing or write(2)ing at offset 0x0-0x1f, is
14 * equivalent to reading or writing lm78 registers 0x20-0x3f.
18 /* address of chip on serial interface */
21 /* parallel access registers */
26 /* internal register addresses */
33 Bnmi= (1<<5), /* if set, use nmi, else irq */
42 Rvidfan= 0x47, /* set fan counter, and read voltage level */
45 Raddr= 0x48, /* address used on serial bus */
46 Rresetid= 0x49, /* chip reset and ID register */
47 Rpost= 0x00, /* start of post ram */
48 Rvalue= 0x20, /* start of value ram */
50 VRsize= 0x20, /* size of value ram */
59 static Dirtab lm78dir[] = {
60 ".", { Qdir, 0, QTDIR}, 0, 0555,
61 "lm78vram", { Qlm78vram, 0 }, 0, 0444,
75 int ifc; /* which interface is connected */
76 SMBus *smbus; /* serial interface */
77 int port; /* parallel interface */
80 extern SMBus* piix4smbus(void);
82 /* wait for device to become quiescent and then set the */
83 /* register address */
89 for(tries = 0; tries < 1000000; tries++)
90 if((inb(lm78.port+Rpaddr) & Bbusy) == 0){
91 outb(lm78.port+Rpaddr, reg);
97 /* routines that actually touch the device */
99 lm78wrreg(int reg, uchar val)
109 lm78.smbus->transact(lm78.smbus, SMBbytewrite, Serialaddr, reg, &val);
113 outb(lm78.port+Rpdata, val);
137 lm78.smbus->transact(lm78.smbus, SMBsend, Serialaddr, reg, nil);
138 lm78.smbus->transact(lm78.smbus, SMBrecv, Serialaddr, 0, &val);
142 val = inb(lm78.port+Rpdata);
154 /* start the chip monitoring but don't change any smi
155 * interrupts and/or alarms that the BIOS may have set up.
156 * this isn't locked because it's thought to be idempotent
166 if(lm78.probed == 0){
167 /* make sure its really there */
168 if(lm78rdreg(Raddr) != Serialaddr){
172 /* start the sampling */
173 config = lm78rdreg(Rconfig);
174 config = (config | Bstart) & ~(Bintclr|Binit);
175 lm78wrreg(Rconfig, config);
176 pprint("Rvidfan %2.2ux\n", lm78rdreg(Rconfig), lm78rdreg(Rvidfan));
188 Piix4PMID= 0x7113, /* PIIX4 power management function */
190 PCSC= 0x78, /* programmable chip select control register */
194 /* figure out what kind of interface we could have */
203 while((p = pcimatch(p, IntelVendID, 0)) != nil){
205 /* these bridges use the PCSC to map the lm78 into port space. */
206 /* for this case the lm78's CS# select is connected to the PIIX's */
207 /* PCS# output and the bottom 3 bits of address are passed to the */
208 /* LM78's A0-A2 inputs. */
211 pcs = pcicfgr16(p, PCSC);
213 /* already enabled */
214 lm78.port = pcs & ~3;
219 /* enable the chip, use default address 0x50 */
220 pcicfgw16(p, PCSC, 0x50|PCSC8bytes);
221 pcs = pcicfgr16(p, PCSC);
222 lm78.port = pcs & ~3;
226 /* this bridge puts the lm78's serial interface on the smbus */
228 lm78.smbus = piix4smbus();
229 if(lm78.smbus == nil)
231 print("found piix4 smbus, base %lud\n", lm78.smbus->base);
239 lm78walk(Chan* c, Chan *nc, char** name, int nname)
241 return devwalk(c, nc, name, nname, lm78dir, nelem(lm78dir), devgen);
245 lm78stat(Chan* c, uchar* dp, int n)
247 return devstat(c, dp, n, lm78dir, nelem(lm78dir), devgen);
251 lm78open(Chan* c, int omode)
253 return devopen(c, omode, lm78dir, nelem(lm78dir), devgen);
267 lm78read(Chan *c, void *a, long n, vlong offset)
274 switch((ulong)c->qid.path){
276 return devdirread(c, a, n, lm78dir, nelem(lm78dir), devgen);
284 for(; off < e; off++)
285 *va++ = lm78rdreg(Rvalue+off);
286 return (int)(va - (uchar*)a);
292 lm78write(Chan *c, void *a, long n, vlong offset)
299 switch((ulong)c->qid.path){
309 for(; off < e; off++)
310 lm78wrreg(Rvalue+off, *va++);
311 return va - (uchar*)a;
316 extern Dev lm78devtab;
319 lm78attach(char* spec)
323 return devattach(lm78devtab.dc, spec);