2 #include "../port/lib.h"
8 #include "../port/error.h"
10 typedef struct IOMap IOMap;
25 IOMap maps[32]; /* some initial free maps */
27 QLock ql; /* lock for reading map */
47 enum { /* cpuid standard function codes */
48 Highstdfunc = 0, /* also returns vendor string */
54 typedef long Rdwrfn(Chan*, void*, long, vlong);
56 static Rdwrfn *readfn[Qmax];
57 static Rdwrfn *writefn[Qmax];
59 static Dirtab archdir[Qmax] = {
60 ".", { Qdir, 0, QTDIR }, 0, 0555,
61 "ioalloc", { Qioalloc, 0 }, 0, 0444,
62 "iob", { Qiob, 0 }, 0, 0660,
63 "iow", { Qiow, 0 }, 0, 0660,
64 "iol", { Qiol, 0 }, 0, 0660,
65 "msr", { Qmsr, 0 }, 0, 0660,
67 Lock archwlock; /* the lock is only for changing archdir */
69 int (*_pcmspecial)(char*, ISAConf*);
70 void (*_pcmspecialclose)(int);
72 static int doi8253set = 1;
75 * Add a file to the #P listing. Once added, you can't delete it.
76 * You can't add a file with the same name as one already there,
77 * and you get a pointer to the Dirtab entry so you can do things
78 * like change the Qid version. Changing the Qid path is disallowed.
81 addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
87 memset(&d, 0, sizeof d);
94 print("addarchfile: out of entries for %s\n", name);
98 for(i=0; i<narchdir; i++)
99 if(strcmp(archdir[i].name, name) == 0){
104 d.qid.path = narchdir;
105 archdir[narchdir] = d;
106 readfn[narchdir] = rdfn;
107 writefn[narchdir] = wrfn;
108 dp = &archdir[narchdir++];
120 for(i = 0; i < nelem(iomap.maps)-1; i++)
121 iomap.maps[i].next = &iomap.maps[i+1];
122 iomap.maps[i].next = nil;
123 iomap.free = iomap.maps;
126 * This is necessary to make the IBM X20 boot.
127 * Have not tracked down the reason.
128 * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
130 ioalloc(0x0fff, 1, 0, "dummy");
132 if ((excluded = getconf("ioexclude")) != nil) {
136 while (s && *s != '\0' && *s != '\n') {
140 io_s = (int)strtol(s, &ends, 0);
141 if (ends == nil || ends == s || *ends != '-') {
142 print("ioinit: cannot parse option string\n");
147 io_e = (int)strtol(s, &ends, 0);
148 if (ends && *ends == ',')
152 ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
159 * Reserve a range to be ioalloced later.
160 * This is in particular useful for exchangable cards, such
161 * as pcmcia and cardbus cards.
164 ioreserve(int, int size, int align, char *tag)
170 /* find a free port above 0x400 and below 0x1000 */
172 for(l = &iomap.m; *l; l = &(*l)->next){
174 if (m->start < 0x400) continue;
179 port = ((port+align-1)/align)*align;
189 print("ioalloc: out of maps");
193 iomap.free = m->next;
196 m->end = port + size;
198 strncpy(m->tag, tag, sizeof(m->tag)-1);
199 m->tag[sizeof(m->tag)-1] = 0;
202 archdir[0].qid.vers++;
209 * alloc some io port space and remember who it was
210 * alloced to. if port < 0, find a free region.
213 ioalloc(int port, int size, int align, char *tag)
220 /* find a free port above 0x400 and below 0x1000 */
222 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
223 if (m->start < 0x400) continue;
228 port = ((port+align-1)/align)*align;
237 /* Only 64KB I/O space on the x86. */
238 if((port+size) > 0x10000){
242 /* see if the space clashes with previously allocated ports */
243 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
246 if(m->reserved && m->start == port && m->end >= port + size) {
251 if(m->start >= port+size)
259 print("ioalloc: out of maps");
263 iomap.free = m->next;
266 m->end = port + size;
267 strncpy(m->tag, tag, sizeof(m->tag)-1);
268 m->tag[sizeof(m->tag)-1] = 0;
271 archdir[0].qid.vers++;
283 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
284 if(m->start == port){
286 m->next = iomap.free;
293 archdir[0].qid.vers++;
298 iounused(int start, int end)
302 for(m = iomap.m; m != nil; m = m->next){
303 if(start >= m->start && start < m->end
304 || start <= m->start && end > m->start)
311 checkport(int start, int end)
313 /* standard vga regs are OK */
314 if(start >= 0x2b0 && end <= 0x2df+1)
316 if(start >= 0x3c0 && end <= 0x3da+1)
319 if(iounused(start, end))
325 archattach(char* spec)
327 return devattach('P', spec);
331 archwalk(Chan* c, Chan *nc, char** name, int nname)
333 return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
337 archstat(Chan* c, uchar* dp, int n)
339 return devstat(c, dp, n, archdir, narchdir, devgen);
343 archopen(Chan* c, int omode)
345 return devopen(c, omode, archdir, narchdir, devgen);
354 archread(Chan *c, void *a, long n, vlong offset)
364 switch((ulong)c->qid.path){
366 return devdirread(c, a, n, archdir, narchdir, devgen);
370 checkport(offset, offset+n);
371 for(p = a; port < offset+n; port++)
378 checkport(offset, offset+n);
380 for(port = offset; port < offset+n; port += 2)
387 checkport(offset, offset+n);
389 for(port = offset; port < offset+n; port += 4)
397 for(port = offset; port < offset+n; port += 8)
398 if(rdmsr(port, vp++) < 0)
405 for(m = iomap.m; m != nil; m = m->next){
406 i = snprint(buf, sizeof(buf), "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
417 memmove(a, buf+offset, n);
421 if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
422 return fn(c, a, n, offset);
429 archwrite(Chan *c, void *a, long n, vlong offset)
438 switch((ulong)c->qid.path){
441 checkport(offset, offset+n);
442 for(port = offset; port < offset+n; port++)
449 checkport(offset, offset+n);
451 for(port = offset; port < offset+n; port += 2)
458 checkport(offset, offset+n);
460 for(port = offset; port < offset+n; port += 4)
468 for(port = offset; port < offset+n; port += 8)
469 if(wrmsr(port, *vp++) < 0)
474 if(c->qid.path < narchdir && (fn = writefn[c->qid.path]) != nil)
475 return fn(c, a, n, offset);
504 * the following is a generic version of the
505 * architecture specific stuff
525 * Often the BIOS hangs during restart if a conventional 8042
526 * warm-boot sequence is tried. The following is Intel specific and
527 * seems to perform a cold-boot, but at least it comes back.
528 * And sometimes there is no keyboard...
530 * The reset register (0xcf9) is usually in one of the bridge
531 * chips. The actual location and sequence could be extracted from
532 * ACPI but why bother, this is the end of the line anyway.
534 print("Takes a licking and keeps on ticking...\n");
535 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
539 print("can't reset\n");
545 * 386 has no compare-and-swap instruction.
546 * Run it with interrupts turned off instead.
549 cmpswap386(long *addr, long old, long new)
554 if(r = (*addr == old))
561 * On a uniprocessor, you'd think that coherence could be nop,
562 * but it can't. We still need a barrier when using coherence() in
565 * On VMware, it's safe (and a huge win) to set this to nop.
566 * Aux/vmware does this via the #P/archctl file.
568 void (*coherence)(void) = nop;
570 int (*cmpswap)(long*, long, long) = cmpswap386;
573 extern PCArch* knownarch[];
575 PCArch archgeneric = {
579 .serialpower= unimplemented,
580 .modempower= unimplemented,
582 .intrinit= i8259init,
583 .intrenable= i8259enable,
584 .intrvecno= i8259vecno,
585 .intrdisable= i8259disable,
589 .clockenable= i8253enable,
590 .fastclock= i8253read,
591 .timerset= i8253timerset,
594 typedef struct X86type X86type;
602 static X86type x86intel[] =
604 { 4, 0, 22, "486DX", }, /* known chips */
605 { 4, 1, 22, "486DX50", },
606 { 4, 2, 22, "486SX", },
607 { 4, 3, 22, "486DX2", },
608 { 4, 4, 22, "486SL", },
609 { 4, 5, 22, "486SX2", },
610 { 4, 7, 22, "DX2WB", }, /* P24D */
611 { 4, 8, 22, "DX4", }, /* P24C */
612 { 4, 9, 22, "DX4WB", }, /* P24CT */
615 { 5, 2, 23, "P54C", },
616 { 5, 3, 23, "P24T", },
617 { 5, 4, 23, "P55C MMX", },
618 { 5, 7, 23, "P54C VRT", },
619 { 6, 1, 16, "PentiumPro", },/* trial and error */
620 { 6, 3, 16, "PentiumII", },
621 { 6, 5, 16, "PentiumII/Xeon", },
622 { 6, 6, 16, "Celeron", },
623 { 6, 7, 16, "PentiumIII/Xeon", },
624 { 6, 8, 16, "PentiumIII/Xeon", },
625 { 6, 0xB, 16, "PentiumIII/Xeon", },
626 { 6, 0xF, 16, "Xeon5000-series", },
627 { 6, 0x16, 16, "Celeron", },
628 { 6, 0x17, 16, "Core 2/Xeon", },
629 { 6, 0x1A, 16, "Core i7/Xeon", },
630 { 6, 0x1C, 16, "Atom", },
631 { 6, 0x1D, 16, "Xeon MP", },
632 { 0xF, 1, 16, "P4", }, /* P4 */
633 { 0xF, 2, 16, "PentiumIV/Xeon", },
634 { 0xF, 6, 16, "PentiumIV/Xeon", },
636 { 3, -1, 32, "386", }, /* family defaults */
637 { 4, -1, 22, "486", },
638 { 5, -1, 23, "P5", },
639 { 6, -1, 16, "P6", },
640 { 0xF, -1, 16, "P4", }, /* P4 */
642 { -1, -1, 16, "unknown", }, /* total default */
646 * The AMD processors all implement the CPUID instruction.
647 * The later ones also return the processor name via functions
648 * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
650 * K5 "AMD-K5(tm) Processor"
651 * K6 "AMD-K6tm w/ multimedia extensions"
652 * K6 3D "AMD-K6(tm) 3D processor"
655 static X86type x86amd[] =
657 { 5, 0, 23, "AMD-K5", }, /* guesswork */
658 { 5, 1, 23, "AMD-K5", }, /* guesswork */
659 { 5, 2, 23, "AMD-K5", }, /* guesswork */
660 { 5, 3, 23, "AMD-K5", }, /* guesswork */
661 { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
662 { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
663 { 5, 6, 11, "AMD-K6", }, /* trial and error */
664 { 5, 7, 11, "AMD-K6", }, /* trial and error */
665 { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
666 { 5, 9, 11, "AMD-K6-III", },/* trial and error */
667 { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
669 { 6, 1, 11, "AMD-Athlon", },/* trial and error */
670 { 6, 2, 11, "AMD-Athlon", },/* trial and error */
672 { 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
674 { 4, -1, 22, "Am486", }, /* guesswork */
675 { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
676 { 6, -1, 11, "AMD-Athlon", },/* guesswork */
677 { 0xF, -1, 11, "AMD-K8", }, /* guesswork */
678 { 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
680 { -1, -1, 11, "unknown", }, /* total default */
686 static X86type x86winchip[] =
688 {5, 4, 23, "Winchip",}, /* guesswork */
689 {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
690 {6, 8, 23, "Via C3 Ezra-T",},
691 {6, 9, 23, "Via C3 Eden-N",},
692 { -1, -1, 23, "unknown", }, /* total default */
698 static X86type x86sis[] =
700 {5, 0, 23, "SiS 55x",}, /* guesswork */
701 { -1, -1, 23, "unknown", }, /* total default */
704 static X86type *cputype;
706 static void simplecycles(uvlong*);
707 void (*cycles)(uvlong*) = simplecycles;
708 void _cycles(uvlong*); /* in l.s */
711 simplecycles(uvlong*x)
719 print("cpu%d: %dMHz %s %s (AX %8.8uX CX %8.8uX DX %8.8uX)\n",
720 m->machno, m->cpumhz, m->cpuidid, m->cpuidtype,
721 m->cpuidax, m->cpuidcx, m->cpuiddx);
727 * - whether or not we have a TSC (cycle counter)
728 * - whether or not it supports page size extensions
730 * - whether or not it supports machine check exceptions
732 * - whether or not it supports the page global flag
739 int family, model, nomce;
745 cpuid(Highstdfunc, regs);
746 memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
747 memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
748 memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
749 m->cpuidid[12] = '\0';
751 cpuid(Procsig, regs);
752 m->cpuidax = regs[0];
753 m->cpuidcx = regs[2];
754 m->cpuiddx = regs[3];
756 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
757 strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
759 else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
761 else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
766 family = X86FAMILY(m->cpuidax);
767 model = X86MODEL(m->cpuidax);
768 for(t=tab; t->name; t++)
769 if((t->family == family && t->model == model)
770 || (t->family == family && t->model == -1)
771 || (t->family == -1))
774 m->cpuidtype = t->name;
777 * if there is one, set tsc to a known value
779 if(m->cpuiddx & Tsc){
782 if(m->cpuiddx & Cpumsr)
787 * use i8253 to guess our cpu speed
789 guesscpuhz(t->aalcycles);
792 * If machine check exception, page size extensions or page global bit
793 * are supported enable them in CR4 and clear any other set extensions.
794 * If machine check was enabled clear out any lingering status.
796 if(m->cpuiddx & (Pge|Mce|Pse)){
799 cr4 |= 0x10; /* page size extensions */
800 if(p = getconf("*nomce"))
801 nomce = strtoul(p, 0, 0);
804 if((m->cpuiddx & Mce) != 0 && !nomce){
805 if((m->cpuiddx & Mca) != 0){
813 wrmsr(0x17B, ~0ULL); /* enable all mca features */
819 /* init MCi .. MC1 (except MC0) */
821 wrmsr(0x400 + bank*4, ~0ULL);
822 wrmsr(0x401 + bank*4, 0);
825 if(family != 6 || model >= 0x1A)
830 else if(family == 5){
834 cr4 |= 0x40; /* machine check enable */
838 * Detect whether the chip supports the global bit
839 * in page directory and page table entries. When set
840 * in a particular entry, it means ``don't bother removing
841 * this from the TLB when CR3 changes.''
843 * We flag all kernel pages with this bit. Doing so lessens the
844 * overhead of switching processes on bare hardware,
845 * even more so on VMware. See mmu.c:/^memglobal.
847 * For future reference, should we ever need to do a
848 * full TLB flush, it can be accomplished by clearing
849 * the PGE bit in CR4, writing to CR3, and then
850 * restoring the PGE bit.
852 if(m->cpuiddx & Pge){
853 cr4 |= 0x80; /* page global enable bit */
859 if((m->cpuiddx & (Mca|Mce)) == Mce)
863 if(m->cpuiddx & Mtrr)
866 if((m->cpuiddx & (Sse|Fxsr)) == (Sse|Fxsr)){ /* have sse fp? */
868 fprestore = fpsserestore;
869 putcr4(getcr4() | CR4Osfxsr|CR4Oxmmex);
872 fprestore = fpx87restore;
875 if(strcmp(m->cpuidid, "GenuineIntel") == 0 && (m->cpuidcx & Rdrnd) != 0)
876 hwrandbuf = rdrandbuf;
885 cputyperead(Chan*, void *a, long n, vlong offset)
890 mhz = (m->cpuhz+999999)/1000000;
892 snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
893 return readstr(offset, a, n, str);
897 archctlread(Chan*, void *a, long nn, vlong offset)
902 p = buf = smalloc(READSTR);
904 p = seprint(p, ep, "cpu %s %lud%s\n",
905 cputype->name, (ulong)(m->cpuhz+999999)/1000000,
906 m->havepge ? " pge" : "");
907 p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
908 p = seprint(p, ep, "coherence ");
909 if(coherence == mb386)
910 p = seprint(p, ep, "mb386\n");
911 else if(coherence == mb586)
912 p = seprint(p, ep, "mb586\n");
913 else if(coherence == mfence)
914 p = seprint(p, ep, "mfence\n");
915 else if(coherence == nop)
916 p = seprint(p, ep, "nop\n");
918 p = seprint(p, ep, "0x%p\n", coherence);
919 p = seprint(p, ep, "cmpswap ");
920 if(cmpswap == cmpswap386)
921 p = seprint(p, ep, "cmpswap386\n");
922 else if(cmpswap == cmpswap486)
923 p = seprint(p, ep, "cmpswap486\n");
925 p = seprint(p, ep, "0x%p\n", cmpswap);
926 p = seprint(p, ep, "i8253set %s\n", doi8253set ? "on" : "off");
927 p = seprint(p, ep, "arch %s\n", arch->id);
929 n += mtrrprint(p, ep - p);
932 n = readstr(offset, a, nn, buf);
945 static Cmdtab archctlmsg[] =
948 CMcoherence, "coherence", 2,
949 CMi8253set, "i8253set", 2,
954 archctlwrite(Chan*, void *a, long n, vlong)
966 ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
970 error("processor does not support pge");
971 if(strcmp(cb->f[1], "on") == 0)
972 putcr4(getcr4() | 0x80);
973 else if(strcmp(cb->f[1], "off") == 0)
974 putcr4(getcr4() & ~0x80);
976 cmderror(cb, "invalid pge ctl");
979 if(strcmp(cb->f[1], "mb386") == 0)
981 else if(strcmp(cb->f[1], "mb586") == 0){
982 if(X86FAMILY(m->cpuidax) < 5)
983 error("invalid coherence ctl on this cpu family");
985 }else if(strcmp(cb->f[1], "mfence") == 0){
986 if((m->cpuiddx & Sse2) == 0)
987 error("invalid coherence ctl on this cpu family");
989 }else if(strcmp(cb->f[1], "nop") == 0){
990 /* only safe on vmware */
992 error("cannot disable coherence on a multiprocessor");
995 cmderror(cb, "invalid coherence ctl");
998 if(strcmp(cb->f[1], "on") == 0)
1000 else if(strcmp(cb->f[1], "off") == 0){
1002 (*arch->timerset)(0);
1004 cmderror(cb, "invalid i2853set ctl");
1007 base = strtoull(cb->f[1], &ep, 0);
1009 error("cache: parse error: base not a number?");
1010 size = strtoull(cb->f[2], &ep, 0);
1012 error("cache: parse error: size not a number?");
1013 ep = mtrr(base, size, cb->f[3]);
1024 rmemrw(int isr, void *a, long n, vlong off)
1028 if(off < 0 || n < 0)
1029 error("bad offset/count");
1035 memmove(a, KADDR(addr), n);
1037 /* allow vga framebuf's write access */
1038 if(addr >= MB || addr+n > MB ||
1039 (addr < 0xA0000 || addr+n > 0xB0000+0x10000))
1040 error("bad offset/count in write");
1041 memmove(KADDR(addr), a, n);
1047 rmemread(Chan*, void *a, long n, vlong off)
1049 return rmemrw(1, a, n, off);
1053 rmemwrite(Chan*, void *a, long n, vlong off)
1055 return rmemrw(0, a, n, off);
1063 arch = &archgeneric;
1064 for(p = knownarch; *p != nil; p++){
1065 if((*p)->ident != nil && (*p)->ident() == 0){
1070 if(arch != &archgeneric){
1072 arch->id = archgeneric.id;
1073 if(arch->reset == nil)
1074 arch->reset = archgeneric.reset;
1075 if(arch->serialpower == nil)
1076 arch->serialpower = archgeneric.serialpower;
1077 if(arch->modempower == nil)
1078 arch->modempower = archgeneric.modempower;
1079 if(arch->intrinit == nil)
1080 arch->intrinit = archgeneric.intrinit;
1081 if(arch->intrenable == nil)
1082 arch->intrenable = archgeneric.intrenable;
1086 * Decide whether to use copy-on-reference (386 and mp).
1087 * We get another chance to set it in mpinit() for a
1090 if(X86FAMILY(m->cpuidax) == 3)
1093 if(X86FAMILY(m->cpuidax) >= 4)
1094 cmpswap = cmpswap486;
1096 if(X86FAMILY(m->cpuidax) >= 5)
1099 if(m->cpuiddx & Sse2)
1102 addarchfile("cputype", 0444, cputyperead, nil);
1103 addarchfile("archctl", 0664, archctlread, archctlwrite);
1104 addarchfile("realmodemem", 0660, rmemread, rmemwrite);
1108 * call either the pcmcia or pccard device setup
1111 pcmspecial(char *idstr, ISAConf *isa)
1113 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
1117 * call either the pcmcia or pccard device teardown
1120 pcmspecialclose(int a)
1122 if (_pcmspecialclose != nil)
1123 _pcmspecialclose(a);
1127 * return value and speed of timer set in arch->clockenable
1130 fastticks(uvlong *hz)
1132 return (*arch->fastclock)(hz);
1138 return fastticks2us((*arch->fastclock)(nil));
1142 * set next timer interrupt
1148 (*arch->timerset)(x);
1152 * put the processor in the halt state if we've no processes to run.
1153 * an interrupt will get us going again.
1155 * halting in an smp system can result in a startup latency for
1156 * processes that become ready.
1157 * if idle_spin is zero, we care more about saving energy
1158 * than reducing this latency.
1160 * the performance loss with idle_spin == 0 seems to be slight
1161 * and it reduces lock contention (thus system time and real time)
1162 * on many-core systems with large values of NPROC.
1167 extern int nrdy, idle_spin;
1171 else if(m->cpuidcx & Monitor)
1173 else if(idle_spin == 0)
1178 isaconfig(char *class, int ctlrno, ISAConf *isa)
1183 snprint(cc, sizeof cc, "%s%d", class, ctlrno);
1189 isa->nopt = tokenize(p, isa->opt, NISAOPT);
1190 for(i = 0; i < isa->nopt; i++){
1192 if(cistrncmp(p, "type=", 5) == 0)
1194 else if(cistrncmp(p, "port=", 5) == 0)
1195 isa->port = strtoul(p+5, &p, 0);
1196 else if(cistrncmp(p, "irq=", 4) == 0)
1197 isa->irq = strtoul(p+4, &p, 0);
1198 else if(cistrncmp(p, "dma=", 4) == 0)
1199 isa->dma = strtoul(p+4, &p, 0);
1200 else if(cistrncmp(p, "mem=", 4) == 0)
1201 isa->mem = strtoul(p+4, &p, 0);
1202 else if(cistrncmp(p, "size=", 5) == 0)
1203 isa->size = strtoul(p+5, &p, 0);
1204 else if(cistrncmp(p, "freq=", 5) == 0)
1205 isa->freq = strtoul(p+5, &p, 0);
1216 if((m->cpuiddx & (Mce|Cpumsr)) != (Mce|Cpumsr))
1218 if((m->cpuiddx & Mca) == 0){
1221 iprint("MCA %8.8llux MCT %8.8llux\n", v, w);
1226 iprint("MCG CAP %.16llux STATUS %.16llux\n", v, w);
1232 rdmsr(0x401 + bank*4, &v);
1233 if((v & (1ull << 63)) == 0)
1235 iprint("MC%d STATUS %.16llux", bank, v);
1236 if(v & (1ull << 58)){
1237 rdmsr(0x402 + bank*4, &w);
1238 iprint(" ADDR %.16llux", w);
1240 if(v & (1ull << 59)){
1241 rdmsr(0x403 + bank*4, &w);
1242 iprint(" MISC %.16llux", w);