2 #include "../port/lib.h"
8 #include "../port/error.h"
10 typedef struct IOMap IOMap;
25 IOMap maps[32]; /* some initial free maps */
27 QLock ql; /* lock for reading map */
40 enum { /* cpuid standard function codes */
41 Highstdfunc = 0, /* also returns vendor string */
47 typedef long Rdwrfn(Chan*, void*, long, vlong);
49 static Rdwrfn *readfn[Qmax];
50 static Rdwrfn *writefn[Qmax];
52 static Dirtab archdir[Qmax] = {
53 ".", { Qdir, 0, QTDIR }, 0, 0555,
54 "ioalloc", { Qioalloc, 0 }, 0, 0444,
55 "iob", { Qiob, 0 }, 0, 0660,
56 "iow", { Qiow, 0 }, 0, 0660,
57 "iol", { Qiol, 0 }, 0, 0660,
59 Lock archwlock; /* the lock is only for changing archdir */
61 int (*_pcmspecial)(char*, ISAConf*);
62 void (*_pcmspecialclose)(int);
64 static int doi8253set = 1;
67 * Add a file to the #P listing. Once added, you can't delete it.
68 * You can't add a file with the same name as one already there,
69 * and you get a pointer to the Dirtab entry so you can do things
70 * like change the Qid version. Changing the Qid path is disallowed.
73 addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
79 memset(&d, 0, sizeof d);
89 for(i=0; i<narchdir; i++)
90 if(strcmp(archdir[i].name, name) == 0){
95 d.qid.path = narchdir;
96 archdir[narchdir] = d;
97 readfn[narchdir] = rdfn;
98 writefn[narchdir] = wrfn;
99 dp = &archdir[narchdir++];
111 for(i = 0; i < nelem(iomap.maps)-1; i++)
112 iomap.maps[i].next = &iomap.maps[i+1];
113 iomap.maps[i].next = nil;
114 iomap.free = iomap.maps;
117 * This is necessary to make the IBM X20 boot.
118 * Have not tracked down the reason.
119 * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
121 ioalloc(0x0fff, 1, 0, "dummy");
123 if ((excluded = getconf("ioexclude")) != nil) {
127 while (s && *s != '\0' && *s != '\n') {
131 io_s = (int)strtol(s, &ends, 0);
132 if (ends == nil || ends == s || *ends != '-') {
133 print("ioinit: cannot parse option string\n");
138 io_e = (int)strtol(s, &ends, 0);
139 if (ends && *ends == ',')
143 ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
150 * Reserve a range to be ioalloced later.
151 * This is in particular useful for exchangable cards, such
152 * as pcmcia and cardbus cards.
155 ioreserve(int, int size, int align, char *tag)
161 /* find a free port above 0x400 and below 0x1000 */
163 for(l = &iomap.m; *l; l = &(*l)->next){
165 if (m->start < 0x400) continue;
170 port = ((port+align-1)/align)*align;
180 print("ioalloc: out of maps");
184 iomap.free = m->next;
187 m->end = port + size;
189 strncpy(m->tag, tag, sizeof(m->tag));
190 m->tag[sizeof(m->tag)-1] = 0;
193 archdir[0].qid.vers++;
200 * alloc some io port space and remember who it was
201 * alloced to. if port < 0, find a free region.
204 ioalloc(int port, int size, int align, char *tag)
211 /* find a free port above 0x400 and below 0x1000 */
213 for(l = &iomap.m; *l; l = &(*l)->next){
215 if (m->start < 0x400) continue;
220 port = ((port+align-1)/align)*align;
229 /* Only 64KB I/O space on the x86. */
230 if((port+size) > 0x10000){
234 /* see if the space clashes with previously allocated ports */
235 for(l = &iomap.m; *l; l = &(*l)->next){
239 if(m->reserved && m->start == port && m->end == port + size) {
244 if(m->start >= port+size)
252 print("ioalloc: out of maps");
256 iomap.free = m->next;
259 m->end = port + size;
260 strncpy(m->tag, tag, sizeof(m->tag));
261 m->tag[sizeof(m->tag)-1] = 0;
264 archdir[0].qid.vers++;
276 for(l = &iomap.m; *l; l = &(*l)->next){
277 if((*l)->start == port){
280 m->next = iomap.free;
284 if((*l)->start > port)
287 archdir[0].qid.vers++;
292 iounused(int start, int end)
296 for(m = iomap.m; m; m = m->next){
297 if(start >= m->start && start < m->end
298 || start <= m->start && end > m->start)
305 checkport(int start, int end)
307 /* standard vga regs are OK */
308 if(start >= 0x2b0 && end <= 0x2df+1)
310 if(start >= 0x3c0 && end <= 0x3da+1)
313 if(iounused(start, end))
319 archattach(char* spec)
321 return devattach('P', spec);
325 archwalk(Chan* c, Chan *nc, char** name, int nname)
327 return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
331 archstat(Chan* c, uchar* dp, int n)
333 return devstat(c, dp, n, archdir, narchdir, devgen);
337 archopen(Chan* c, int omode)
339 return devopen(c, omode, archdir, narchdir, devgen);
353 archread(Chan *c, void *a, long n, vlong offset)
362 switch((ulong)c->qid.path){
365 return devdirread(c, a, n, archdir, narchdir, devgen);
369 checkport(offset, offset+n);
370 for(p = a; port < offset+n; port++)
377 checkport(offset, offset+n);
379 for(port = offset; port < offset+n; port += 2)
386 checkport(offset, offset+n);
388 for(port = offset; port < offset+n; port += 4)
396 if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
397 return fn(c, a, n, offset);
402 if((buf = malloc(n)) == nil)
406 offset = offset/Linelen;
409 for(m = iomap.m; n > 0 && m != nil; m = m->next){
412 sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
426 archwrite(Chan *c, void *a, long n, vlong offset)
434 switch((ulong)c->qid.path){
438 checkport(offset, offset+n);
439 for(port = offset; port < offset+n; port++)
446 checkport(offset, offset+n);
448 for(port = offset; port < offset+n; port += 2)
455 checkport(offset, offset+n);
457 for(port = offset; port < offset+n; port += 4)
462 if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
463 return fn(c, a, n, offset);
492 * the following is a generic version of the
493 * architecture specific stuff
513 * Often the BIOS hangs during restart if a conventional 8042
514 * warm-boot sequence is tried. The following is Intel specific and
515 * seems to perform a cold-boot, but at least it comes back.
516 * And sometimes there is no keyboard...
518 * The reset register (0xcf9) is usually in one of the bridge
519 * chips. The actual location and sequence could be extracted from
520 * ACPI but why bother, this is the end of the line anyway.
522 print("Takes a licking and keeps on ticking...\n");
523 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
532 * 386 has no compare-and-swap instruction.
533 * Run it with interrupts turned off instead.
536 cmpswap386(long *addr, long old, long new)
541 if(r = (*addr == old))
548 * On a uniprocessor, you'd think that coherence could be nop,
549 * but it can't. We still need a barrier when using coherence() in
552 * On VMware, it's safe (and a huge win) to set this to nop.
553 * Aux/vmware does this via the #P/archctl file.
555 void (*coherence)(void) = nop;
557 int (*cmpswap)(long*, long, long) = cmpswap386;
560 extern PCArch* knownarch[];
562 PCArch archgeneric = {
566 .serialpower= unimplemented,
567 .modempower= unimplemented,
569 .intrinit= i8259init,
570 .intrenable= i8259enable,
571 .intrvecno= i8259vecno,
572 .intrdisable= i8259disable,
576 .clockenable= i8253enable,
577 .fastclock= i8253read,
578 .timerset= i8253timerset,
581 typedef struct X86type X86type;
589 static X86type x86intel[] =
591 { 4, 0, 22, "486DX", }, /* known chips */
592 { 4, 1, 22, "486DX50", },
593 { 4, 2, 22, "486SX", },
594 { 4, 3, 22, "486DX2", },
595 { 4, 4, 22, "486SL", },
596 { 4, 5, 22, "486SX2", },
597 { 4, 7, 22, "DX2WB", }, /* P24D */
598 { 4, 8, 22, "DX4", }, /* P24C */
599 { 4, 9, 22, "DX4WB", }, /* P24CT */
602 { 5, 2, 23, "P54C", },
603 { 5, 3, 23, "P24T", },
604 { 5, 4, 23, "P55C MMX", },
605 { 5, 7, 23, "P54C VRT", },
606 { 6, 1, 16, "PentiumPro", },/* trial and error */
607 { 6, 3, 16, "PentiumII", },
608 { 6, 5, 16, "PentiumII/Xeon", },
609 { 6, 6, 16, "Celeron", },
610 { 6, 7, 16, "PentiumIII/Xeon", },
611 { 6, 8, 16, "PentiumIII/Xeon", },
612 { 6, 0xB, 16, "PentiumIII/Xeon", },
613 { 6, 0xF, 16, "Xeon5000-series", },
614 { 6, 0x16, 16, "Celeron", },
615 { 6, 0x17, 16, "Core 2/Xeon", },
616 { 6, 0x1A, 16, "Core i7/Xeon", },
617 { 6, 0x1C, 16, "Atom", },
618 { 6, 0x1D, 16, "Xeon MP", },
619 { 0xF, 1, 16, "P4", }, /* P4 */
620 { 0xF, 2, 16, "PentiumIV/Xeon", },
621 { 0xF, 6, 16, "PentiumIV/Xeon", },
623 { 3, -1, 32, "386", }, /* family defaults */
624 { 4, -1, 22, "486", },
625 { 5, -1, 23, "P5", },
626 { 6, -1, 16, "P6", },
627 { 0xF, -1, 16, "P4", }, /* P4 */
629 { -1, -1, 16, "unknown", }, /* total default */
633 * The AMD processors all implement the CPUID instruction.
634 * The later ones also return the processor name via functions
635 * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
637 * K5 "AMD-K5(tm) Processor"
638 * K6 "AMD-K6tm w/ multimedia extensions"
639 * K6 3D "AMD-K6(tm) 3D processor"
642 static X86type x86amd[] =
644 { 5, 0, 23, "AMD-K5", }, /* guesswork */
645 { 5, 1, 23, "AMD-K5", }, /* guesswork */
646 { 5, 2, 23, "AMD-K5", }, /* guesswork */
647 { 5, 3, 23, "AMD-K5", }, /* guesswork */
648 { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
649 { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
650 { 5, 6, 11, "AMD-K6", }, /* trial and error */
651 { 5, 7, 11, "AMD-K6", }, /* trial and error */
652 { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
653 { 5, 9, 11, "AMD-K6-III", },/* trial and error */
654 { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
656 { 6, 1, 11, "AMD-Athlon", },/* trial and error */
657 { 6, 2, 11, "AMD-Athlon", },/* trial and error */
659 { 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
661 { 4, -1, 22, "Am486", }, /* guesswork */
662 { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
663 { 6, -1, 11, "AMD-Athlon", },/* guesswork */
664 { 0xF, -1, 11, "AMD-K8", }, /* guesswork */
665 { 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
667 { -1, -1, 11, "unknown", }, /* total default */
673 static X86type x86winchip[] =
675 {5, 4, 23, "Winchip",}, /* guesswork */
676 {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
677 {6, 8, 23, "Via C3 Ezra-T",},
678 {6, 9, 23, "Via C3 Eden-N",},
679 { -1, -1, 23, "unknown", }, /* total default */
685 static X86type x86sis[] =
687 {5, 0, 23, "SiS 55x",}, /* guesswork */
688 { -1, -1, 23, "unknown", }, /* total default */
691 static X86type *cputype;
693 static void simplecycles(uvlong*);
694 void (*cycles)(uvlong*) = simplecycles;
695 void _cycles(uvlong*); /* in l.s */
698 simplecycles(uvlong*x)
709 i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
711 i += sprint(buf+i, "%12.12s ", m->cpuidid);
712 seprint(buf+i, buf + sizeof buf - 1,
713 "%s (cpuid: AX 0x%4.4uX DX 0x%4.4uX)\n",
714 m->cpuidtype, m->cpuidax, m->cpuiddx);
721 * - whether or not we have a TSC (cycle counter)
722 * - whether or not it supports page size extensions
724 * - whether or not it supports machine check exceptions
726 * - whether or not it supports the page global flag
733 int family, model, nomce;
739 cpuid(Highstdfunc, regs);
740 memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
741 memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
742 memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
743 m->cpuidid[12] = '\0';
745 cpuid(Procsig, regs);
746 m->cpuidax = regs[0];
747 m->cpuiddx = regs[3];
749 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
750 strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
752 else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
754 else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
759 family = X86FAMILY(m->cpuidax);
760 model = X86MODEL(m->cpuidax);
761 for(t=tab; t->name; t++)
762 if((t->family == family && t->model == model)
763 || (t->family == family && t->model == -1)
764 || (t->family == -1))
767 m->cpuidtype = t->name;
770 * if there is one, set tsc to a known value
772 if(m->cpuiddx & Tsc){
775 if(m->cpuiddx & Cpumsr)
780 * use i8253 to guess our cpu speed
782 guesscpuhz(t->aalcycles);
785 * If machine check exception, page size extensions or page global bit
786 * are supported enable them in CR4 and clear any other set extensions.
787 * If machine check was enabled clear out any lingering status.
789 if(m->cpuiddx & (Pge|Mce|0x8)){
791 if(m->cpuiddx & 0x08)
792 cr4 |= 0x10; /* page size extensions */
793 if(p = getconf("*nomce"))
794 nomce = strtoul(p, 0, 0);
797 if((m->cpuiddx & Mce) && !nomce){
798 cr4 |= 0x40; /* machine check enable */
806 * Detect whether the chip supports the global bit
807 * in page directory and page table entries. When set
808 * in a particular entry, it means ``don't bother removing
809 * this from the TLB when CR3 changes.''
811 * We flag all kernel pages with this bit. Doing so lessens the
812 * overhead of switching processes on bare hardware,
813 * even more so on VMware. See mmu.c:/^memglobal.
815 * For future reference, should we ever need to do a
816 * full TLB flush, it can be accomplished by clearing
817 * the PGE bit in CR4, writing to CR3, and then
818 * restoring the PGE bit.
820 if(m->cpuiddx & Pge){
821 cr4 |= 0x80; /* page global enable bit */
835 cputyperead(Chan*, void *a, long n, vlong offset)
840 mhz = (m->cpuhz+999999)/1000000;
842 snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
843 return readstr(offset, a, n, str);
847 archctlread(Chan*, void *a, long nn, vlong offset)
852 p = buf = malloc(READSTR);
854 p = seprint(p, ep, "cpu %s %lud%s\n",
855 cputype->name, (ulong)(m->cpuhz+999999)/1000000,
856 m->havepge ? " pge" : "");
857 p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
858 p = seprint(p, ep, "coherence ");
859 if(coherence == mb386)
860 p = seprint(p, ep, "mb386\n");
861 else if(coherence == mb586)
862 p = seprint(p, ep, "mb586\n");
863 else if(coherence == mfence)
864 p = seprint(p, ep, "mfence\n");
865 else if(coherence == nop)
866 p = seprint(p, ep, "nop\n");
868 p = seprint(p, ep, "0x%p\n", coherence);
869 p = seprint(p, ep, "cmpswap ");
870 if(cmpswap == cmpswap386)
871 p = seprint(p, ep, "cmpswap386\n");
872 else if(cmpswap == cmpswap486)
873 p = seprint(p, ep, "cmpswap486\n");
875 p = seprint(p, ep, "0x%p\n", cmpswap);
876 p = seprint(p, ep, "i8253set %s\n", doi8253set ? "on" : "off");
878 n += mtrrprint(p, ep - p);
881 n = readstr(offset, a, nn, buf);
894 static Cmdtab archctlmsg[] =
897 CMcoherence, "coherence", 2,
898 CMi8253set, "i8253set", 2,
903 archctlwrite(Chan*, void *a, long n, vlong)
915 ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
919 error("processor does not support pge");
920 if(strcmp(cb->f[1], "on") == 0)
921 putcr4(getcr4() | 0x80);
922 else if(strcmp(cb->f[1], "off") == 0)
923 putcr4(getcr4() & ~0x80);
925 cmderror(cb, "invalid pge ctl");
928 if(strcmp(cb->f[1], "mb386") == 0)
930 else if(strcmp(cb->f[1], "mb586") == 0){
931 if(X86FAMILY(m->cpuidax) < 5)
932 error("invalid coherence ctl on this cpu family");
934 }else if(strcmp(cb->f[1], "mfence") == 0){
935 if((m->cpuiddx & Sse2) == 0)
936 error("invalid coherence ctl on this cpu family");
938 }else if(strcmp(cb->f[1], "nop") == 0){
939 /* only safe on vmware */
941 error("cannot disable coherence on a multiprocessor");
944 cmderror(cb, "invalid coherence ctl");
947 if(strcmp(cb->f[1], "on") == 0)
949 else if(strcmp(cb->f[1], "off") == 0){
951 (*arch->timerset)(0);
953 cmderror(cb, "invalid i2853set ctl");
956 base = strtoull(cb->f[1], &ep, 0);
958 error("cache: parse error: base not a number?");
959 size = strtoull(cb->f[2], &ep, 0);
961 error("cache: parse error: size not a number?");
962 mtrr(base, size, cb->f[3]);
976 for(p = knownarch; *p; p++){
977 if((*p)->ident && (*p)->ident() == 0){
986 arch->id = archgeneric.id;
988 arch->reset = archgeneric.reset;
989 if(arch->serialpower == 0)
990 arch->serialpower = archgeneric.serialpower;
991 if(arch->modempower == 0)
992 arch->modempower = archgeneric.modempower;
993 if(arch->intrinit == 0)
994 arch->intrinit = archgeneric.intrinit;
995 if(arch->intrenable == 0)
996 arch->intrenable = archgeneric.intrenable;
1000 * Decide whether to use copy-on-reference (386 and mp).
1001 * We get another chance to set it in mpinit() for a
1004 if(X86FAMILY(m->cpuidax) == 3)
1007 if(X86FAMILY(m->cpuidax) >= 4)
1008 cmpswap = cmpswap486;
1010 if(X86FAMILY(m->cpuidax) >= 5)
1013 if(m->cpuiddx & Sse2)
1016 addarchfile("cputype", 0444, cputyperead, nil);
1017 addarchfile("archctl", 0664, archctlread, archctlwrite);
1021 * call either the pcmcia or pccard device setup
1024 pcmspecial(char *idstr, ISAConf *isa)
1026 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
1030 * call either the pcmcia or pccard device teardown
1033 pcmspecialclose(int a)
1035 if (_pcmspecialclose != nil)
1036 _pcmspecialclose(a);
1040 * return value and speed of timer set in arch->clockenable
1043 fastticks(uvlong *hz)
1045 return (*arch->fastclock)(hz);
1051 return fastticks2us((*arch->fastclock)(nil));
1055 * set next timer interrupt
1061 (*arch->timerset)(x);