2 #include "../port/lib.h"
8 #include "../port/error.h"
10 typedef struct IOMap IOMap;
25 IOMap maps[32]; /* some initial free maps */
27 QLock ql; /* lock for reading map */
47 enum { /* cpuid standard function codes */
48 Highstdfunc = 0, /* also returns vendor string */
54 typedef long Rdwrfn(Chan*, void*, long, vlong);
56 static Rdwrfn *readfn[Qmax];
57 static Rdwrfn *writefn[Qmax];
59 static Dirtab archdir[Qmax] = {
60 ".", { Qdir, 0, QTDIR }, 0, 0555,
61 "ioalloc", { Qioalloc, 0 }, 0, 0444,
62 "iob", { Qiob, 0 }, 0, 0660,
63 "iow", { Qiow, 0 }, 0, 0660,
64 "iol", { Qiol, 0 }, 0, 0660,
65 "msr", { Qmsr, 0}, 0, 0660,
67 Lock archwlock; /* the lock is only for changing archdir */
69 int (*_pcmspecial)(char*, ISAConf*);
70 void (*_pcmspecialclose)(int);
72 static int doi8253set = 1;
75 * Add a file to the #P listing. Once added, you can't delete it.
76 * You can't add a file with the same name as one already there,
77 * and you get a pointer to the Dirtab entry so you can do things
78 * like change the Qid version. Changing the Qid path is disallowed.
81 addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
87 memset(&d, 0, sizeof d);
97 for(i=0; i<narchdir; i++)
98 if(strcmp(archdir[i].name, name) == 0){
103 d.qid.path = narchdir;
104 archdir[narchdir] = d;
105 readfn[narchdir] = rdfn;
106 writefn[narchdir] = wrfn;
107 dp = &archdir[narchdir++];
119 for(i = 0; i < nelem(iomap.maps)-1; i++)
120 iomap.maps[i].next = &iomap.maps[i+1];
121 iomap.maps[i].next = nil;
122 iomap.free = iomap.maps;
125 * This is necessary to make the IBM X20 boot.
126 * Have not tracked down the reason.
127 * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
129 ioalloc(0x0fff, 1, 0, "dummy");
131 if ((excluded = getconf("ioexclude")) != nil) {
135 while (s && *s != '\0' && *s != '\n') {
139 io_s = (int)strtol(s, &ends, 0);
140 if (ends == nil || ends == s || *ends != '-') {
141 print("ioinit: cannot parse option string\n");
146 io_e = (int)strtol(s, &ends, 0);
147 if (ends && *ends == ',')
151 ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
158 * Reserve a range to be ioalloced later.
159 * This is in particular useful for exchangable cards, such
160 * as pcmcia and cardbus cards.
163 ioreserve(int, int size, int align, char *tag)
169 /* find a free port above 0x400 and below 0x1000 */
171 for(l = &iomap.m; *l; l = &(*l)->next){
173 if (m->start < 0x400) continue;
178 port = ((port+align-1)/align)*align;
188 print("ioalloc: out of maps");
192 iomap.free = m->next;
195 m->end = port + size;
197 strncpy(m->tag, tag, sizeof(m->tag)-1);
198 m->tag[sizeof(m->tag)-1] = 0;
201 archdir[0].qid.vers++;
208 * alloc some io port space and remember who it was
209 * alloced to. if port < 0, find a free region.
212 ioalloc(int port, int size, int align, char *tag)
219 /* find a free port above 0x400 and below 0x1000 */
221 for(l = &iomap.m; *l; l = &(*l)->next){
223 if (m->start < 0x400) continue;
228 port = ((port+align-1)/align)*align;
237 /* Only 64KB I/O space on the x86. */
238 if((port+size) > 0x10000){
242 /* see if the space clashes with previously allocated ports */
243 for(l = &iomap.m; *l; l = &(*l)->next){
247 if(m->reserved && m->start == port && m->end >= port + size) {
252 if(m->start >= port+size)
260 print("ioalloc: out of maps");
264 iomap.free = m->next;
267 m->end = port + size;
268 strncpy(m->tag, tag, sizeof(m->tag)-1);
269 m->tag[sizeof(m->tag)-1] = 0;
272 archdir[0].qid.vers++;
284 for(l = &iomap.m; *l; l = &(*l)->next){
285 if((*l)->start == port){
288 m->next = iomap.free;
292 if((*l)->start > port)
295 archdir[0].qid.vers++;
300 iounused(int start, int end)
304 for(m = iomap.m; m; m = m->next){
305 if(start >= m->start && start < m->end
306 || start <= m->start && end > m->start)
313 checkport(int start, int end)
315 /* standard vga regs are OK */
316 if(start >= 0x2b0 && end <= 0x2df+1)
318 if(start >= 0x3c0 && end <= 0x3da+1)
321 if(iounused(start, end))
327 archattach(char* spec)
329 return devattach('P', spec);
333 archwalk(Chan* c, Chan *nc, char** name, int nname)
335 return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
339 archstat(Chan* c, uchar* dp, int n)
341 return devstat(c, dp, n, archdir, narchdir, devgen);
345 archopen(Chan* c, int omode)
347 return devopen(c, omode, archdir, narchdir, devgen);
361 archread(Chan *c, void *a, long n, vlong offset)
371 switch((ulong)c->qid.path){
374 return devdirread(c, a, n, archdir, narchdir, devgen);
378 checkport(offset, offset+n);
379 for(p = a; port < offset+n; port++)
386 checkport(offset, offset+n);
388 for(port = offset; port < offset+n; port += 2)
395 checkport(offset, offset+n);
397 for(port = offset; port < offset+n; port += 4)
405 for(port = offset; port < offset+n; port += 8)
406 if(rdmsr(port, vp++) < 0)
414 if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
415 return fn(c, a, n, offset);
420 if((buf = malloc(n)) == nil)
424 offset = offset/Linelen;
427 for(m = iomap.m; n > 0 && m != nil; m = m->next){
430 sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
444 archwrite(Chan *c, void *a, long n, vlong offset)
453 switch((ulong)c->qid.path){
457 checkport(offset, offset+n);
458 for(port = offset; port < offset+n; port++)
465 checkport(offset, offset+n);
467 for(port = offset; port < offset+n; port += 2)
474 checkport(offset, offset+n);
476 for(port = offset; port < offset+n; port += 4)
484 for(port = offset; port < offset+n; port += 8)
485 if(wrmsr(port, *vp++) < 0)
490 if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
491 return fn(c, a, n, offset);
520 * the following is a generic version of the
521 * architecture specific stuff
541 * Often the BIOS hangs during restart if a conventional 8042
542 * warm-boot sequence is tried. The following is Intel specific and
543 * seems to perform a cold-boot, but at least it comes back.
544 * And sometimes there is no keyboard...
546 * The reset register (0xcf9) is usually in one of the bridge
547 * chips. The actual location and sequence could be extracted from
548 * ACPI but why bother, this is the end of the line anyway.
550 print("Takes a licking and keeps on ticking...\n");
551 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
560 * 386 has no compare-and-swap instruction.
561 * Run it with interrupts turned off instead.
564 cmpswap386(long *addr, long old, long new)
569 if(r = (*addr == old))
576 * On a uniprocessor, you'd think that coherence could be nop,
577 * but it can't. We still need a barrier when using coherence() in
580 * On VMware, it's safe (and a huge win) to set this to nop.
581 * Aux/vmware does this via the #P/archctl file.
583 void (*coherence)(void) = nop;
585 int (*cmpswap)(long*, long, long) = cmpswap386;
588 extern PCArch* knownarch[];
590 PCArch archgeneric = {
594 .serialpower= unimplemented,
595 .modempower= unimplemented,
597 .intrinit= i8259init,
598 .intrenable= i8259enable,
599 .intrvecno= i8259vecno,
600 .intrdisable= i8259disable,
604 .clockenable= i8253enable,
605 .fastclock= i8253read,
606 .timerset= i8253timerset,
609 typedef struct X86type X86type;
617 static X86type x86intel[] =
619 { 4, 0, 22, "486DX", }, /* known chips */
620 { 4, 1, 22, "486DX50", },
621 { 4, 2, 22, "486SX", },
622 { 4, 3, 22, "486DX2", },
623 { 4, 4, 22, "486SL", },
624 { 4, 5, 22, "486SX2", },
625 { 4, 7, 22, "DX2WB", }, /* P24D */
626 { 4, 8, 22, "DX4", }, /* P24C */
627 { 4, 9, 22, "DX4WB", }, /* P24CT */
630 { 5, 2, 23, "P54C", },
631 { 5, 3, 23, "P24T", },
632 { 5, 4, 23, "P55C MMX", },
633 { 5, 7, 23, "P54C VRT", },
634 { 6, 1, 16, "PentiumPro", },/* trial and error */
635 { 6, 3, 16, "PentiumII", },
636 { 6, 5, 16, "PentiumII/Xeon", },
637 { 6, 6, 16, "Celeron", },
638 { 6, 7, 16, "PentiumIII/Xeon", },
639 { 6, 8, 16, "PentiumIII/Xeon", },
640 { 6, 0xB, 16, "PentiumIII/Xeon", },
641 { 6, 0xF, 16, "Xeon5000-series", },
642 { 6, 0x16, 16, "Celeron", },
643 { 6, 0x17, 16, "Core 2/Xeon", },
644 { 6, 0x1A, 16, "Core i7/Xeon", },
645 { 6, 0x1C, 16, "Atom", },
646 { 6, 0x1D, 16, "Xeon MP", },
647 { 0xF, 1, 16, "P4", }, /* P4 */
648 { 0xF, 2, 16, "PentiumIV/Xeon", },
649 { 0xF, 6, 16, "PentiumIV/Xeon", },
651 { 3, -1, 32, "386", }, /* family defaults */
652 { 4, -1, 22, "486", },
653 { 5, -1, 23, "P5", },
654 { 6, -1, 16, "P6", },
655 { 0xF, -1, 16, "P4", }, /* P4 */
657 { -1, -1, 16, "unknown", }, /* total default */
661 * The AMD processors all implement the CPUID instruction.
662 * The later ones also return the processor name via functions
663 * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
665 * K5 "AMD-K5(tm) Processor"
666 * K6 "AMD-K6tm w/ multimedia extensions"
667 * K6 3D "AMD-K6(tm) 3D processor"
670 static X86type x86amd[] =
672 { 5, 0, 23, "AMD-K5", }, /* guesswork */
673 { 5, 1, 23, "AMD-K5", }, /* guesswork */
674 { 5, 2, 23, "AMD-K5", }, /* guesswork */
675 { 5, 3, 23, "AMD-K5", }, /* guesswork */
676 { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
677 { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
678 { 5, 6, 11, "AMD-K6", }, /* trial and error */
679 { 5, 7, 11, "AMD-K6", }, /* trial and error */
680 { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
681 { 5, 9, 11, "AMD-K6-III", },/* trial and error */
682 { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
684 { 6, 1, 11, "AMD-Athlon", },/* trial and error */
685 { 6, 2, 11, "AMD-Athlon", },/* trial and error */
687 { 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
689 { 4, -1, 22, "Am486", }, /* guesswork */
690 { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
691 { 6, -1, 11, "AMD-Athlon", },/* guesswork */
692 { 0xF, -1, 11, "AMD-K8", }, /* guesswork */
693 { 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
695 { -1, -1, 11, "unknown", }, /* total default */
701 static X86type x86winchip[] =
703 {5, 4, 23, "Winchip",}, /* guesswork */
704 {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
705 {6, 8, 23, "Via C3 Ezra-T",},
706 {6, 9, 23, "Via C3 Eden-N",},
707 { -1, -1, 23, "unknown", }, /* total default */
713 static X86type x86sis[] =
715 {5, 0, 23, "SiS 55x",}, /* guesswork */
716 { -1, -1, 23, "unknown", }, /* total default */
719 static X86type *cputype;
721 static void simplecycles(uvlong*);
722 void (*cycles)(uvlong*) = simplecycles;
723 void _cycles(uvlong*); /* in l.s */
726 simplecycles(uvlong*x)
737 i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
739 i += sprint(buf+i, "%12.12s ", m->cpuidid);
740 seprint(buf+i, buf + sizeof buf - 1,
741 "%s (cpuid: AX 0x%4.4uX CX 0x%4.4uX DX 0x%4.4uX)\n",
742 m->cpuidtype, m->cpuidax, m->cpuidcx, m->cpuiddx);
749 * - whether or not we have a TSC (cycle counter)
750 * - whether or not it supports page size extensions
752 * - whether or not it supports machine check exceptions
754 * - whether or not it supports the page global flag
761 int family, model, nomce;
767 cpuid(Highstdfunc, regs);
768 memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
769 memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
770 memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
771 m->cpuidid[12] = '\0';
773 cpuid(Procsig, regs);
774 m->cpuidax = regs[0];
775 m->cpuidcx = regs[2];
776 m->cpuiddx = regs[3];
778 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
779 strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
781 else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
783 else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
788 family = X86FAMILY(m->cpuidax);
789 model = X86MODEL(m->cpuidax);
790 for(t=tab; t->name; t++)
791 if((t->family == family && t->model == model)
792 || (t->family == family && t->model == -1)
793 || (t->family == -1))
796 m->cpuidtype = t->name;
799 * if there is one, set tsc to a known value
801 if(m->cpuiddx & Tsc){
804 if(m->cpuiddx & Cpumsr)
810 * use i8253 to guess our cpu speed
812 guesscpuhz(t->aalcycles);
815 * If machine check exception, page size extensions or page global bit
816 * are supported enable them in CR4 and clear any other set extensions.
817 * If machine check was enabled clear out any lingering status.
819 if(m->cpuiddx & (Pge|Mce|Pse)){
822 cr4 |= 0x10; /* page size extensions */
823 if(p = getconf("*nomce"))
824 nomce = strtoul(p, 0, 0);
827 if((m->cpuiddx & Mce) != 0 && !nomce){
828 if((m->cpuiddx & Mca) != 0){
836 wrmsr(0x17B, ~0ULL); /* enable all mca features */
842 /* init MCi .. MC1 (except MC0) */
844 wrmsr(0x400 + bank*4, ~0ULL);
845 wrmsr(0x401 + bank*4, 0);
848 if(family != 6 || model >= 0x1A)
853 else if(family == 5){
857 cr4 |= 0x40; /* machine check enable */
861 * Detect whether the chip supports the global bit
862 * in page directory and page table entries. When set
863 * in a particular entry, it means ``don't bother removing
864 * this from the TLB when CR3 changes.''
866 * We flag all kernel pages with this bit. Doing so lessens the
867 * overhead of switching processes on bare hardware,
868 * even more so on VMware. See mmu.c:/^memglobal.
870 * For future reference, should we ever need to do a
871 * full TLB flush, it can be accomplished by clearing
872 * the PGE bit in CR4, writing to CR3, and then
873 * restoring the PGE bit.
875 if(m->cpuiddx & Pge){
876 cr4 |= 0x80; /* page global enable bit */
882 if((m->cpuiddx & (Mca|Mce)) == Mce)
886 if(m->cpuiddx & Fxsr){ /* have sse fp? */
888 fprestore = fpsserestore;
889 putcr4(getcr4() | CR4Osfxsr|CR4Oxmmex);
892 fprestore = fpx87restore;
900 cputyperead(Chan*, void *a, long n, vlong offset)
905 mhz = (m->cpuhz+999999)/1000000;
907 snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
908 return readstr(offset, a, n, str);
912 archctlread(Chan*, void *a, long nn, vlong offset)
917 p = buf = smalloc(READSTR);
919 p = seprint(p, ep, "cpu %s %lud%s\n",
920 cputype->name, (ulong)(m->cpuhz+999999)/1000000,
921 m->havepge ? " pge" : "");
922 p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
923 p = seprint(p, ep, "coherence ");
924 if(coherence == mb386)
925 p = seprint(p, ep, "mb386\n");
926 else if(coherence == mb586)
927 p = seprint(p, ep, "mb586\n");
928 else if(coherence == mfence)
929 p = seprint(p, ep, "mfence\n");
930 else if(coherence == nop)
931 p = seprint(p, ep, "nop\n");
933 p = seprint(p, ep, "0x%p\n", coherence);
934 p = seprint(p, ep, "cmpswap ");
935 if(cmpswap == cmpswap386)
936 p = seprint(p, ep, "cmpswap386\n");
937 else if(cmpswap == cmpswap486)
938 p = seprint(p, ep, "cmpswap486\n");
940 p = seprint(p, ep, "0x%p\n", cmpswap);
941 p = seprint(p, ep, "i8253set %s\n", doi8253set ? "on" : "off");
943 n += mtrrprint(p, ep - p);
946 n = readstr(offset, a, nn, buf);
959 static Cmdtab archctlmsg[] =
962 CMcoherence, "coherence", 2,
963 CMi8253set, "i8253set", 2,
968 archctlwrite(Chan*, void *a, long n, vlong)
980 ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
984 error("processor does not support pge");
985 if(strcmp(cb->f[1], "on") == 0)
986 putcr4(getcr4() | 0x80);
987 else if(strcmp(cb->f[1], "off") == 0)
988 putcr4(getcr4() & ~0x80);
990 cmderror(cb, "invalid pge ctl");
993 if(strcmp(cb->f[1], "mb386") == 0)
995 else if(strcmp(cb->f[1], "mb586") == 0){
996 if(X86FAMILY(m->cpuidax) < 5)
997 error("invalid coherence ctl on this cpu family");
999 }else if(strcmp(cb->f[1], "mfence") == 0){
1000 if((m->cpuiddx & Sse2) == 0)
1001 error("invalid coherence ctl on this cpu family");
1003 }else if(strcmp(cb->f[1], "nop") == 0){
1004 /* only safe on vmware */
1006 error("cannot disable coherence on a multiprocessor");
1009 cmderror(cb, "invalid coherence ctl");
1012 if(strcmp(cb->f[1], "on") == 0)
1014 else if(strcmp(cb->f[1], "off") == 0){
1016 (*arch->timerset)(0);
1018 cmderror(cb, "invalid i2853set ctl");
1021 base = strtoull(cb->f[1], &ep, 0);
1023 error("cache: parse error: base not a number?");
1024 size = strtoull(cb->f[2], &ep, 0);
1026 error("cache: parse error: size not a number?");
1027 mtrr(base, size, cb->f[3]);
1036 rmemrw(int isr, void *a, long n, vlong off)
1040 if(off < 0 || n < 0)
1041 error("bad offset/count");
1047 memmove(a, KADDR(addr), n);
1049 /* allow vga framebuf's write access */
1050 if(addr >= MB || addr+n > MB ||
1051 (addr < 0xA0000 || addr+n > 0xB0000+0x10000))
1052 error("bad offset/count in write");
1053 memmove(KADDR(addr), a, n);
1059 rmemread(Chan*, void *a, long n, vlong off)
1061 return rmemrw(1, a, n, off);
1065 rmemwrite(Chan*, void *a, long n, vlong off)
1067 return rmemrw(0, a, n, off);
1076 for(p = knownarch; *p; p++){
1077 if((*p)->ident && (*p)->ident() == 0){
1083 arch = &archgeneric;
1086 arch->id = archgeneric.id;
1087 if(arch->reset == 0)
1088 arch->reset = archgeneric.reset;
1089 if(arch->serialpower == 0)
1090 arch->serialpower = archgeneric.serialpower;
1091 if(arch->modempower == 0)
1092 arch->modempower = archgeneric.modempower;
1093 if(arch->intrinit == 0)
1094 arch->intrinit = archgeneric.intrinit;
1095 if(arch->intrenable == 0)
1096 arch->intrenable = archgeneric.intrenable;
1100 * Decide whether to use copy-on-reference (386 and mp).
1101 * We get another chance to set it in mpinit() for a
1104 if(X86FAMILY(m->cpuidax) == 3)
1107 if(X86FAMILY(m->cpuidax) >= 4)
1108 cmpswap = cmpswap486;
1110 if(X86FAMILY(m->cpuidax) >= 5)
1113 if(m->cpuiddx & Sse2)
1116 addarchfile("cputype", 0444, cputyperead, nil);
1117 addarchfile("archctl", 0664, archctlread, archctlwrite);
1118 addarchfile("realmodemem", 0660, rmemread, rmemwrite);
1122 * call either the pcmcia or pccard device setup
1125 pcmspecial(char *idstr, ISAConf *isa)
1127 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
1131 * call either the pcmcia or pccard device teardown
1134 pcmspecialclose(int a)
1136 if (_pcmspecialclose != nil)
1137 _pcmspecialclose(a);
1141 * return value and speed of timer set in arch->clockenable
1144 fastticks(uvlong *hz)
1146 return (*arch->fastclock)(hz);
1152 return fastticks2us((*arch->fastclock)(nil));
1156 * set next timer interrupt
1162 (*arch->timerset)(x);
1166 * put the processor in the halt state if we've no processes to run.
1167 * an interrupt will get us going again.
1169 * halting in an smp system can result in a startup latency for
1170 * processes that become ready.
1171 * if idle_spin is zero, we care more about saving energy
1172 * than reducing this latency.
1174 * the performance loss with idle_spin == 0 seems to be slight
1175 * and it reduces lock contention (thus system time and real time)
1176 * on many-core systems with large values of NPROC.
1181 extern int nrdy, idle_spin;
1185 else if(m->cpuidcx & Monitor)
1187 else if(idle_spin == 0)
1192 isaconfig(char *class, int ctlrno, ISAConf *isa)
1197 snprint(cc, sizeof cc, "%s%d", class, ctlrno);
1203 isa->nopt = tokenize(p, isa->opt, NISAOPT);
1204 for(i = 0; i < isa->nopt; i++){
1206 if(cistrncmp(p, "type=", 5) == 0)
1208 else if(cistrncmp(p, "port=", 5) == 0)
1209 isa->port = strtoul(p+5, &p, 0);
1210 else if(cistrncmp(p, "irq=", 4) == 0)
1211 isa->irq = strtoul(p+4, &p, 0);
1212 else if(cistrncmp(p, "dma=", 4) == 0)
1213 isa->dma = strtoul(p+4, &p, 0);
1214 else if(cistrncmp(p, "mem=", 4) == 0)
1215 isa->mem = strtoul(p+4, &p, 0);
1216 else if(cistrncmp(p, "size=", 5) == 0)
1217 isa->size = strtoul(p+5, &p, 0);
1218 else if(cistrncmp(p, "freq=", 5) == 0)
1219 isa->freq = strtoul(p+5, &p, 0);
1230 if((m->cpuiddx & (Mce|Cpumsr)) != (Mce|Cpumsr))
1232 if((m->cpuiddx & Mca) == 0){
1235 iprint("MCA %8.8llux MCT %8.8llux\n", v, w);
1240 iprint("MCG CAP %.16llux STATUS %.16llux\n", v, w);
1246 rdmsr(0x401 + bank*4, &v);
1247 if((v & (1ull << 63)) == 0)
1249 iprint("MC%d STATUS %.16llux", bank, v);
1250 if(v & (1ull << 58)){
1251 rdmsr(0x402 + bank*4, &w);
1252 iprint(" ADDR %.16llux", w);
1254 if(v & (1ull << 59)){
1255 rdmsr(0x403 + bank*4, &w);
1256 iprint(" MISC %.16llux", w);