2 #include "../port/lib.h"
8 #include "../port/error.h"
10 typedef struct IOMap IOMap;
25 IOMap maps[32]; /* some initial free maps */
27 QLock ql; /* lock for reading map */
47 enum { /* cpuid standard function codes */
48 Highstdfunc = 0, /* also returns vendor string */
54 typedef long Rdwrfn(Chan*, void*, long, vlong);
56 static Rdwrfn *readfn[Qmax];
57 static Rdwrfn *writefn[Qmax];
59 static Dirtab archdir[Qmax] = {
60 ".", { Qdir, 0, QTDIR }, 0, 0555,
61 "ioalloc", { Qioalloc, 0 }, 0, 0444,
62 "iob", { Qiob, 0 }, 0, 0660,
63 "iow", { Qiow, 0 }, 0, 0660,
64 "iol", { Qiol, 0 }, 0, 0660,
65 "msr", { Qmsr, 0 }, 0, 0660,
67 Lock archwlock; /* the lock is only for changing archdir */
69 int (*_pcmspecial)(char*, ISAConf*);
70 void (*_pcmspecialclose)(int);
73 * Add a file to the #P listing. Once added, you can't delete it.
74 * You can't add a file with the same name as one already there,
75 * and you get a pointer to the Dirtab entry so you can do things
76 * like change the Qid version. Changing the Qid path is disallowed.
79 addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
85 memset(&d, 0, sizeof d);
92 print("addarchfile: out of entries for %s\n", name);
96 for(i=0; i<narchdir; i++)
97 if(strcmp(archdir[i].name, name) == 0){
102 d.qid.path = narchdir;
103 archdir[narchdir] = d;
104 readfn[narchdir] = rdfn;
105 writefn[narchdir] = wrfn;
106 dp = &archdir[narchdir++];
118 for(i = 0; i < nelem(iomap.maps)-1; i++)
119 iomap.maps[i].next = &iomap.maps[i+1];
120 iomap.maps[i].next = nil;
121 iomap.free = iomap.maps;
124 * This is necessary to make the IBM X20 boot.
125 * Have not tracked down the reason.
126 * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
128 ioalloc(0x0fff, 1, 0, "dummy");
130 if ((excluded = getconf("ioexclude")) != nil) {
134 while (s && *s != '\0' && *s != '\n') {
138 io_s = (int)strtol(s, &ends, 0);
139 if (ends == nil || ends == s || *ends != '-') {
140 print("ioinit: cannot parse option string\n");
145 io_e = (int)strtol(s, &ends, 0);
146 if (ends && *ends == ',')
150 ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
157 * Reserve a range to be ioalloced later.
158 * This is in particular useful for exchangable cards, such
159 * as pcmcia and cardbus cards.
162 ioreserve(int, int size, int align, char *tag)
168 /* find a free port above 0x400 and below 0x1000 */
170 for(l = &iomap.m; *l; l = &(*l)->next){
172 if (m->start < 0x400) continue;
177 port = ((port+align-1)/align)*align;
187 print("ioalloc: out of maps");
191 iomap.free = m->next;
194 m->end = port + size;
196 strncpy(m->tag, tag, sizeof(m->tag)-1);
197 m->tag[sizeof(m->tag)-1] = 0;
200 archdir[0].qid.vers++;
207 * alloc some io port space and remember who it was
208 * alloced to. if port < 0, find a free region.
211 ioalloc(int port, int size, int align, char *tag)
218 /* find a free port above 0x400 and below 0x1000 */
220 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
221 if (m->start < 0x400) continue;
226 port = ((port+align-1)/align)*align;
235 /* Only 64KB I/O space on the x86. */
236 if((port+size) > 0x10000){
240 /* see if the space clashes with previously allocated ports */
241 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
244 if(m->reserved && m->start == port && m->end >= port + size) {
249 if(m->start >= port+size)
257 print("ioalloc: out of maps");
261 iomap.free = m->next;
264 m->end = port + size;
265 strncpy(m->tag, tag, sizeof(m->tag)-1);
266 m->tag[sizeof(m->tag)-1] = 0;
269 archdir[0].qid.vers++;
281 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
282 if(m->start == port){
284 m->next = iomap.free;
291 archdir[0].qid.vers++;
296 iounused(int start, int end)
300 for(m = iomap.m; m != nil; m = m->next){
301 if(start >= m->start && start < m->end
302 || start <= m->start && end > m->start)
309 checkport(int start, int end)
311 /* standard vga regs are OK */
312 if(start >= 0x2b0 && end <= 0x2df+1)
314 if(start >= 0x3c0 && end <= 0x3da+1)
317 if(iounused(start, end))
323 archattach(char* spec)
325 return devattach('P', spec);
329 archwalk(Chan* c, Chan *nc, char** name, int nname)
331 return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
335 archstat(Chan* c, uchar* dp, int n)
337 return devstat(c, dp, n, archdir, narchdir, devgen);
341 archopen(Chan* c, int omode)
343 return devopen(c, omode, archdir, narchdir, devgen);
352 archread(Chan *c, void *a, long n, vlong offset)
362 switch((ulong)c->qid.path){
364 return devdirread(c, a, n, archdir, narchdir, devgen);
368 checkport(offset, offset+n);
369 for(p = a; port < offset+n; port++)
376 checkport(offset, offset+n);
378 for(port = offset; port < offset+n; port += 2)
385 checkport(offset, offset+n);
387 for(port = offset; port < offset+n; port += 4)
395 for(port = offset; port < offset+n; port += 8)
396 if(rdmsr(port, vp++) < 0)
403 for(m = iomap.m; m != nil; m = m->next){
404 i = snprint(buf, sizeof(buf), "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
415 memmove(a, buf+offset, n);
419 if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
420 return fn(c, a, n, offset);
427 archwrite(Chan *c, void *a, long n, vlong offset)
436 switch((ulong)c->qid.path){
439 checkport(offset, offset+n);
440 for(port = offset; port < offset+n; port++)
447 checkport(offset, offset+n);
449 for(port = offset; port < offset+n; port += 2)
456 checkport(offset, offset+n);
458 for(port = offset; port < offset+n; port += 4)
466 for(port = offset; port < offset+n; port += 8)
467 if(wrmsr(port, *vp++) < 0)
472 if(c->qid.path < narchdir && (fn = writefn[c->qid.path]) != nil)
473 return fn(c, a, n, offset);
502 * the following is a generic version of the
503 * architecture specific stuff
523 * Often the BIOS hangs during restart if a conventional 8042
524 * warm-boot sequence is tried. The following is Intel specific and
525 * seems to perform a cold-boot, but at least it comes back.
526 * And sometimes there is no keyboard...
528 * The reset register (0xcf9) is usually in one of the bridge
529 * chips. The actual location and sequence could be extracted from
530 * ACPI but why bother, this is the end of the line anyway.
532 print("Takes a licking and keeps on ticking...\n");
533 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
537 print("can't reset\n");
543 * 386 has no compare-and-swap instruction.
544 * Run it with interrupts turned off instead.
547 cmpswap386(long *addr, long old, long new)
552 if(r = (*addr == old))
559 * On a uniprocessor, you'd think that coherence could be nop,
560 * but it can't. We still need a barrier when using coherence() in
563 * On VMware, it's safe (and a huge win) to set this to nop.
564 * Aux/vmware does this via the #P/archctl file.
566 void (*coherence)(void) = nop;
568 int (*cmpswap)(long*, long, long) = cmpswap386;
571 extern PCArch* knownarch[];
573 PCArch archgeneric = {
577 .serialpower= unimplemented,
578 .modempower= unimplemented,
580 .intrinit= i8259init,
581 .intrenable= i8259enable,
582 .intrvecno= i8259vecno,
583 .intrdisable= i8259disable,
587 .clockenable= i8253enable,
588 .fastclock= i8253read,
589 .timerset= i8253timerset,
592 typedef struct X86type X86type;
600 static X86type x86intel[] =
602 { 4, 0, 22, "486DX", }, /* known chips */
603 { 4, 1, 22, "486DX50", },
604 { 4, 2, 22, "486SX", },
605 { 4, 3, 22, "486DX2", },
606 { 4, 4, 22, "486SL", },
607 { 4, 5, 22, "486SX2", },
608 { 4, 7, 22, "DX2WB", }, /* P24D */
609 { 4, 8, 22, "DX4", }, /* P24C */
610 { 4, 9, 22, "DX4WB", }, /* P24CT */
613 { 5, 2, 23, "P54C", },
614 { 5, 3, 23, "P24T", },
615 { 5, 4, 23, "P55C MMX", },
616 { 5, 7, 23, "P54C VRT", },
617 { 6, 1, 16, "PentiumPro", },/* trial and error */
618 { 6, 3, 16, "PentiumII", },
619 { 6, 5, 16, "PentiumII/Xeon", },
620 { 6, 6, 16, "Celeron", },
621 { 6, 7, 16, "PentiumIII/Xeon", },
622 { 6, 8, 16, "PentiumIII/Xeon", },
623 { 6, 0xB, 16, "PentiumIII/Xeon", },
624 { 6, 0xF, 16, "Xeon5000-series", },
625 { 6, 0x16, 16, "Celeron", },
626 { 6, 0x17, 16, "Core 2/Xeon", },
627 { 6, 0x1A, 16, "Core i7/Xeon", },
628 { 6, 0x1C, 16, "Atom", },
629 { 6, 0x1D, 16, "Xeon MP", },
630 { 0xF, 1, 16, "P4", }, /* P4 */
631 { 0xF, 2, 16, "PentiumIV/Xeon", },
632 { 0xF, 6, 16, "PentiumIV/Xeon", },
634 { 3, -1, 32, "386", }, /* family defaults */
635 { 4, -1, 22, "486", },
636 { 5, -1, 23, "P5", },
637 { 6, -1, 16, "P6", },
638 { 0xF, -1, 16, "P4", }, /* P4 */
640 { -1, -1, 16, "unknown", }, /* total default */
644 * The AMD processors all implement the CPUID instruction.
645 * The later ones also return the processor name via functions
646 * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
648 * K5 "AMD-K5(tm) Processor"
649 * K6 "AMD-K6tm w/ multimedia extensions"
650 * K6 3D "AMD-K6(tm) 3D processor"
653 static X86type x86amd[] =
655 { 5, 0, 23, "AMD-K5", }, /* guesswork */
656 { 5, 1, 23, "AMD-K5", }, /* guesswork */
657 { 5, 2, 23, "AMD-K5", }, /* guesswork */
658 { 5, 3, 23, "AMD-K5", }, /* guesswork */
659 { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
660 { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
661 { 5, 6, 11, "AMD-K6", }, /* trial and error */
662 { 5, 7, 11, "AMD-K6", }, /* trial and error */
663 { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
664 { 5, 9, 11, "AMD-K6-III", },/* trial and error */
665 { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
667 { 6, 1, 11, "AMD-Athlon", },/* trial and error */
668 { 6, 2, 11, "AMD-Athlon", },/* trial and error */
670 { 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
672 { 4, -1, 22, "Am486", }, /* guesswork */
673 { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
674 { 6, -1, 11, "AMD-Athlon", },/* guesswork */
675 { 0xF, -1, 11, "AMD-K8", }, /* guesswork */
676 { 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
678 { -1, -1, 11, "unknown", }, /* total default */
684 static X86type x86winchip[] =
686 {5, 4, 23, "Winchip",}, /* guesswork */
687 {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
688 {6, 8, 23, "Via C3 Ezra-T",},
689 {6, 9, 23, "Via C3 Eden-N",},
690 { -1, -1, 23, "unknown", }, /* total default */
696 static X86type x86sis[] =
698 {5, 0, 23, "SiS 55x",}, /* guesswork */
699 { -1, -1, 23, "unknown", }, /* total default */
702 static X86type *cputype;
704 static void simplecycles(uvlong*);
705 void (*cycles)(uvlong*) = simplecycles;
706 void _cycles(uvlong*); /* in l.s */
709 simplecycles(uvlong*x)
717 print("cpu%d: %dMHz %s %s (AX %8.8uX CX %8.8uX DX %8.8uX)\n",
718 m->machno, m->cpumhz, m->cpuidid, m->cpuidtype,
719 m->cpuidax, m->cpuidcx, m->cpuiddx);
725 * - whether or not we have a TSC (cycle counter)
726 * - whether or not it supports page size extensions
728 * - whether or not it supports machine check exceptions
730 * - whether or not it supports the page global flag
737 int family, model, nomce;
743 cpuid(Highstdfunc, regs);
744 memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
745 memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
746 memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
747 m->cpuidid[12] = '\0';
749 cpuid(Procsig, regs);
750 m->cpuidax = regs[0];
751 m->cpuidcx = regs[2];
752 m->cpuiddx = regs[3];
754 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
755 strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
757 else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
759 else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
764 family = X86FAMILY(m->cpuidax);
765 model = X86MODEL(m->cpuidax);
766 for(t=tab; t->name; t++)
767 if((t->family == family && t->model == model)
768 || (t->family == family && t->model == -1)
769 || (t->family == -1))
772 m->cpuidtype = t->name;
775 * if there is one, set tsc to a known value
777 if(m->cpuiddx & Tsc){
780 if(m->cpuiddx & Cpumsr)
785 * use i8253 to guess our cpu speed
787 guesscpuhz(t->aalcycles);
790 * If machine check exception, page size extensions or page global bit
791 * are supported enable them in CR4 and clear any other set extensions.
792 * If machine check was enabled clear out any lingering status.
794 if(m->cpuiddx & (Pge|Mce|Pse)){
797 cr4 |= 0x10; /* page size extensions */
798 if(p = getconf("*nomce"))
799 nomce = strtoul(p, 0, 0);
802 if((m->cpuiddx & Mce) != 0 && !nomce){
803 if((m->cpuiddx & Mca) != 0){
811 wrmsr(0x17B, ~0ULL); /* enable all mca features */
817 /* init MCi .. MC1 (except MC0) */
819 wrmsr(0x400 + bank*4, ~0ULL);
820 wrmsr(0x401 + bank*4, 0);
823 if(family != 6 || model >= 0x1A)
828 else if(family == 5){
832 cr4 |= 0x40; /* machine check enable */
836 * Detect whether the chip supports the global bit
837 * in page directory and page table entries. When set
838 * in a particular entry, it means ``don't bother removing
839 * this from the TLB when CR3 changes.''
841 * We flag all kernel pages with this bit. Doing so lessens the
842 * overhead of switching processes on bare hardware,
843 * even more so on VMware. See mmu.c:/^memglobal.
845 * For future reference, should we ever need to do a
846 * full TLB flush, it can be accomplished by clearing
847 * the PGE bit in CR4, writing to CR3, and then
848 * restoring the PGE bit.
850 if(m->cpuiddx & Pge){
851 cr4 |= 0x80; /* page global enable bit */
857 if((m->cpuiddx & (Mca|Mce)) == Mce)
861 if(m->cpuiddx & Mtrr)
864 if((m->cpuiddx & (Sse|Fxsr)) == (Sse|Fxsr)){ /* have sse fp? */
866 fprestore = fpsserestore;
867 putcr4(getcr4() | CR4Osfxsr|CR4Oxmmex);
870 fprestore = fpx87restore;
873 if(strcmp(m->cpuidid, "GenuineIntel") == 0 && (m->cpuidcx & Rdrnd) != 0)
874 hwrandbuf = rdrandbuf;
883 cputyperead(Chan*, void *a, long n, vlong offset)
888 mhz = (m->cpuhz+999999)/1000000;
890 snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
891 return readstr(offset, a, n, str);
895 archctlread(Chan*, void *a, long nn, vlong offset)
900 p = buf = smalloc(READSTR);
902 p = seprint(p, ep, "cpu %s %lud%s\n",
903 cputype->name, (ulong)(m->cpuhz+999999)/1000000,
904 m->havepge ? " pge" : "");
905 p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
906 p = seprint(p, ep, "coherence ");
907 if(coherence == mb386)
908 p = seprint(p, ep, "mb386\n");
909 else if(coherence == mb586)
910 p = seprint(p, ep, "mb586\n");
911 else if(coherence == mfence)
912 p = seprint(p, ep, "mfence\n");
913 else if(coherence == nop)
914 p = seprint(p, ep, "nop\n");
916 p = seprint(p, ep, "0x%p\n", coherence);
917 p = seprint(p, ep, "cmpswap ");
918 if(cmpswap == cmpswap386)
919 p = seprint(p, ep, "cmpswap386\n");
920 else if(cmpswap == cmpswap486)
921 p = seprint(p, ep, "cmpswap486\n");
923 p = seprint(p, ep, "0x%p\n", cmpswap);
924 p = seprint(p, ep, "arch %s\n", arch->id);
926 n += mtrrprint(p, ep - p);
929 n = readstr(offset, a, nn, buf);
941 static Cmdtab archctlmsg[] =
944 CMcoherence, "coherence", 2,
949 archctlwrite(Chan*, void *a, long n, vlong)
961 ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
965 error("processor does not support pge");
966 if(strcmp(cb->f[1], "on") == 0)
967 putcr4(getcr4() | 0x80);
968 else if(strcmp(cb->f[1], "off") == 0)
969 putcr4(getcr4() & ~0x80);
971 cmderror(cb, "invalid pge ctl");
974 if(strcmp(cb->f[1], "mb386") == 0)
976 else if(strcmp(cb->f[1], "mb586") == 0){
977 if(X86FAMILY(m->cpuidax) < 5)
978 error("invalid coherence ctl on this cpu family");
980 }else if(strcmp(cb->f[1], "mfence") == 0){
981 if((m->cpuiddx & Sse2) == 0)
982 error("invalid coherence ctl on this cpu family");
984 }else if(strcmp(cb->f[1], "nop") == 0){
985 /* only safe on vmware */
987 error("cannot disable coherence on a multiprocessor");
990 cmderror(cb, "invalid coherence ctl");
993 base = strtoull(cb->f[1], &ep, 0);
995 error("cache: parse error: base not a number?");
996 size = strtoull(cb->f[2], &ep, 0);
998 error("cache: parse error: size not a number?");
999 ep = mtrr(base, size, cb->f[3]);
1010 rmemrw(int isr, void *a, long n, vlong off)
1014 if(off < 0 || n < 0)
1015 error("bad offset/count");
1021 memmove(a, KADDR(addr), n);
1023 /* allow vga framebuf's write access */
1024 if(addr >= MB || addr+n > MB ||
1025 (addr < 0xA0000 || addr+n > 0xB0000+0x10000))
1026 error("bad offset/count in write");
1027 memmove(KADDR(addr), a, n);
1033 rmemread(Chan*, void *a, long n, vlong off)
1035 return rmemrw(1, a, n, off);
1039 rmemwrite(Chan*, void *a, long n, vlong off)
1041 return rmemrw(0, a, n, off);
1049 arch = &archgeneric;
1050 for(p = knownarch; *p != nil; p++){
1051 if((*p)->ident != nil && (*p)->ident() == 0){
1056 if(arch != &archgeneric){
1058 arch->id = archgeneric.id;
1059 if(arch->reset == nil)
1060 arch->reset = archgeneric.reset;
1061 if(arch->serialpower == nil)
1062 arch->serialpower = archgeneric.serialpower;
1063 if(arch->modempower == nil)
1064 arch->modempower = archgeneric.modempower;
1065 if(arch->intrinit == nil)
1066 arch->intrinit = archgeneric.intrinit;
1067 if(arch->intrenable == nil)
1068 arch->intrenable = archgeneric.intrenable;
1072 * Decide whether to use copy-on-reference (386 and mp).
1073 * We get another chance to set it in mpinit() for a
1076 if(X86FAMILY(m->cpuidax) == 3)
1079 if(X86FAMILY(m->cpuidax) >= 4)
1080 cmpswap = cmpswap486;
1082 if(X86FAMILY(m->cpuidax) >= 5)
1085 if(m->cpuiddx & Sse2)
1088 addarchfile("cputype", 0444, cputyperead, nil);
1089 addarchfile("archctl", 0664, archctlread, archctlwrite);
1090 addarchfile("realmodemem", 0660, rmemread, rmemwrite);
1094 * call either the pcmcia or pccard device setup
1097 pcmspecial(char *idstr, ISAConf *isa)
1099 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
1103 * call either the pcmcia or pccard device teardown
1106 pcmspecialclose(int a)
1108 if (_pcmspecialclose != nil)
1109 _pcmspecialclose(a);
1113 * return value and speed of timer set in arch->clockenable
1116 fastticks(uvlong *hz)
1118 return (*arch->fastclock)(hz);
1124 return fastticks2us((*arch->fastclock)(nil));
1128 * set next timer interrupt
1133 (*arch->timerset)(x);
1137 * put the processor in the halt state if we've no processes to run.
1138 * an interrupt will get us going again.
1140 * halting in an smp system can result in a startup latency for
1141 * processes that become ready.
1142 * if idle_spin is zero, we care more about saving energy
1143 * than reducing this latency.
1145 * the performance loss with idle_spin == 0 seems to be slight
1146 * and it reduces lock contention (thus system time and real time)
1147 * on many-core systems with large values of NPROC.
1152 extern int nrdy, idle_spin;
1156 else if(m->cpuidcx & Monitor)
1158 else if(idle_spin == 0)
1163 isaconfig(char *class, int ctlrno, ISAConf *isa)
1168 snprint(cc, sizeof cc, "%s%d", class, ctlrno);
1174 isa->nopt = tokenize(p, isa->opt, NISAOPT);
1175 for(i = 0; i < isa->nopt; i++){
1177 if(cistrncmp(p, "type=", 5) == 0)
1179 else if(cistrncmp(p, "port=", 5) == 0)
1180 isa->port = strtoul(p+5, &p, 0);
1181 else if(cistrncmp(p, "irq=", 4) == 0)
1182 isa->irq = strtoul(p+4, &p, 0);
1183 else if(cistrncmp(p, "dma=", 4) == 0)
1184 isa->dma = strtoul(p+4, &p, 0);
1185 else if(cistrncmp(p, "mem=", 4) == 0)
1186 isa->mem = strtoul(p+4, &p, 0);
1187 else if(cistrncmp(p, "size=", 5) == 0)
1188 isa->size = strtoul(p+5, &p, 0);
1189 else if(cistrncmp(p, "freq=", 5) == 0)
1190 isa->freq = strtoul(p+5, &p, 0);
1201 if((m->cpuiddx & (Mce|Cpumsr)) != (Mce|Cpumsr))
1203 if((m->cpuiddx & Mca) == 0){
1206 iprint("MCA %8.8llux MCT %8.8llux\n", v, w);
1211 iprint("MCG CAP %.16llux STATUS %.16llux\n", v, w);
1217 rdmsr(0x401 + bank*4, &v);
1218 if((v & (1ull << 63)) == 0)
1220 iprint("MC%d STATUS %.16llux", bank, v);
1221 if(v & (1ull << 58)){
1222 rdmsr(0x402 + bank*4, &w);
1223 iprint(" ADDR %.16llux", w);
1225 if(v & (1ull << 59)){
1226 rdmsr(0x403 + bank*4, &w);
1227 iprint(" MISC %.16llux", w);