2 #include "../port/lib.h"
8 #include "../port/error.h"
10 typedef struct IOMap IOMap;
25 IOMap maps[32]; /* some initial free maps */
27 QLock ql; /* lock for reading map */
41 enum { /* cpuid standard function codes */
42 Highstdfunc = 0, /* also returns vendor string */
48 typedef long Rdwrfn(Chan*, void*, long, vlong);
50 static Rdwrfn *readfn[Qmax];
51 static Rdwrfn *writefn[Qmax];
53 static Dirtab archdir[Qmax] = {
54 ".", { Qdir, 0, QTDIR }, 0, 0555,
55 "ioalloc", { Qioalloc, 0 }, 0, 0444,
56 "iob", { Qiob, 0 }, 0, 0660,
57 "iow", { Qiow, 0 }, 0, 0660,
58 "iol", { Qiol, 0 }, 0, 0660,
59 "msr", { Qmsr, 0}, 0, 0660,
61 Lock archwlock; /* the lock is only for changing archdir */
63 int (*_pcmspecial)(char*, ISAConf*);
64 void (*_pcmspecialclose)(int);
66 static int doi8253set = 1;
69 * Add a file to the #P listing. Once added, you can't delete it.
70 * You can't add a file with the same name as one already there,
71 * and you get a pointer to the Dirtab entry so you can do things
72 * like change the Qid version. Changing the Qid path is disallowed.
75 addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
81 memset(&d, 0, sizeof d);
91 for(i=0; i<narchdir; i++)
92 if(strcmp(archdir[i].name, name) == 0){
97 d.qid.path = narchdir;
98 archdir[narchdir] = d;
99 readfn[narchdir] = rdfn;
100 writefn[narchdir] = wrfn;
101 dp = &archdir[narchdir++];
113 for(i = 0; i < nelem(iomap.maps)-1; i++)
114 iomap.maps[i].next = &iomap.maps[i+1];
115 iomap.maps[i].next = nil;
116 iomap.free = iomap.maps;
119 * This is necessary to make the IBM X20 boot.
120 * Have not tracked down the reason.
121 * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
123 ioalloc(0x0fff, 1, 0, "dummy");
125 if ((excluded = getconf("ioexclude")) != nil) {
129 while (s && *s != '\0' && *s != '\n') {
133 io_s = (int)strtol(s, &ends, 0);
134 if (ends == nil || ends == s || *ends != '-') {
135 print("ioinit: cannot parse option string\n");
140 io_e = (int)strtol(s, &ends, 0);
141 if (ends && *ends == ',')
145 ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
152 * Reserve a range to be ioalloced later.
153 * This is in particular useful for exchangable cards, such
154 * as pcmcia and cardbus cards.
157 ioreserve(int, int size, int align, char *tag)
163 /* find a free port above 0x400 and below 0x1000 */
165 for(l = &iomap.m; *l; l = &(*l)->next){
167 if (m->start < 0x400) continue;
172 port = ((port+align-1)/align)*align;
182 print("ioalloc: out of maps");
186 iomap.free = m->next;
189 m->end = port + size;
191 strncpy(m->tag, tag, sizeof(m->tag)-1);
192 m->tag[sizeof(m->tag)-1] = 0;
195 archdir[0].qid.vers++;
202 * alloc some io port space and remember who it was
203 * alloced to. if port < 0, find a free region.
206 ioalloc(int port, int size, int align, char *tag)
213 /* find a free port above 0x400 and below 0x1000 */
215 for(l = &iomap.m; *l; l = &(*l)->next){
217 if (m->start < 0x400) continue;
222 port = ((port+align-1)/align)*align;
231 /* Only 64KB I/O space on the x86. */
232 if((port+size) > 0x10000){
236 /* see if the space clashes with previously allocated ports */
237 for(l = &iomap.m; *l; l = &(*l)->next){
241 if(m->reserved && m->start == port && m->end >= port + size) {
246 if(m->start >= port+size)
254 print("ioalloc: out of maps");
258 iomap.free = m->next;
261 m->end = port + size;
262 strncpy(m->tag, tag, sizeof(m->tag)-1);
263 m->tag[sizeof(m->tag)-1] = 0;
266 archdir[0].qid.vers++;
278 for(l = &iomap.m; *l; l = &(*l)->next){
279 if((*l)->start == port){
282 m->next = iomap.free;
286 if((*l)->start > port)
289 archdir[0].qid.vers++;
294 iounused(int start, int end)
298 for(m = iomap.m; m; m = m->next){
299 if(start >= m->start && start < m->end
300 || start <= m->start && end > m->start)
307 checkport(int start, int end)
309 /* standard vga regs are OK */
310 if(start >= 0x2b0 && end <= 0x2df+1)
312 if(start >= 0x3c0 && end <= 0x3da+1)
315 if(iounused(start, end))
321 archattach(char* spec)
323 return devattach('P', spec);
327 archwalk(Chan* c, Chan *nc, char** name, int nname)
329 return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
333 archstat(Chan* c, uchar* dp, int n)
335 return devstat(c, dp, n, archdir, narchdir, devgen);
339 archopen(Chan* c, int omode)
341 return devopen(c, omode, archdir, narchdir, devgen);
355 archread(Chan *c, void *a, long n, vlong offset)
365 switch((ulong)c->qid.path){
368 return devdirread(c, a, n, archdir, narchdir, devgen);
372 checkport(offset, offset+n);
373 for(p = a; port < offset+n; port++)
380 checkport(offset, offset+n);
382 for(port = offset; port < offset+n; port += 2)
389 checkport(offset, offset+n);
391 for(port = offset; port < offset+n; port += 4)
399 for(port = offset; port < offset+n; port += 8)
400 if(rdmsr(port, vp++) < 0)
408 if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
409 return fn(c, a, n, offset);
414 if((buf = malloc(n)) == nil)
418 offset = offset/Linelen;
421 for(m = iomap.m; n > 0 && m != nil; m = m->next){
424 sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
438 archwrite(Chan *c, void *a, long n, vlong offset)
447 switch((ulong)c->qid.path){
451 checkport(offset, offset+n);
452 for(port = offset; port < offset+n; port++)
459 checkport(offset, offset+n);
461 for(port = offset; port < offset+n; port += 2)
468 checkport(offset, offset+n);
470 for(port = offset; port < offset+n; port += 4)
478 for(port = offset; port < offset+n; port += 8)
479 if(wrmsr(port, *vp++) < 0)
484 if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
485 return fn(c, a, n, offset);
514 * the following is a generic version of the
515 * architecture specific stuff
535 * Often the BIOS hangs during restart if a conventional 8042
536 * warm-boot sequence is tried. The following is Intel specific and
537 * seems to perform a cold-boot, but at least it comes back.
538 * And sometimes there is no keyboard...
540 * The reset register (0xcf9) is usually in one of the bridge
541 * chips. The actual location and sequence could be extracted from
542 * ACPI but why bother, this is the end of the line anyway.
544 print("Takes a licking and keeps on ticking...\n");
545 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
554 * 386 has no compare-and-swap instruction.
555 * Run it with interrupts turned off instead.
558 cmpswap386(long *addr, long old, long new)
563 if(r = (*addr == old))
570 * On a uniprocessor, you'd think that coherence could be nop,
571 * but it can't. We still need a barrier when using coherence() in
574 * On VMware, it's safe (and a huge win) to set this to nop.
575 * Aux/vmware does this via the #P/archctl file.
577 void (*coherence)(void) = nop;
579 int (*cmpswap)(long*, long, long) = cmpswap386;
582 extern PCArch* knownarch[];
584 PCArch archgeneric = {
588 .serialpower= unimplemented,
589 .modempower= unimplemented,
591 .intrinit= i8259init,
592 .intrenable= i8259enable,
593 .intrvecno= i8259vecno,
594 .intrdisable= i8259disable,
598 .clockenable= i8253enable,
599 .fastclock= i8253read,
600 .timerset= i8253timerset,
603 typedef struct X86type X86type;
611 static X86type x86intel[] =
613 { 4, 0, 22, "486DX", }, /* known chips */
614 { 4, 1, 22, "486DX50", },
615 { 4, 2, 22, "486SX", },
616 { 4, 3, 22, "486DX2", },
617 { 4, 4, 22, "486SL", },
618 { 4, 5, 22, "486SX2", },
619 { 4, 7, 22, "DX2WB", }, /* P24D */
620 { 4, 8, 22, "DX4", }, /* P24C */
621 { 4, 9, 22, "DX4WB", }, /* P24CT */
624 { 5, 2, 23, "P54C", },
625 { 5, 3, 23, "P24T", },
626 { 5, 4, 23, "P55C MMX", },
627 { 5, 7, 23, "P54C VRT", },
628 { 6, 1, 16, "PentiumPro", },/* trial and error */
629 { 6, 3, 16, "PentiumII", },
630 { 6, 5, 16, "PentiumII/Xeon", },
631 { 6, 6, 16, "Celeron", },
632 { 6, 7, 16, "PentiumIII/Xeon", },
633 { 6, 8, 16, "PentiumIII/Xeon", },
634 { 6, 0xB, 16, "PentiumIII/Xeon", },
635 { 6, 0xF, 16, "Xeon5000-series", },
636 { 6, 0x16, 16, "Celeron", },
637 { 6, 0x17, 16, "Core 2/Xeon", },
638 { 6, 0x1A, 16, "Core i7/Xeon", },
639 { 6, 0x1C, 16, "Atom", },
640 { 6, 0x1D, 16, "Xeon MP", },
641 { 0xF, 1, 16, "P4", }, /* P4 */
642 { 0xF, 2, 16, "PentiumIV/Xeon", },
643 { 0xF, 6, 16, "PentiumIV/Xeon", },
645 { 3, -1, 32, "386", }, /* family defaults */
646 { 4, -1, 22, "486", },
647 { 5, -1, 23, "P5", },
648 { 6, -1, 16, "P6", },
649 { 0xF, -1, 16, "P4", }, /* P4 */
651 { -1, -1, 16, "unknown", }, /* total default */
655 * The AMD processors all implement the CPUID instruction.
656 * The later ones also return the processor name via functions
657 * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
659 * K5 "AMD-K5(tm) Processor"
660 * K6 "AMD-K6tm w/ multimedia extensions"
661 * K6 3D "AMD-K6(tm) 3D processor"
664 static X86type x86amd[] =
666 { 5, 0, 23, "AMD-K5", }, /* guesswork */
667 { 5, 1, 23, "AMD-K5", }, /* guesswork */
668 { 5, 2, 23, "AMD-K5", }, /* guesswork */
669 { 5, 3, 23, "AMD-K5", }, /* guesswork */
670 { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
671 { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
672 { 5, 6, 11, "AMD-K6", }, /* trial and error */
673 { 5, 7, 11, "AMD-K6", }, /* trial and error */
674 { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
675 { 5, 9, 11, "AMD-K6-III", },/* trial and error */
676 { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
678 { 6, 1, 11, "AMD-Athlon", },/* trial and error */
679 { 6, 2, 11, "AMD-Athlon", },/* trial and error */
681 { 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
683 { 4, -1, 22, "Am486", }, /* guesswork */
684 { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
685 { 6, -1, 11, "AMD-Athlon", },/* guesswork */
686 { 0xF, -1, 11, "AMD-K8", }, /* guesswork */
687 { 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
689 { -1, -1, 11, "unknown", }, /* total default */
695 static X86type x86winchip[] =
697 {5, 4, 23, "Winchip",}, /* guesswork */
698 {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
699 {6, 8, 23, "Via C3 Ezra-T",},
700 {6, 9, 23, "Via C3 Eden-N",},
701 { -1, -1, 23, "unknown", }, /* total default */
707 static X86type x86sis[] =
709 {5, 0, 23, "SiS 55x",}, /* guesswork */
710 { -1, -1, 23, "unknown", }, /* total default */
713 static X86type *cputype;
715 static void simplecycles(uvlong*);
716 void (*cycles)(uvlong*) = simplecycles;
717 void _cycles(uvlong*); /* in l.s */
720 simplecycles(uvlong*x)
731 i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
733 i += sprint(buf+i, "%12.12s ", m->cpuidid);
734 seprint(buf+i, buf + sizeof buf - 1,
735 "%s (cpuid: AX 0x%4.4uX CX 0x%4.4uX DX 0x%4.4uX)\n",
736 m->cpuidtype, m->cpuidax, m->cpuidcx, m->cpuiddx);
743 * - whether or not we have a TSC (cycle counter)
744 * - whether or not it supports page size extensions
746 * - whether or not it supports machine check exceptions
748 * - whether or not it supports the page global flag
755 int family, model, nomce;
761 cpuid(Highstdfunc, regs);
762 memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
763 memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
764 memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
765 m->cpuidid[12] = '\0';
767 cpuid(Procsig, regs);
768 m->cpuidax = regs[0];
769 m->cpuidcx = regs[2];
770 m->cpuiddx = regs[3];
772 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
773 strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
775 else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
777 else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
782 family = X86FAMILY(m->cpuidax);
783 model = X86MODEL(m->cpuidax);
784 for(t=tab; t->name; t++)
785 if((t->family == family && t->model == model)
786 || (t->family == family && t->model == -1)
787 || (t->family == -1))
790 m->cpuidtype = t->name;
793 * if there is one, set tsc to a known value
795 if(m->cpuiddx & Tsc){
798 if(m->cpuiddx & Cpumsr)
803 * use i8253 to guess our cpu speed
805 guesscpuhz(t->aalcycles);
808 * If machine check exception, page size extensions or page global bit
809 * are supported enable them in CR4 and clear any other set extensions.
810 * If machine check was enabled clear out any lingering status.
812 if(m->cpuiddx & (Pge|Mce|Pse)){
815 cr4 |= 0x10; /* page size extensions */
816 if(p = getconf("*nomce"))
817 nomce = strtoul(p, 0, 0);
820 if((m->cpuiddx & Mce) && !nomce){
821 cr4 |= 0x40; /* machine check enable */
829 * Detect whether the chip supports the global bit
830 * in page directory and page table entries. When set
831 * in a particular entry, it means ``don't bother removing
832 * this from the TLB when CR3 changes.''
834 * We flag all kernel pages with this bit. Doing so lessens the
835 * overhead of switching processes on bare hardware,
836 * even more so on VMware. See mmu.c:/^memglobal.
838 * For future reference, should we ever need to do a
839 * full TLB flush, it can be accomplished by clearing
840 * the PGE bit in CR4, writing to CR3, and then
841 * restoring the PGE bit.
843 if(m->cpuiddx & Pge){
844 cr4 |= 0x80; /* page global enable bit */
858 cputyperead(Chan*, void *a, long n, vlong offset)
863 mhz = (m->cpuhz+999999)/1000000;
865 snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
866 return readstr(offset, a, n, str);
870 archctlread(Chan*, void *a, long nn, vlong offset)
875 p = buf = smalloc(READSTR);
877 p = seprint(p, ep, "cpu %s %lud%s\n",
878 cputype->name, (ulong)(m->cpuhz+999999)/1000000,
879 m->havepge ? " pge" : "");
880 p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
881 p = seprint(p, ep, "coherence ");
882 if(coherence == mb386)
883 p = seprint(p, ep, "mb386\n");
884 else if(coherence == mb586)
885 p = seprint(p, ep, "mb586\n");
886 else if(coherence == mfence)
887 p = seprint(p, ep, "mfence\n");
888 else if(coherence == nop)
889 p = seprint(p, ep, "nop\n");
891 p = seprint(p, ep, "0x%p\n", coherence);
892 p = seprint(p, ep, "cmpswap ");
893 if(cmpswap == cmpswap386)
894 p = seprint(p, ep, "cmpswap386\n");
895 else if(cmpswap == cmpswap486)
896 p = seprint(p, ep, "cmpswap486\n");
898 p = seprint(p, ep, "0x%p\n", cmpswap);
899 p = seprint(p, ep, "i8253set %s\n", doi8253set ? "on" : "off");
901 n += mtrrprint(p, ep - p);
904 n = readstr(offset, a, nn, buf);
917 static Cmdtab archctlmsg[] =
920 CMcoherence, "coherence", 2,
921 CMi8253set, "i8253set", 2,
926 archctlwrite(Chan*, void *a, long n, vlong)
938 ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
942 error("processor does not support pge");
943 if(strcmp(cb->f[1], "on") == 0)
944 putcr4(getcr4() | 0x80);
945 else if(strcmp(cb->f[1], "off") == 0)
946 putcr4(getcr4() & ~0x80);
948 cmderror(cb, "invalid pge ctl");
951 if(strcmp(cb->f[1], "mb386") == 0)
953 else if(strcmp(cb->f[1], "mb586") == 0){
954 if(X86FAMILY(m->cpuidax) < 5)
955 error("invalid coherence ctl on this cpu family");
957 }else if(strcmp(cb->f[1], "mfence") == 0){
958 if((m->cpuiddx & Sse2) == 0)
959 error("invalid coherence ctl on this cpu family");
961 }else if(strcmp(cb->f[1], "nop") == 0){
962 /* only safe on vmware */
964 error("cannot disable coherence on a multiprocessor");
967 cmderror(cb, "invalid coherence ctl");
970 if(strcmp(cb->f[1], "on") == 0)
972 else if(strcmp(cb->f[1], "off") == 0){
974 (*arch->timerset)(0);
976 cmderror(cb, "invalid i2853set ctl");
979 base = strtoull(cb->f[1], &ep, 0);
981 error("cache: parse error: base not a number?");
982 size = strtoull(cb->f[2], &ep, 0);
984 error("cache: parse error: size not a number?");
985 mtrr(base, size, cb->f[3]);
994 rmemrw(int isr, void *a, long n, vlong off)
997 error("bad offset/count");
1003 memmove(a, KADDR((ulong)off), n);
1005 /* allow vga framebuf's access */
1006 if(off >= MB || off+n > MB ||
1007 (off < 0xA0000 || off+n > 0xB0000+0x10000))
1008 error("bad offset/count in write");
1009 memmove(KADDR((ulong)off), a, n);
1015 rmemread(Chan*, void *a, long n, vlong off)
1017 return rmemrw(1, a, n, off);
1021 rmemwrite(Chan*, void *a, long n, vlong off)
1023 return rmemrw(0, a, n, off);
1032 for(p = knownarch; *p; p++){
1033 if((*p)->ident && (*p)->ident() == 0){
1039 arch = &archgeneric;
1042 arch->id = archgeneric.id;
1043 if(arch->reset == 0)
1044 arch->reset = archgeneric.reset;
1045 if(arch->serialpower == 0)
1046 arch->serialpower = archgeneric.serialpower;
1047 if(arch->modempower == 0)
1048 arch->modempower = archgeneric.modempower;
1049 if(arch->intrinit == 0)
1050 arch->intrinit = archgeneric.intrinit;
1051 if(arch->intrenable == 0)
1052 arch->intrenable = archgeneric.intrenable;
1056 * Decide whether to use copy-on-reference (386 and mp).
1057 * We get another chance to set it in mpinit() for a
1060 if(X86FAMILY(m->cpuidax) == 3)
1063 if(X86FAMILY(m->cpuidax) >= 4)
1064 cmpswap = cmpswap486;
1066 if(X86FAMILY(m->cpuidax) >= 5)
1069 if(m->cpuiddx & Sse2)
1072 addarchfile("cputype", 0444, cputyperead, nil);
1073 addarchfile("archctl", 0664, archctlread, archctlwrite);
1074 addarchfile("realmodemem", 0660, rmemread, rmemwrite);
1078 * call either the pcmcia or pccard device setup
1081 pcmspecial(char *idstr, ISAConf *isa)
1083 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
1087 * call either the pcmcia or pccard device teardown
1090 pcmspecialclose(int a)
1092 if (_pcmspecialclose != nil)
1093 _pcmspecialclose(a);
1097 * return value and speed of timer set in arch->clockenable
1100 fastticks(uvlong *hz)
1102 return (*arch->fastclock)(hz);
1108 return fastticks2us((*arch->fastclock)(nil));
1112 * set next timer interrupt
1118 (*arch->timerset)(x);