2 #include "../port/lib.h"
8 #include "../port/error.h"
10 typedef struct IOMap IOMap;
25 IOMap maps[32]; /* some initial free maps */
27 QLock ql; /* lock for reading map */
46 enum { /* cpuid standard function codes */
47 Highstdfunc = 0, /* also returns vendor string */
53 typedef long Rdwrfn(Chan*, void*, long, vlong);
55 static Rdwrfn *readfn[Qmax];
56 static Rdwrfn *writefn[Qmax];
58 static Dirtab archdir[Qmax] = {
59 ".", { Qdir, 0, QTDIR }, 0, 0555,
60 "ioalloc", { Qioalloc, 0 }, 0, 0444,
61 "iob", { Qiob, 0 }, 0, 0660,
62 "iow", { Qiow, 0 }, 0, 0660,
63 "iol", { Qiol, 0 }, 0, 0660,
64 "msr", { Qmsr, 0}, 0, 0660,
66 Lock archwlock; /* the lock is only for changing archdir */
68 int (*_pcmspecial)(char*, ISAConf*);
69 void (*_pcmspecialclose)(int);
71 static int doi8253set = 1;
74 * Add a file to the #P listing. Once added, you can't delete it.
75 * You can't add a file with the same name as one already there,
76 * and you get a pointer to the Dirtab entry so you can do things
77 * like change the Qid version. Changing the Qid path is disallowed.
80 addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
86 memset(&d, 0, sizeof d);
96 for(i=0; i<narchdir; i++)
97 if(strcmp(archdir[i].name, name) == 0){
102 d.qid.path = narchdir;
103 archdir[narchdir] = d;
104 readfn[narchdir] = rdfn;
105 writefn[narchdir] = wrfn;
106 dp = &archdir[narchdir++];
118 for(i = 0; i < nelem(iomap.maps)-1; i++)
119 iomap.maps[i].next = &iomap.maps[i+1];
120 iomap.maps[i].next = nil;
121 iomap.free = iomap.maps;
124 * This is necessary to make the IBM X20 boot.
125 * Have not tracked down the reason.
126 * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
128 ioalloc(0x0fff, 1, 0, "dummy");
130 if ((excluded = getconf("ioexclude")) != nil) {
134 while (s && *s != '\0' && *s != '\n') {
138 io_s = (int)strtol(s, &ends, 0);
139 if (ends == nil || ends == s || *ends != '-') {
140 print("ioinit: cannot parse option string\n");
145 io_e = (int)strtol(s, &ends, 0);
146 if (ends && *ends == ',')
150 ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
157 * Reserve a range to be ioalloced later.
158 * This is in particular useful for exchangable cards, such
159 * as pcmcia and cardbus cards.
162 ioreserve(int, int size, int align, char *tag)
168 /* find a free port above 0x400 and below 0x1000 */
170 for(l = &iomap.m; *l; l = &(*l)->next){
172 if (m->start < 0x400) continue;
177 port = ((port+align-1)/align)*align;
187 print("ioalloc: out of maps");
191 iomap.free = m->next;
194 m->end = port + size;
196 strncpy(m->tag, tag, sizeof(m->tag)-1);
197 m->tag[sizeof(m->tag)-1] = 0;
200 archdir[0].qid.vers++;
207 * alloc some io port space and remember who it was
208 * alloced to. if port < 0, find a free region.
211 ioalloc(int port, int size, int align, char *tag)
218 /* find a free port above 0x400 and below 0x1000 */
220 for(l = &iomap.m; *l; l = &(*l)->next){
222 if (m->start < 0x400) continue;
227 port = ((port+align-1)/align)*align;
236 /* Only 64KB I/O space on the x86. */
237 if((port+size) > 0x10000){
241 /* see if the space clashes with previously allocated ports */
242 for(l = &iomap.m; *l; l = &(*l)->next){
246 if(m->reserved && m->start == port && m->end >= port + size) {
251 if(m->start >= port+size)
259 print("ioalloc: out of maps");
263 iomap.free = m->next;
266 m->end = port + size;
267 strncpy(m->tag, tag, sizeof(m->tag)-1);
268 m->tag[sizeof(m->tag)-1] = 0;
271 archdir[0].qid.vers++;
283 for(l = &iomap.m; *l; l = &(*l)->next){
284 if((*l)->start == port){
287 m->next = iomap.free;
291 if((*l)->start > port)
294 archdir[0].qid.vers++;
299 iounused(int start, int end)
303 for(m = iomap.m; m; m = m->next){
304 if(start >= m->start && start < m->end
305 || start <= m->start && end > m->start)
312 checkport(int start, int end)
314 /* standard vga regs are OK */
315 if(start >= 0x2b0 && end <= 0x2df+1)
317 if(start >= 0x3c0 && end <= 0x3da+1)
320 if(iounused(start, end))
326 archattach(char* spec)
328 return devattach('P', spec);
332 archwalk(Chan* c, Chan *nc, char** name, int nname)
334 return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
338 archstat(Chan* c, uchar* dp, int n)
340 return devstat(c, dp, n, archdir, narchdir, devgen);
344 archopen(Chan* c, int omode)
346 return devopen(c, omode, archdir, narchdir, devgen);
360 archread(Chan *c, void *a, long n, vlong offset)
370 switch((ulong)c->qid.path){
373 return devdirread(c, a, n, archdir, narchdir, devgen);
377 checkport(offset, offset+n);
378 for(p = a; port < offset+n; port++)
385 checkport(offset, offset+n);
387 for(port = offset; port < offset+n; port += 2)
394 checkport(offset, offset+n);
396 for(port = offset; port < offset+n; port += 4)
404 for(port = offset; port < offset+n; port += 8)
405 if(rdmsr(port, vp++) < 0)
413 if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
414 return fn(c, a, n, offset);
419 if((buf = malloc(n)) == nil)
423 offset = offset/Linelen;
426 for(m = iomap.m; n > 0 && m != nil; m = m->next){
429 sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
443 archwrite(Chan *c, void *a, long n, vlong offset)
452 switch((ulong)c->qid.path){
456 checkport(offset, offset+n);
457 for(port = offset; port < offset+n; port++)
464 checkport(offset, offset+n);
466 for(port = offset; port < offset+n; port += 2)
473 checkport(offset, offset+n);
475 for(port = offset; port < offset+n; port += 4)
483 for(port = offset; port < offset+n; port += 8)
484 if(wrmsr(port, *vp++) < 0)
489 if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
490 return fn(c, a, n, offset);
519 * the following is a generic version of the
520 * architecture specific stuff
540 * Often the BIOS hangs during restart if a conventional 8042
541 * warm-boot sequence is tried. The following is Intel specific and
542 * seems to perform a cold-boot, but at least it comes back.
543 * And sometimes there is no keyboard...
545 * The reset register (0xcf9) is usually in one of the bridge
546 * chips. The actual location and sequence could be extracted from
547 * ACPI but why bother, this is the end of the line anyway.
549 print("Takes a licking and keeps on ticking...\n");
550 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
559 * 386 has no compare-and-swap instruction.
560 * Run it with interrupts turned off instead.
563 cmpswap386(long *addr, long old, long new)
568 if(r = (*addr == old))
575 * On a uniprocessor, you'd think that coherence could be nop,
576 * but it can't. We still need a barrier when using coherence() in
579 * On VMware, it's safe (and a huge win) to set this to nop.
580 * Aux/vmware does this via the #P/archctl file.
582 void (*coherence)(void) = nop;
584 int (*cmpswap)(long*, long, long) = cmpswap386;
587 extern PCArch* knownarch[];
589 PCArch archgeneric = {
593 .serialpower= unimplemented,
594 .modempower= unimplemented,
596 .intrinit= i8259init,
597 .intrenable= i8259enable,
598 .intrvecno= i8259vecno,
599 .intrdisable= i8259disable,
603 .clockenable= i8253enable,
604 .fastclock= i8253read,
605 .timerset= i8253timerset,
608 typedef struct X86type X86type;
616 static X86type x86intel[] =
618 { 4, 0, 22, "486DX", }, /* known chips */
619 { 4, 1, 22, "486DX50", },
620 { 4, 2, 22, "486SX", },
621 { 4, 3, 22, "486DX2", },
622 { 4, 4, 22, "486SL", },
623 { 4, 5, 22, "486SX2", },
624 { 4, 7, 22, "DX2WB", }, /* P24D */
625 { 4, 8, 22, "DX4", }, /* P24C */
626 { 4, 9, 22, "DX4WB", }, /* P24CT */
629 { 5, 2, 23, "P54C", },
630 { 5, 3, 23, "P24T", },
631 { 5, 4, 23, "P55C MMX", },
632 { 5, 7, 23, "P54C VRT", },
633 { 6, 1, 16, "PentiumPro", },/* trial and error */
634 { 6, 3, 16, "PentiumII", },
635 { 6, 5, 16, "PentiumII/Xeon", },
636 { 6, 6, 16, "Celeron", },
637 { 6, 7, 16, "PentiumIII/Xeon", },
638 { 6, 8, 16, "PentiumIII/Xeon", },
639 { 6, 0xB, 16, "PentiumIII/Xeon", },
640 { 6, 0xF, 16, "Xeon5000-series", },
641 { 6, 0x16, 16, "Celeron", },
642 { 6, 0x17, 16, "Core 2/Xeon", },
643 { 6, 0x1A, 16, "Core i7/Xeon", },
644 { 6, 0x1C, 16, "Atom", },
645 { 6, 0x1D, 16, "Xeon MP", },
646 { 0xF, 1, 16, "P4", }, /* P4 */
647 { 0xF, 2, 16, "PentiumIV/Xeon", },
648 { 0xF, 6, 16, "PentiumIV/Xeon", },
650 { 3, -1, 32, "386", }, /* family defaults */
651 { 4, -1, 22, "486", },
652 { 5, -1, 23, "P5", },
653 { 6, -1, 16, "P6", },
654 { 0xF, -1, 16, "P4", }, /* P4 */
656 { -1, -1, 16, "unknown", }, /* total default */
660 * The AMD processors all implement the CPUID instruction.
661 * The later ones also return the processor name via functions
662 * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
664 * K5 "AMD-K5(tm) Processor"
665 * K6 "AMD-K6tm w/ multimedia extensions"
666 * K6 3D "AMD-K6(tm) 3D processor"
669 static X86type x86amd[] =
671 { 5, 0, 23, "AMD-K5", }, /* guesswork */
672 { 5, 1, 23, "AMD-K5", }, /* guesswork */
673 { 5, 2, 23, "AMD-K5", }, /* guesswork */
674 { 5, 3, 23, "AMD-K5", }, /* guesswork */
675 { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
676 { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
677 { 5, 6, 11, "AMD-K6", }, /* trial and error */
678 { 5, 7, 11, "AMD-K6", }, /* trial and error */
679 { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
680 { 5, 9, 11, "AMD-K6-III", },/* trial and error */
681 { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
683 { 6, 1, 11, "AMD-Athlon", },/* trial and error */
684 { 6, 2, 11, "AMD-Athlon", },/* trial and error */
686 { 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
688 { 4, -1, 22, "Am486", }, /* guesswork */
689 { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
690 { 6, -1, 11, "AMD-Athlon", },/* guesswork */
691 { 0xF, -1, 11, "AMD-K8", }, /* guesswork */
692 { 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
694 { -1, -1, 11, "unknown", }, /* total default */
700 static X86type x86winchip[] =
702 {5, 4, 23, "Winchip",}, /* guesswork */
703 {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
704 {6, 8, 23, "Via C3 Ezra-T",},
705 {6, 9, 23, "Via C3 Eden-N",},
706 { -1, -1, 23, "unknown", }, /* total default */
712 static X86type x86sis[] =
714 {5, 0, 23, "SiS 55x",}, /* guesswork */
715 { -1, -1, 23, "unknown", }, /* total default */
718 static X86type *cputype;
720 static void simplecycles(uvlong*);
721 void (*cycles)(uvlong*) = simplecycles;
722 void _cycles(uvlong*); /* in l.s */
725 simplecycles(uvlong*x)
736 i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
738 i += sprint(buf+i, "%12.12s ", m->cpuidid);
739 seprint(buf+i, buf + sizeof buf - 1,
740 "%s (cpuid: AX 0x%4.4uX CX 0x%4.4uX DX 0x%4.4uX)\n",
741 m->cpuidtype, m->cpuidax, m->cpuidcx, m->cpuiddx);
748 * - whether or not we have a TSC (cycle counter)
749 * - whether or not it supports page size extensions
751 * - whether or not it supports machine check exceptions
753 * - whether or not it supports the page global flag
760 int family, model, nomce;
766 cpuid(Highstdfunc, regs);
767 memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
768 memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
769 memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
770 m->cpuidid[12] = '\0';
772 cpuid(Procsig, regs);
773 m->cpuidax = regs[0];
774 m->cpuidcx = regs[2];
775 m->cpuiddx = regs[3];
777 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
778 strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
780 else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
782 else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
787 family = X86FAMILY(m->cpuidax);
788 model = X86MODEL(m->cpuidax);
789 for(t=tab; t->name; t++)
790 if((t->family == family && t->model == model)
791 || (t->family == family && t->model == -1)
792 || (t->family == -1))
795 m->cpuidtype = t->name;
798 * if there is one, set tsc to a known value
800 if(m->cpuiddx & Tsc){
803 if(m->cpuiddx & Cpumsr)
809 * use i8253 to guess our cpu speed
811 guesscpuhz(t->aalcycles);
814 * If machine check exception, page size extensions or page global bit
815 * are supported enable them in CR4 and clear any other set extensions.
816 * If machine check was enabled clear out any lingering status.
818 if(m->cpuiddx & (Pge|Mce|Pse)){
821 cr4 |= 0x10; /* page size extensions */
822 if(p = getconf("*nomce"))
823 nomce = strtoul(p, 0, 0);
826 if((m->cpuiddx & Mce) && !nomce){
827 cr4 |= 0x40; /* machine check enable */
835 * Detect whether the chip supports the global bit
836 * in page directory and page table entries. When set
837 * in a particular entry, it means ``don't bother removing
838 * this from the TLB when CR3 changes.''
840 * We flag all kernel pages with this bit. Doing so lessens the
841 * overhead of switching processes on bare hardware,
842 * even more so on VMware. See mmu.c:/^memglobal.
844 * For future reference, should we ever need to do a
845 * full TLB flush, it can be accomplished by clearing
846 * the PGE bit in CR4, writing to CR3, and then
847 * restoring the PGE bit.
849 if(m->cpuiddx & Pge){
850 cr4 |= 0x80; /* page global enable bit */
860 if(m->cpuiddx & Fxsr){ /* have sse fp? */
862 fprestore = fpsserestore;
863 putcr4(getcr4() | CR4Osfxsr);
866 fprestore = fpx87restore;
874 cputyperead(Chan*, void *a, long n, vlong offset)
879 mhz = (m->cpuhz+999999)/1000000;
881 snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
882 return readstr(offset, a, n, str);
886 archctlread(Chan*, void *a, long nn, vlong offset)
891 p = buf = smalloc(READSTR);
893 p = seprint(p, ep, "cpu %s %lud%s\n",
894 cputype->name, (ulong)(m->cpuhz+999999)/1000000,
895 m->havepge ? " pge" : "");
896 p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
897 p = seprint(p, ep, "coherence ");
898 if(coherence == mb386)
899 p = seprint(p, ep, "mb386\n");
900 else if(coherence == mb586)
901 p = seprint(p, ep, "mb586\n");
902 else if(coherence == mfence)
903 p = seprint(p, ep, "mfence\n");
904 else if(coherence == nop)
905 p = seprint(p, ep, "nop\n");
907 p = seprint(p, ep, "0x%p\n", coherence);
908 p = seprint(p, ep, "cmpswap ");
909 if(cmpswap == cmpswap386)
910 p = seprint(p, ep, "cmpswap386\n");
911 else if(cmpswap == cmpswap486)
912 p = seprint(p, ep, "cmpswap486\n");
914 p = seprint(p, ep, "0x%p\n", cmpswap);
915 p = seprint(p, ep, "i8253set %s\n", doi8253set ? "on" : "off");
917 n += mtrrprint(p, ep - p);
920 n = readstr(offset, a, nn, buf);
933 static Cmdtab archctlmsg[] =
936 CMcoherence, "coherence", 2,
937 CMi8253set, "i8253set", 2,
942 archctlwrite(Chan*, void *a, long n, vlong)
954 ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
958 error("processor does not support pge");
959 if(strcmp(cb->f[1], "on") == 0)
960 putcr4(getcr4() | 0x80);
961 else if(strcmp(cb->f[1], "off") == 0)
962 putcr4(getcr4() & ~0x80);
964 cmderror(cb, "invalid pge ctl");
967 if(strcmp(cb->f[1], "mb386") == 0)
969 else if(strcmp(cb->f[1], "mb586") == 0){
970 if(X86FAMILY(m->cpuidax) < 5)
971 error("invalid coherence ctl on this cpu family");
973 }else if(strcmp(cb->f[1], "mfence") == 0){
974 if((m->cpuiddx & Sse2) == 0)
975 error("invalid coherence ctl on this cpu family");
977 }else if(strcmp(cb->f[1], "nop") == 0){
978 /* only safe on vmware */
980 error("cannot disable coherence on a multiprocessor");
983 cmderror(cb, "invalid coherence ctl");
986 if(strcmp(cb->f[1], "on") == 0)
988 else if(strcmp(cb->f[1], "off") == 0){
990 (*arch->timerset)(0);
992 cmderror(cb, "invalid i2853set ctl");
995 base = strtoull(cb->f[1], &ep, 0);
997 error("cache: parse error: base not a number?");
998 size = strtoull(cb->f[2], &ep, 0);
1000 error("cache: parse error: size not a number?");
1001 mtrr(base, size, cb->f[3]);
1010 rmemrw(int isr, void *a, long n, vlong off)
1012 if(off < 0 || n < 0)
1013 error("bad offset/count");
1019 memmove(a, KADDR((ulong)off), n);
1021 /* allow vga framebuf's access */
1022 if(off >= MB || off+n > MB ||
1023 (off < 0xA0000 || off+n > 0xB0000+0x10000))
1024 error("bad offset/count in write");
1025 memmove(KADDR((ulong)off), a, n);
1031 rmemread(Chan*, void *a, long n, vlong off)
1033 return rmemrw(1, a, n, off);
1037 rmemwrite(Chan*, void *a, long n, vlong off)
1039 return rmemrw(0, a, n, off);
1048 for(p = knownarch; *p; p++){
1049 if((*p)->ident && (*p)->ident() == 0){
1055 arch = &archgeneric;
1058 arch->id = archgeneric.id;
1059 if(arch->reset == 0)
1060 arch->reset = archgeneric.reset;
1061 if(arch->serialpower == 0)
1062 arch->serialpower = archgeneric.serialpower;
1063 if(arch->modempower == 0)
1064 arch->modempower = archgeneric.modempower;
1065 if(arch->intrinit == 0)
1066 arch->intrinit = archgeneric.intrinit;
1067 if(arch->intrenable == 0)
1068 arch->intrenable = archgeneric.intrenable;
1072 * Decide whether to use copy-on-reference (386 and mp).
1073 * We get another chance to set it in mpinit() for a
1076 if(X86FAMILY(m->cpuidax) == 3)
1079 if(X86FAMILY(m->cpuidax) >= 4)
1080 cmpswap = cmpswap486;
1082 if(X86FAMILY(m->cpuidax) >= 5)
1085 if(m->cpuiddx & Sse2)
1088 addarchfile("cputype", 0444, cputyperead, nil);
1089 addarchfile("archctl", 0664, archctlread, archctlwrite);
1090 addarchfile("realmodemem", 0660, rmemread, rmemwrite);
1094 * call either the pcmcia or pccard device setup
1097 pcmspecial(char *idstr, ISAConf *isa)
1099 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
1103 * call either the pcmcia or pccard device teardown
1106 pcmspecialclose(int a)
1108 if (_pcmspecialclose != nil)
1109 _pcmspecialclose(a);
1113 * return value and speed of timer set in arch->clockenable
1116 fastticks(uvlong *hz)
1118 return (*arch->fastclock)(hz);
1124 return fastticks2us((*arch->fastclock)(nil));
1128 * set next timer interrupt
1134 (*arch->timerset)(x);
1138 * put the processor in the halt state if we've no processes to run.
1139 * an interrupt will get us going again.
1141 * halting in an smp system can result in a startup latency for
1142 * processes that become ready.
1143 * if idle_spin is zero, we care more about saving energy
1144 * than reducing this latency.
1146 * the performance loss with idle_spin == 0 seems to be slight
1147 * and it reduces lock contention (thus system time and real time)
1148 * on many-core systems with large values of NPROC.
1153 extern int nrdy, idle_spin;
1157 else if(m->cpuidcx & Monitor)
1159 else if(idle_spin == 0)
1164 isaconfig(char *class, int ctlrno, ISAConf *isa)
1169 snprint(cc, sizeof cc, "%s%d", class, ctlrno);
1175 isa->nopt = tokenize(p, isa->opt, NISAOPT);
1176 for(i = 0; i < isa->nopt; i++){
1178 if(cistrncmp(p, "type=", 5) == 0)
1180 else if(cistrncmp(p, "port=", 5) == 0)
1181 isa->port = strtoul(p+5, &p, 0);
1182 else if(cistrncmp(p, "irq=", 4) == 0)
1183 isa->irq = strtoul(p+4, &p, 0);
1184 else if(cistrncmp(p, "dma=", 4) == 0)
1185 isa->dma = strtoul(p+4, &p, 0);
1186 else if(cistrncmp(p, "mem=", 4) == 0)
1187 isa->mem = strtoul(p+4, &p, 0);
1188 else if(cistrncmp(p, "size=", 5) == 0)
1189 isa->size = strtoul(p+5, &p, 0);
1190 else if(cistrncmp(p, "freq=", 5) == 0)
1191 isa->freq = strtoul(p+5, &p, 0);