2 #include "../port/lib.h"
8 #include "../port/error.h"
10 typedef struct IOMap IOMap;
25 IOMap maps[32]; /* some initial free maps */
27 QLock ql; /* lock for reading map */
48 enum { /* cpuid standard function codes */
49 Highstdfunc = 0, /* also returns vendor string */
55 typedef long Rdwrfn(Chan*, void*, long, vlong);
57 static Rdwrfn *readfn[Qmax];
58 static Rdwrfn *writefn[Qmax];
60 static Dirtab archdir[Qmax] = {
61 ".", { Qdir, 0, QTDIR }, 0, 0555,
62 "ioalloc", { Qioalloc, 0 }, 0, 0444,
63 "iob", { Qiob, 0 }, 0, 0660,
64 "iow", { Qiow, 0 }, 0, 0660,
65 "iol", { Qiol, 0 }, 0, 0660,
66 "msr", { Qmsr, 0 }, 0, 0660,
67 "ec", { Qec, 0 }, 0, 0660,
69 Lock archwlock; /* the lock is only for changing archdir */
71 int (*_pcmspecial)(char*, ISAConf*);
72 void (*_pcmspecialclose)(int);
74 static int doi8253set = 1;
77 * Add a file to the #P listing. Once added, you can't delete it.
78 * You can't add a file with the same name as one already there,
79 * and you get a pointer to the Dirtab entry so you can do things
80 * like change the Qid version. Changing the Qid path is disallowed.
83 addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
89 memset(&d, 0, sizeof d);
99 for(i=0; i<narchdir; i++)
100 if(strcmp(archdir[i].name, name) == 0){
105 d.qid.path = narchdir;
106 archdir[narchdir] = d;
107 readfn[narchdir] = rdfn;
108 writefn[narchdir] = wrfn;
109 dp = &archdir[narchdir++];
121 for(i = 0; i < nelem(iomap.maps)-1; i++)
122 iomap.maps[i].next = &iomap.maps[i+1];
123 iomap.maps[i].next = nil;
124 iomap.free = iomap.maps;
127 * This is necessary to make the IBM X20 boot.
128 * Have not tracked down the reason.
129 * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
131 ioalloc(0x0fff, 1, 0, "dummy");
133 if ((excluded = getconf("ioexclude")) != nil) {
137 while (s && *s != '\0' && *s != '\n') {
141 io_s = (int)strtol(s, &ends, 0);
142 if (ends == nil || ends == s || *ends != '-') {
143 print("ioinit: cannot parse option string\n");
148 io_e = (int)strtol(s, &ends, 0);
149 if (ends && *ends == ',')
153 ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
160 * Reserve a range to be ioalloced later.
161 * This is in particular useful for exchangable cards, such
162 * as pcmcia and cardbus cards.
165 ioreserve(int, int size, int align, char *tag)
171 /* find a free port above 0x400 and below 0x1000 */
173 for(l = &iomap.m; *l; l = &(*l)->next){
175 if (m->start < 0x400) continue;
180 port = ((port+align-1)/align)*align;
190 print("ioalloc: out of maps");
194 iomap.free = m->next;
197 m->end = port + size;
199 strncpy(m->tag, tag, sizeof(m->tag)-1);
200 m->tag[sizeof(m->tag)-1] = 0;
203 archdir[0].qid.vers++;
210 * alloc some io port space and remember who it was
211 * alloced to. if port < 0, find a free region.
214 ioalloc(int port, int size, int align, char *tag)
221 /* find a free port above 0x400 and below 0x1000 */
223 for(l = &iomap.m; *l; l = &(*l)->next){
225 if (m->start < 0x400) continue;
230 port = ((port+align-1)/align)*align;
239 /* Only 64KB I/O space on the x86. */
240 if((port+size) > 0x10000){
244 /* see if the space clashes with previously allocated ports */
245 for(l = &iomap.m; *l; l = &(*l)->next){
249 if(m->reserved && m->start == port && m->end >= port + size) {
254 if(m->start >= port+size)
262 print("ioalloc: out of maps");
266 iomap.free = m->next;
269 m->end = port + size;
270 strncpy(m->tag, tag, sizeof(m->tag)-1);
271 m->tag[sizeof(m->tag)-1] = 0;
274 archdir[0].qid.vers++;
286 for(l = &iomap.m; *l; l = &(*l)->next){
287 if((*l)->start == port){
290 m->next = iomap.free;
294 if((*l)->start > port)
297 archdir[0].qid.vers++;
302 iounused(int start, int end)
306 for(m = iomap.m; m; m = m->next){
307 if(start >= m->start && start < m->end
308 || start <= m->start && end > m->start)
315 checkport(int start, int end)
317 /* standard vga regs are OK */
318 if(start >= 0x2b0 && end <= 0x2df+1)
320 if(start >= 0x3c0 && end <= 0x3da+1)
323 if(iounused(start, end))
329 archattach(char* spec)
331 return devattach('P', spec);
335 archwalk(Chan* c, Chan *nc, char** name, int nname)
337 return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
341 archstat(Chan* c, uchar* dp, int n)
343 return devstat(c, dp, n, archdir, narchdir, devgen);
347 archopen(Chan* c, int omode)
349 return devopen(c, omode, archdir, narchdir, devgen);
363 archread(Chan *c, void *a, long n, vlong offset)
373 switch((ulong)c->qid.path){
376 return devdirread(c, a, n, archdir, narchdir, devgen);
380 checkport(offset, offset+n);
381 for(p = a; port < offset+n; port++)
388 checkport(offset, offset+n);
390 for(port = offset; port < offset+n; port += 2)
397 checkport(offset, offset+n);
399 for(port = offset; port < offset+n; port += 4)
407 for(port = offset; port < offset+n; port += 8)
408 if(rdmsr(port, vp++) < 0)
418 for(port = offset; port < offset+n; port++){
419 if((v = ecread(port)) < 0)
429 if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
430 return fn(c, a, n, offset);
435 if((buf = malloc(n)) == nil)
439 offset = offset/Linelen;
442 for(m = iomap.m; n > 0 && m != nil; m = m->next){
445 sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
459 archwrite(Chan *c, void *a, long n, vlong offset)
468 switch((ulong)c->qid.path){
472 checkport(offset, offset+n);
473 for(port = offset; port < offset+n; port++)
480 checkport(offset, offset+n);
482 for(port = offset; port < offset+n; port += 2)
489 checkport(offset, offset+n);
491 for(port = offset; port < offset+n; port += 4)
499 for(port = offset; port < offset+n; port += 8)
500 if(wrmsr(port, *vp++) < 0)
508 for(port = offset; port < offset+n; port++)
509 if(ecwrite(port, *p++) < 0)
514 if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
515 return fn(c, a, n, offset);
544 * the following is a generic version of the
545 * architecture specific stuff
565 * Often the BIOS hangs during restart if a conventional 8042
566 * warm-boot sequence is tried. The following is Intel specific and
567 * seems to perform a cold-boot, but at least it comes back.
568 * And sometimes there is no keyboard...
570 * The reset register (0xcf9) is usually in one of the bridge
571 * chips. The actual location and sequence could be extracted from
572 * ACPI but why bother, this is the end of the line anyway.
574 print("Takes a licking and keeps on ticking...\n");
575 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
584 * 386 has no compare-and-swap instruction.
585 * Run it with interrupts turned off instead.
588 cmpswap386(long *addr, long old, long new)
593 if(r = (*addr == old))
600 * On a uniprocessor, you'd think that coherence could be nop,
601 * but it can't. We still need a barrier when using coherence() in
604 * On VMware, it's safe (and a huge win) to set this to nop.
605 * Aux/vmware does this via the #P/archctl file.
607 void (*coherence)(void) = nop;
609 int (*cmpswap)(long*, long, long) = cmpswap386;
612 extern PCArch* knownarch[];
614 PCArch archgeneric = {
618 .serialpower= unimplemented,
619 .modempower= unimplemented,
621 .intrinit= i8259init,
622 .intrenable= i8259enable,
623 .intrvecno= i8259vecno,
624 .intrdisable= i8259disable,
628 .clockenable= i8253enable,
629 .fastclock= i8253read,
630 .timerset= i8253timerset,
633 typedef struct X86type X86type;
641 static X86type x86intel[] =
643 { 4, 0, 22, "486DX", }, /* known chips */
644 { 4, 1, 22, "486DX50", },
645 { 4, 2, 22, "486SX", },
646 { 4, 3, 22, "486DX2", },
647 { 4, 4, 22, "486SL", },
648 { 4, 5, 22, "486SX2", },
649 { 4, 7, 22, "DX2WB", }, /* P24D */
650 { 4, 8, 22, "DX4", }, /* P24C */
651 { 4, 9, 22, "DX4WB", }, /* P24CT */
654 { 5, 2, 23, "P54C", },
655 { 5, 3, 23, "P24T", },
656 { 5, 4, 23, "P55C MMX", },
657 { 5, 7, 23, "P54C VRT", },
658 { 6, 1, 16, "PentiumPro", },/* trial and error */
659 { 6, 3, 16, "PentiumII", },
660 { 6, 5, 16, "PentiumII/Xeon", },
661 { 6, 6, 16, "Celeron", },
662 { 6, 7, 16, "PentiumIII/Xeon", },
663 { 6, 8, 16, "PentiumIII/Xeon", },
664 { 6, 0xB, 16, "PentiumIII/Xeon", },
665 { 6, 0xF, 16, "Xeon5000-series", },
666 { 6, 0x16, 16, "Celeron", },
667 { 6, 0x17, 16, "Core 2/Xeon", },
668 { 6, 0x1A, 16, "Core i7/Xeon", },
669 { 6, 0x1C, 16, "Atom", },
670 { 6, 0x1D, 16, "Xeon MP", },
671 { 0xF, 1, 16, "P4", }, /* P4 */
672 { 0xF, 2, 16, "PentiumIV/Xeon", },
673 { 0xF, 6, 16, "PentiumIV/Xeon", },
675 { 3, -1, 32, "386", }, /* family defaults */
676 { 4, -1, 22, "486", },
677 { 5, -1, 23, "P5", },
678 { 6, -1, 16, "P6", },
679 { 0xF, -1, 16, "P4", }, /* P4 */
681 { -1, -1, 16, "unknown", }, /* total default */
685 * The AMD processors all implement the CPUID instruction.
686 * The later ones also return the processor name via functions
687 * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
689 * K5 "AMD-K5(tm) Processor"
690 * K6 "AMD-K6tm w/ multimedia extensions"
691 * K6 3D "AMD-K6(tm) 3D processor"
694 static X86type x86amd[] =
696 { 5, 0, 23, "AMD-K5", }, /* guesswork */
697 { 5, 1, 23, "AMD-K5", }, /* guesswork */
698 { 5, 2, 23, "AMD-K5", }, /* guesswork */
699 { 5, 3, 23, "AMD-K5", }, /* guesswork */
700 { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
701 { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
702 { 5, 6, 11, "AMD-K6", }, /* trial and error */
703 { 5, 7, 11, "AMD-K6", }, /* trial and error */
704 { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
705 { 5, 9, 11, "AMD-K6-III", },/* trial and error */
706 { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
708 { 6, 1, 11, "AMD-Athlon", },/* trial and error */
709 { 6, 2, 11, "AMD-Athlon", },/* trial and error */
711 { 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
713 { 4, -1, 22, "Am486", }, /* guesswork */
714 { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
715 { 6, -1, 11, "AMD-Athlon", },/* guesswork */
716 { 0xF, -1, 11, "AMD-K8", }, /* guesswork */
717 { 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
719 { -1, -1, 11, "unknown", }, /* total default */
725 static X86type x86winchip[] =
727 {5, 4, 23, "Winchip",}, /* guesswork */
728 {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
729 {6, 8, 23, "Via C3 Ezra-T",},
730 {6, 9, 23, "Via C3 Eden-N",},
731 { -1, -1, 23, "unknown", }, /* total default */
737 static X86type x86sis[] =
739 {5, 0, 23, "SiS 55x",}, /* guesswork */
740 { -1, -1, 23, "unknown", }, /* total default */
743 static X86type *cputype;
745 static void simplecycles(uvlong*);
746 void (*cycles)(uvlong*) = simplecycles;
747 void _cycles(uvlong*); /* in l.s */
750 simplecycles(uvlong*x)
761 i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
763 i += sprint(buf+i, "%12.12s ", m->cpuidid);
764 seprint(buf+i, buf + sizeof buf - 1,
765 "%s (cpuid: AX 0x%4.4uX CX 0x%4.4uX DX 0x%4.4uX)\n",
766 m->cpuidtype, m->cpuidax, m->cpuidcx, m->cpuiddx);
773 * - whether or not we have a TSC (cycle counter)
774 * - whether or not it supports page size extensions
776 * - whether or not it supports machine check exceptions
778 * - whether or not it supports the page global flag
785 int family, model, nomce;
791 cpuid(Highstdfunc, regs);
792 memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
793 memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
794 memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
795 m->cpuidid[12] = '\0';
797 cpuid(Procsig, regs);
798 m->cpuidax = regs[0];
799 m->cpuidcx = regs[2];
800 m->cpuiddx = regs[3];
802 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
803 strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
805 else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
807 else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
812 family = X86FAMILY(m->cpuidax);
813 model = X86MODEL(m->cpuidax);
814 for(t=tab; t->name; t++)
815 if((t->family == family && t->model == model)
816 || (t->family == family && t->model == -1)
817 || (t->family == -1))
820 m->cpuidtype = t->name;
823 * if there is one, set tsc to a known value
825 if(m->cpuiddx & Tsc){
828 if(m->cpuiddx & Cpumsr)
834 * use i8253 to guess our cpu speed
836 guesscpuhz(t->aalcycles);
839 * If machine check exception, page size extensions or page global bit
840 * are supported enable them in CR4 and clear any other set extensions.
841 * If machine check was enabled clear out any lingering status.
843 if(m->cpuiddx & (Pge|Mce|Pse)){
846 cr4 |= 0x10; /* page size extensions */
847 if(p = getconf("*nomce"))
848 nomce = strtoul(p, 0, 0);
851 if((m->cpuiddx & Mce) != 0 && !nomce){
852 if((m->cpuiddx & Mca) != 0){
860 wrmsr(0x17B, ~0ULL); /* enable all mca features */
866 /* init MCi .. MC1 (except MC0) */
868 wrmsr(0x400 + bank*4, ~0ULL);
869 wrmsr(0x401 + bank*4, 0);
872 if(family != 6 || model >= 0x1A)
877 else if(family == 5){
881 cr4 |= 0x40; /* machine check enable */
885 * Detect whether the chip supports the global bit
886 * in page directory and page table entries. When set
887 * in a particular entry, it means ``don't bother removing
888 * this from the TLB when CR3 changes.''
890 * We flag all kernel pages with this bit. Doing so lessens the
891 * overhead of switching processes on bare hardware,
892 * even more so on VMware. See mmu.c:/^memglobal.
894 * For future reference, should we ever need to do a
895 * full TLB flush, it can be accomplished by clearing
896 * the PGE bit in CR4, writing to CR3, and then
897 * restoring the PGE bit.
899 if(m->cpuiddx & Pge){
900 cr4 |= 0x80; /* page global enable bit */
906 if((m->cpuiddx & (Mca|Mce)) == Mce)
910 if(m->cpuiddx & Mtrr)
913 if(m->cpuiddx & Fxsr){ /* have sse fp? */
915 fprestore = fpsserestore;
916 putcr4(getcr4() | CR4Osfxsr|CR4Oxmmex);
919 fprestore = fpx87restore;
927 cputyperead(Chan*, void *a, long n, vlong offset)
932 mhz = (m->cpuhz+999999)/1000000;
934 snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
935 return readstr(offset, a, n, str);
939 archctlread(Chan*, void *a, long nn, vlong offset)
944 p = buf = smalloc(READSTR);
946 p = seprint(p, ep, "cpu %s %lud%s\n",
947 cputype->name, (ulong)(m->cpuhz+999999)/1000000,
948 m->havepge ? " pge" : "");
949 p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
950 p = seprint(p, ep, "coherence ");
951 if(coherence == mb386)
952 p = seprint(p, ep, "mb386\n");
953 else if(coherence == mb586)
954 p = seprint(p, ep, "mb586\n");
955 else if(coherence == mfence)
956 p = seprint(p, ep, "mfence\n");
957 else if(coherence == nop)
958 p = seprint(p, ep, "nop\n");
960 p = seprint(p, ep, "0x%p\n", coherence);
961 p = seprint(p, ep, "cmpswap ");
962 if(cmpswap == cmpswap386)
963 p = seprint(p, ep, "cmpswap386\n");
964 else if(cmpswap == cmpswap486)
965 p = seprint(p, ep, "cmpswap486\n");
967 p = seprint(p, ep, "0x%p\n", cmpswap);
968 p = seprint(p, ep, "i8253set %s\n", doi8253set ? "on" : "off");
970 n += mtrrprint(p, ep - p);
973 n = readstr(offset, a, nn, buf);
986 static Cmdtab archctlmsg[] =
989 CMcoherence, "coherence", 2,
990 CMi8253set, "i8253set", 2,
995 archctlwrite(Chan*, void *a, long n, vlong)
1002 cb = parsecmd(a, n);
1007 ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
1011 error("processor does not support pge");
1012 if(strcmp(cb->f[1], "on") == 0)
1013 putcr4(getcr4() | 0x80);
1014 else if(strcmp(cb->f[1], "off") == 0)
1015 putcr4(getcr4() & ~0x80);
1017 cmderror(cb, "invalid pge ctl");
1020 if(strcmp(cb->f[1], "mb386") == 0)
1022 else if(strcmp(cb->f[1], "mb586") == 0){
1023 if(X86FAMILY(m->cpuidax) < 5)
1024 error("invalid coherence ctl on this cpu family");
1026 }else if(strcmp(cb->f[1], "mfence") == 0){
1027 if((m->cpuiddx & Sse2) == 0)
1028 error("invalid coherence ctl on this cpu family");
1030 }else if(strcmp(cb->f[1], "nop") == 0){
1031 /* only safe on vmware */
1033 error("cannot disable coherence on a multiprocessor");
1036 cmderror(cb, "invalid coherence ctl");
1039 if(strcmp(cb->f[1], "on") == 0)
1041 else if(strcmp(cb->f[1], "off") == 0){
1043 (*arch->timerset)(0);
1045 cmderror(cb, "invalid i2853set ctl");
1048 base = strtoull(cb->f[1], &ep, 0);
1050 error("cache: parse error: base not a number?");
1051 size = strtoull(cb->f[2], &ep, 0);
1053 error("cache: parse error: size not a number?");
1054 ep = mtrr(base, size, cb->f[3]);
1065 rmemrw(int isr, void *a, long n, vlong off)
1069 if(off < 0 || n < 0)
1070 error("bad offset/count");
1076 memmove(a, KADDR(addr), n);
1078 /* allow vga framebuf's write access */
1079 if(addr >= MB || addr+n > MB ||
1080 (addr < 0xA0000 || addr+n > 0xB0000+0x10000))
1081 error("bad offset/count in write");
1082 memmove(KADDR(addr), a, n);
1088 rmemread(Chan*, void *a, long n, vlong off)
1090 return rmemrw(1, a, n, off);
1094 rmemwrite(Chan*, void *a, long n, vlong off)
1096 return rmemrw(0, a, n, off);
1105 for(p = knownarch; *p; p++){
1106 if((*p)->ident && (*p)->ident() == 0){
1112 arch = &archgeneric;
1115 arch->id = archgeneric.id;
1116 if(arch->reset == 0)
1117 arch->reset = archgeneric.reset;
1118 if(arch->serialpower == 0)
1119 arch->serialpower = archgeneric.serialpower;
1120 if(arch->modempower == 0)
1121 arch->modempower = archgeneric.modempower;
1122 if(arch->intrinit == 0)
1123 arch->intrinit = archgeneric.intrinit;
1124 if(arch->intrenable == 0)
1125 arch->intrenable = archgeneric.intrenable;
1129 * Decide whether to use copy-on-reference (386 and mp).
1130 * We get another chance to set it in mpinit() for a
1133 if(X86FAMILY(m->cpuidax) == 3)
1136 if(X86FAMILY(m->cpuidax) >= 4)
1137 cmpswap = cmpswap486;
1139 if(X86FAMILY(m->cpuidax) >= 5)
1142 if(m->cpuiddx & Sse2)
1145 addarchfile("cputype", 0444, cputyperead, nil);
1146 addarchfile("archctl", 0664, archctlread, archctlwrite);
1147 addarchfile("realmodemem", 0660, rmemread, rmemwrite);
1151 * call either the pcmcia or pccard device setup
1154 pcmspecial(char *idstr, ISAConf *isa)
1156 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
1160 * call either the pcmcia or pccard device teardown
1163 pcmspecialclose(int a)
1165 if (_pcmspecialclose != nil)
1166 _pcmspecialclose(a);
1170 * return value and speed of timer set in arch->clockenable
1173 fastticks(uvlong *hz)
1175 return (*arch->fastclock)(hz);
1181 return fastticks2us((*arch->fastclock)(nil));
1185 * set next timer interrupt
1191 (*arch->timerset)(x);
1195 * put the processor in the halt state if we've no processes to run.
1196 * an interrupt will get us going again.
1198 * halting in an smp system can result in a startup latency for
1199 * processes that become ready.
1200 * if idle_spin is zero, we care more about saving energy
1201 * than reducing this latency.
1203 * the performance loss with idle_spin == 0 seems to be slight
1204 * and it reduces lock contention (thus system time and real time)
1205 * on many-core systems with large values of NPROC.
1210 extern int nrdy, idle_spin;
1214 else if(m->cpuidcx & Monitor)
1216 else if(idle_spin == 0)
1221 isaconfig(char *class, int ctlrno, ISAConf *isa)
1226 snprint(cc, sizeof cc, "%s%d", class, ctlrno);
1232 isa->nopt = tokenize(p, isa->opt, NISAOPT);
1233 for(i = 0; i < isa->nopt; i++){
1235 if(cistrncmp(p, "type=", 5) == 0)
1237 else if(cistrncmp(p, "port=", 5) == 0)
1238 isa->port = strtoul(p+5, &p, 0);
1239 else if(cistrncmp(p, "irq=", 4) == 0)
1240 isa->irq = strtoul(p+4, &p, 0);
1241 else if(cistrncmp(p, "dma=", 4) == 0)
1242 isa->dma = strtoul(p+4, &p, 0);
1243 else if(cistrncmp(p, "mem=", 4) == 0)
1244 isa->mem = strtoul(p+4, &p, 0);
1245 else if(cistrncmp(p, "size=", 5) == 0)
1246 isa->size = strtoul(p+5, &p, 0);
1247 else if(cistrncmp(p, "freq=", 5) == 0)
1248 isa->freq = strtoul(p+5, &p, 0);
1259 if((m->cpuiddx & (Mce|Cpumsr)) != (Mce|Cpumsr))
1261 if((m->cpuiddx & Mca) == 0){
1264 iprint("MCA %8.8llux MCT %8.8llux\n", v, w);
1269 iprint("MCG CAP %.16llux STATUS %.16llux\n", v, w);
1275 rdmsr(0x401 + bank*4, &v);
1276 if((v & (1ull << 63)) == 0)
1278 iprint("MC%d STATUS %.16llux", bank, v);
1279 if(v & (1ull << 58)){
1280 rdmsr(0x402 + bank*4, &w);
1281 iprint(" ADDR %.16llux", w);
1283 if(v & (1ull << 59)){
1284 rdmsr(0x403 + bank*4, &w);
1285 iprint(" MISC %.16llux", w);