2 #include "../port/lib.h"
8 #include "../port/error.h"
10 typedef struct IOMap IOMap;
25 IOMap maps[32]; /* some initial free maps */
27 QLock ql; /* lock for reading map */
47 enum { /* cpuid standard function codes */
48 Highstdfunc = 0, /* also returns vendor string */
53 Highextfunc = 0x80000000,
57 typedef long Rdwrfn(Chan*, void*, long, vlong);
59 static Rdwrfn *readfn[Qmax];
60 static Rdwrfn *writefn[Qmax];
62 static Dirtab archdir[Qmax] = {
63 ".", { Qdir, 0, QTDIR }, 0, 0555,
64 "ioalloc", { Qioalloc, 0 }, 0, 0444,
65 "iob", { Qiob, 0 }, 0, 0660,
66 "iow", { Qiow, 0 }, 0, 0660,
67 "iol", { Qiol, 0 }, 0, 0660,
68 "msr", { Qmsr, 0 }, 0, 0660,
70 Lock archwlock; /* the lock is only for changing archdir */
72 int (*_pcmspecial)(char*, ISAConf*);
73 void (*_pcmspecialclose)(int);
76 * Add a file to the #P listing. Once added, you can't delete it.
77 * You can't add a file with the same name as one already there,
78 * and you get a pointer to the Dirtab entry so you can do things
79 * like change the Qid version. Changing the Qid path is disallowed.
82 addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
88 memset(&d, 0, sizeof d);
95 print("addarchfile: out of entries for %s\n", name);
99 for(i=0; i<narchdir; i++)
100 if(strcmp(archdir[i].name, name) == 0){
105 d.qid.path = narchdir;
106 archdir[narchdir] = d;
107 readfn[narchdir] = rdfn;
108 writefn[narchdir] = wrfn;
109 dp = &archdir[narchdir++];
121 for(i = 0; i < nelem(iomap.maps)-1; i++)
122 iomap.maps[i].next = &iomap.maps[i+1];
123 iomap.maps[i].next = nil;
124 iomap.free = iomap.maps;
127 * This is necessary to make the IBM X20 boot.
128 * Have not tracked down the reason.
129 * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
131 ioalloc(0x0fff, 1, 0, "dummy");
133 if ((excluded = getconf("ioexclude")) != nil) {
137 while (s && *s != '\0' && *s != '\n') {
141 io_s = (int)strtol(s, &ends, 0);
142 if (ends == nil || ends == s || *ends != '-') {
143 print("ioinit: cannot parse option string\n");
148 io_e = (int)strtol(s, &ends, 0);
149 if (ends && *ends == ',')
153 ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
160 * Reserve a range to be ioalloced later.
161 * This is in particular useful for exchangable cards, such
162 * as pcmcia and cardbus cards.
165 ioreserve(int, int size, int align, char *tag)
171 /* find a free port above 0x400 and below 0x1000 */
173 for(l = &iomap.m; *l; l = &(*l)->next){
175 if (m->start < 0x400) continue;
180 port = ((port+align-1)/align)*align;
190 print("ioalloc: out of maps");
194 iomap.free = m->next;
197 m->end = port + size;
199 strncpy(m->tag, tag, sizeof(m->tag)-1);
200 m->tag[sizeof(m->tag)-1] = 0;
203 archdir[0].qid.vers++;
210 * alloc some io port space and remember who it was
211 * alloced to. if port < 0, find a free region.
214 ioalloc(int port, int size, int align, char *tag)
221 /* find a free port above 0x400 and below 0x1000 */
223 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
224 if (m->start < 0x400) continue;
229 port = ((port+align-1)/align)*align;
238 /* Only 64KB I/O space on the x86. */
239 if((port+size) > 0x10000){
243 /* see if the space clashes with previously allocated ports */
244 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
247 if(m->reserved && m->start == port && m->end >= port + size) {
252 if(m->start >= port+size)
260 print("ioalloc: out of maps");
264 iomap.free = m->next;
267 m->end = port + size;
268 strncpy(m->tag, tag, sizeof(m->tag)-1);
269 m->tag[sizeof(m->tag)-1] = 0;
272 archdir[0].qid.vers++;
284 for(l = &iomap.m; (m = *l) != nil; l = &m->next){
285 if(m->start == port){
287 m->next = iomap.free;
294 archdir[0].qid.vers++;
299 iounused(int start, int end)
303 for(m = iomap.m; m != nil; m = m->next){
304 if(start >= m->start && start < m->end
305 || start <= m->start && end > m->start)
312 checkport(uint start, uint end)
314 if(end < start || end > 0x10000)
317 /* standard vga regs are OK */
318 if(start >= 0x2b0 && end <= 0x2df+1)
320 if(start >= 0x3c0 && end <= 0x3da+1)
323 if(iounused(start, end))
329 archattach(char* spec)
331 return devattach('P', spec);
335 archwalk(Chan* c, Chan *nc, char** name, int nname)
337 return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
341 archstat(Chan* c, uchar* dp, int n)
343 return devstat(c, dp, n, archdir, narchdir, devgen);
347 archopen(Chan* c, int omode)
349 return devopen(c, omode, archdir, narchdir, devgen);
358 archread(Chan *c, void *a, long n, vlong offset)
371 switch((ulong)c->qid.path){
373 return devdirread(c, a, n, archdir, narchdir, devgen);
376 checkport(port, end);
377 for(p = a; port < end; port++)
384 checkport(port, end);
385 for(sp = a; port < end; port += 2)
392 checkport(port, end);
393 for(lp = a; port < end; port += 4)
400 if((uint)n/8 > -port)
403 for(vp = a; port != end; port++)
404 if(rdmsr(port, vp++) < 0)
411 for(m = iomap.m; m != nil; m = m->next){
412 i = snprint(buf, sizeof(buf), "%8lux %8lux %-12.12s\n",
413 m->start, m->end-1, m->tag);
424 memmove(a, buf+offset, n);
428 if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
429 return fn(c, a, n, offset);
436 archwrite(Chan *c, void *a, long n, vlong offset)
447 switch((ulong)c->qid.path){
449 checkport(port, end);
450 for(p = a; port < end; port++)
457 checkport(port, end);
458 for(sp = a; port < end; port += 2)
465 checkport(port, end);
466 for(lp = a; port < end; port += 4)
473 if((uint)n/8 > -port)
476 for(vp = a; port != end; port++)
477 if(wrmsr(port, *vp++) < 0)
482 if(c->qid.path < narchdir && (fn = writefn[c->qid.path]) != nil)
483 return fn(c, a, n, offset);
512 * the following is a generic version of the
513 * architecture specific stuff
533 * Often the BIOS hangs during restart if a conventional 8042
534 * warm-boot sequence is tried. The following is Intel specific and
535 * seems to perform a cold-boot, but at least it comes back.
536 * And sometimes there is no keyboard...
538 * The reset register (0xcf9) is usually in one of the bridge
539 * chips. The actual location and sequence could be extracted from
540 * ACPI but why bother, this is the end of the line anyway.
542 print("Takes a licking and keeps on ticking...\n");
543 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
547 print("can't reset\n");
553 * 386 has no compare-and-swap instruction.
554 * Run it with interrupts turned off instead.
557 cmpswap386(long *addr, long old, long new)
562 if(r = (*addr == old))
569 * On a uniprocessor, you'd think that coherence could be nop,
570 * but it can't. We still need a barrier when using coherence() in
573 * On VMware, it's safe (and a huge win) to set this to nop.
574 * Aux/vmware does this via the #P/archctl file.
576 void (*coherence)(void) = nop;
578 int (*cmpswap)(long*, long, long) = cmpswap386;
581 extern PCArch* knownarch[];
583 PCArch archgeneric = {
587 .serialpower= unimplemented,
588 .modempower= unimplemented,
590 .intrinit= i8259init,
591 .intrenable= i8259enable,
592 .intrvecno= i8259vecno,
593 .intrdisable= i8259disable,
597 .clockenable= i8253enable,
598 .fastclock= i8253read,
599 .timerset= i8253timerset,
602 typedef struct X86type X86type;
610 static X86type x86intel[] =
612 { 4, 0, 22, "486DX", }, /* known chips */
613 { 4, 1, 22, "486DX50", },
614 { 4, 2, 22, "486SX", },
615 { 4, 3, 22, "486DX2", },
616 { 4, 4, 22, "486SL", },
617 { 4, 5, 22, "486SX2", },
618 { 4, 7, 22, "DX2WB", }, /* P24D */
619 { 4, 8, 22, "DX4", }, /* P24C */
620 { 4, 9, 22, "DX4WB", }, /* P24CT */
623 { 5, 2, 23, "P54C", },
624 { 5, 3, 23, "P24T", },
625 { 5, 4, 23, "P55C MMX", },
626 { 5, 7, 23, "P54C VRT", },
627 { 6, 1, 16, "PentiumPro", },/* trial and error */
628 { 6, 3, 16, "PentiumII", },
629 { 6, 5, 16, "PentiumII/Xeon", },
630 { 6, 6, 16, "Celeron", },
631 { 6, 7, 16, "PentiumIII/Xeon", },
632 { 6, 8, 16, "PentiumIII/Xeon", },
633 { 6, 0xB, 16, "PentiumIII/Xeon", },
634 { 6, 0xF, 16, "Xeon5000-series", },
635 { 6, 0x16, 16, "Celeron", },
636 { 6, 0x17, 16, "Core 2/Xeon", },
637 { 6, 0x1A, 16, "Core i7/Xeon", },
638 { 6, 0x1C, 16, "Atom", },
639 { 6, 0x1D, 16, "Xeon MP", },
640 { 0xF, 1, 16, "P4", }, /* P4 */
641 { 0xF, 2, 16, "PentiumIV/Xeon", },
642 { 0xF, 6, 16, "PentiumIV/Xeon", },
644 { 3, -1, 32, "386", }, /* family defaults */
645 { 4, -1, 22, "486", },
646 { 5, -1, 23, "P5", },
647 { 6, -1, 16, "P6", },
648 { 0xF, -1, 16, "P4", }, /* P4 */
650 { -1, -1, 16, "unknown", }, /* total default */
654 * The AMD processors all implement the CPUID instruction.
655 * The later ones also return the processor name via functions
656 * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
658 * K5 "AMD-K5(tm) Processor"
659 * K6 "AMD-K6tm w/ multimedia extensions"
660 * K6 3D "AMD-K6(tm) 3D processor"
663 static X86type x86amd[] =
665 { 5, 0, 23, "AMD-K5", }, /* guesswork */
666 { 5, 1, 23, "AMD-K5", }, /* guesswork */
667 { 5, 2, 23, "AMD-K5", }, /* guesswork */
668 { 5, 3, 23, "AMD-K5", }, /* guesswork */
669 { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
670 { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
671 { 5, 6, 11, "AMD-K6", }, /* trial and error */
672 { 5, 7, 11, "AMD-K6", }, /* trial and error */
673 { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
674 { 5, 9, 11, "AMD-K6-III", },/* trial and error */
675 { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
677 { 6, 1, 11, "AMD-Athlon", },/* trial and error */
678 { 6, 2, 11, "AMD-Athlon", },/* trial and error */
680 { 0x1F, 9, 11, "AMD-K10 Opteron G34", },/* guesswork */
682 { 4, -1, 22, "Am486", }, /* guesswork */
683 { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
684 { 6, -1, 11, "AMD-Athlon", },/* guesswork */
685 { 0xF, -1, 11, "AMD-K8", }, /* guesswork */
686 { 0x1F, -1, 11, "AMD-K10", }, /* guesswork */
687 { 23, 1, 13, "AMD Ryzen" },
689 { -1, -1, 11, "unknown", }, /* total default */
695 static X86type x86winchip[] =
697 {5, 4, 23, "Winchip",}, /* guesswork */
698 {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
699 {6, 8, 23, "Via C3 Ezra-T",},
700 {6, 9, 23, "Via C3 Eden-N",},
701 { -1, -1, 23, "unknown", }, /* total default */
707 static X86type x86sis[] =
709 {5, 0, 23, "SiS 55x",}, /* guesswork */
710 { -1, -1, 23, "unknown", }, /* total default */
713 static X86type *cputype;
715 static void simplecycles(uvlong*);
716 void (*cycles)(uvlong*) = simplecycles;
717 void _cycles(uvlong*); /* in l.s */
720 simplecycles(uvlong*x)
728 print("cpu%d: %dMHz %s %s (AX %8.8uX CX %8.8uX DX %8.8uX)\n",
729 m->machno, m->cpumhz, m->cpuidid, m->cpuidtype,
730 m->cpuidax, m->cpuidcx, m->cpuiddx);
736 * - whether or not we have a TSC (cycle counter)
737 * - whether or not it supports page size extensions
739 * - whether or not it supports machine check exceptions
741 * - whether or not it supports the page global flag
748 int family, model, nomce;
754 cpuid(Highstdfunc, regs);
755 memmove(m->cpuidid, ®s[1], BY2WD); /* bx */
756 memmove(m->cpuidid+4, ®s[3], BY2WD); /* dx */
757 memmove(m->cpuidid+8, ®s[2], BY2WD); /* cx */
758 m->cpuidid[12] = '\0';
760 cpuid(Procsig, regs);
761 m->cpuidax = regs[0];
762 m->cpuidcx = regs[2];
763 m->cpuiddx = regs[3];
765 m->cpuidfamily = m->cpuidax >> 8 & 0xf;
766 m->cpuidmodel = m->cpuidax >> 4 & 0xf;
767 m->cpuidstepping = m->cpuidax & 0xf;
768 switch(m->cpuidfamily){
770 m->cpuidfamily += m->cpuidax >> 20 & 0xff;
771 m->cpuidmodel += m->cpuidax >> 16 & 0xf;
774 m->cpuidmodel += m->cpuidax >> 16 & 0xf;
778 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
779 strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
781 else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
783 else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
788 family = m->cpuidfamily;
789 model = m->cpuidmodel;
790 for(t=tab; t->name; t++)
791 if((t->family == family && t->model == model)
792 || (t->family == family && t->model == -1)
793 || (t->family == -1))
796 m->cpuidtype = t->name;
799 * if there is one, set tsc to a known value
801 if(m->cpuiddx & Tsc){
804 if(m->cpuiddx & Cpumsr)
809 * use i8253 to guess our cpu speed
811 guesscpuhz(t->aalcycles);
814 * If machine check exception, page size extensions or page global bit
815 * are supported enable them in CR4 and clear any other set extensions.
816 * If machine check was enabled clear out any lingering status.
818 if(m->cpuiddx & (Pge|Mce|Pse)){
821 cr4 |= 0x10; /* page size extensions */
822 if(p = getconf("*nomce"))
823 nomce = strtoul(p, 0, 0);
826 if((m->cpuiddx & Mce) != 0 && !nomce){
827 if((m->cpuiddx & Mca) != 0){
835 wrmsr(0x17B, ~0ULL); /* enable all mca features */
841 /* init MCi .. MC1 (except MC0) */
843 wrmsr(0x400 + bank*4, ~0ULL);
844 wrmsr(0x401 + bank*4, 0);
847 if(family != 6 || model >= 0x1A)
852 else if(family == 5){
856 cr4 |= 0x40; /* machine check enable */
860 * Detect whether the chip supports the global bit
861 * in page directory and page table entries. When set
862 * in a particular entry, it means ``don't bother removing
863 * this from the TLB when CR3 changes.''
865 * We flag all kernel pages with this bit. Doing so lessens the
866 * overhead of switching processes on bare hardware,
867 * even more so on VMware. See mmu.c:/^memglobal.
869 * For future reference, should we ever need to do a
870 * full TLB flush, it can be accomplished by clearing
871 * the PGE bit in CR4, writing to CR3, and then
872 * restoring the PGE bit.
874 if(m->cpuiddx & Pge){
875 cr4 |= 0x80; /* page global enable bit */
881 if((m->cpuiddx & (Mca|Mce)) == Mce)
885 if(m->cpuiddx & Mtrr)
888 if((m->cpuiddx & (Sse|Fxsr)) == (Sse|Fxsr)){ /* have sse fp? */
890 fprestore = fpsserestore;
891 putcr4(getcr4() | CR4Osfxsr|CR4Oxmmex);
894 fprestore = fpx87restore;
897 if(strcmp(m->cpuidid, "GenuineIntel") == 0 && (m->cpuidcx & Rdrnd) != 0)
898 hwrandbuf = rdrandbuf;
902 if(sizeof(uintptr) == 8) {
903 /* 8-byte watchpoints are supported in Long Mode */
906 /* check and enable NX bit */
907 cpuid(Highextfunc, regs);
908 if(regs[0] >= Procextfeat){
909 cpuid(Procextfeat, regs);
910 if((regs[3] & (1<<20)) != 0){
913 /* enable no-execute feature */
914 if(rdmsr(Efer, &efer) != -1){
916 if(wrmsr(Efer, efer) != -1)
921 } else if(strcmp(m->cpuidid, "GenuineIntel") == 0){
922 /* some random CPUs that support 8-byte watchpoints */
923 if(family == 15 && (model == 3 || model == 4 || model == 6)
924 || family == 6 && (model == 15 || model == 23 || model == 28))
926 /* Intel SDM claims amd64 support implies 8-byte watchpoint support */
927 cpuid(Highextfunc, regs);
928 if(regs[0] >= Procextfeat){
929 cpuid(Procextfeat, regs);
930 if((regs[3] & 1<<29) != 0)
940 cputyperead(Chan*, void *a, long n, vlong offset)
945 mhz = (m->cpuhz+999999)/1000000;
947 snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
948 return readstr(offset, a, n, str);
952 archctlread(Chan*, void *a, long nn, vlong offset)
957 p = buf = smalloc(READSTR);
959 p = seprint(p, ep, "cpu %s %lud%s\n",
960 cputype->name, (ulong)(m->cpuhz+999999)/1000000,
961 m->havepge ? " pge" : "");
962 p = seprint(p, ep, "pge %s\n", getcr4()&0x80 ? "on" : "off");
963 p = seprint(p, ep, "coherence ");
964 if(coherence == mb386)
965 p = seprint(p, ep, "mb386\n");
966 else if(coherence == mb586)
967 p = seprint(p, ep, "mb586\n");
968 else if(coherence == mfence)
969 p = seprint(p, ep, "mfence\n");
970 else if(coherence == nop)
971 p = seprint(p, ep, "nop\n");
973 p = seprint(p, ep, "0x%p\n", coherence);
974 p = seprint(p, ep, "cmpswap ");
975 if(cmpswap == cmpswap386)
976 p = seprint(p, ep, "cmpswap386\n");
977 else if(cmpswap == cmpswap486)
978 p = seprint(p, ep, "cmpswap486\n");
980 p = seprint(p, ep, "0x%p\n", cmpswap);
981 p = seprint(p, ep, "arch %s\n", arch->id);
983 n += mtrrprint(p, ep - p);
986 n = readstr(offset, a, nn, buf);
998 static Cmdtab archctlmsg[] =
1001 CMcoherence, "coherence", 2,
1002 CMcache, "cache", 4,
1006 archctlwrite(Chan*, void *a, long n, vlong)
1013 cb = parsecmd(a, n);
1018 ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
1022 error("processor does not support pge");
1023 if(strcmp(cb->f[1], "on") == 0)
1024 putcr4(getcr4() | 0x80);
1025 else if(strcmp(cb->f[1], "off") == 0)
1026 putcr4(getcr4() & ~0x80);
1028 cmderror(cb, "invalid pge ctl");
1031 if(strcmp(cb->f[1], "mb386") == 0)
1033 else if(strcmp(cb->f[1], "mb586") == 0){
1034 if(m->cpuidfamily < 5)
1035 error("invalid coherence ctl on this cpu family");
1037 }else if(strcmp(cb->f[1], "mfence") == 0){
1038 if((m->cpuiddx & Sse2) == 0)
1039 error("invalid coherence ctl on this cpu family");
1041 }else if(strcmp(cb->f[1], "nop") == 0){
1042 /* only safe on vmware */
1044 error("cannot disable coherence on a multiprocessor");
1047 cmderror(cb, "invalid coherence ctl");
1050 base = strtoull(cb->f[1], &ep, 0);
1052 error("cache: parse error: base not a number?");
1053 size = strtoull(cb->f[2], &ep, 0);
1055 error("cache: parse error: size not a number?");
1056 ep = mtrr(base, size, cb->f[3]);
1067 rmemrw(int isr, void *a, long n, vlong off)
1071 if(off < 0 || n < 0)
1072 error("bad offset/count");
1078 memmove(a, KADDR(addr), n);
1080 /* allow vga framebuf's write access */
1081 if(addr >= MB || addr+n > MB ||
1082 (addr < 0xA0000 || addr+n > 0xB0000+0x10000))
1083 error("bad offset/count in write");
1084 memmove(KADDR(addr), a, n);
1090 rmemread(Chan*, void *a, long n, vlong off)
1092 return rmemrw(1, a, n, off);
1096 rmemwrite(Chan*, void *a, long n, vlong off)
1098 return rmemrw(0, a, n, off);
1106 arch = &archgeneric;
1107 for(p = knownarch; *p != nil; p++){
1108 if((*p)->ident != nil && (*p)->ident() == 0){
1113 if(arch != &archgeneric){
1115 arch->id = archgeneric.id;
1116 if(arch->reset == nil)
1117 arch->reset = archgeneric.reset;
1118 if(arch->serialpower == nil)
1119 arch->serialpower = archgeneric.serialpower;
1120 if(arch->modempower == nil)
1121 arch->modempower = archgeneric.modempower;
1122 if(arch->intrinit == nil)
1123 arch->intrinit = archgeneric.intrinit;
1124 if(arch->intrenable == nil)
1125 arch->intrenable = archgeneric.intrenable;
1129 * Decide whether to use copy-on-reference (386 and mp).
1130 * We get another chance to set it in mpinit() for a
1133 if(m->cpuidfamily == 3)
1136 if(m->cpuidfamily >= 4)
1137 cmpswap = cmpswap486;
1139 if(m->cpuidfamily >= 5)
1142 if(m->cpuiddx & Sse2)
1145 addarchfile("cputype", 0444, cputyperead, nil);
1146 addarchfile("archctl", 0664, archctlread, archctlwrite);
1147 addarchfile("realmodemem", 0660, rmemread, rmemwrite);
1151 * call either the pcmcia or pccard device setup
1154 pcmspecial(char *idstr, ISAConf *isa)
1156 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
1160 * call either the pcmcia or pccard device teardown
1163 pcmspecialclose(int a)
1165 if (_pcmspecialclose != nil)
1166 _pcmspecialclose(a);
1170 * return value and speed of timer set in arch->clockenable
1173 fastticks(uvlong *hz)
1175 return (*arch->fastclock)(hz);
1181 return fastticks2us((*arch->fastclock)(nil));
1185 * set next timer interrupt
1190 (*arch->timerset)(x);
1194 * put the processor in the halt state if we've no processes to run.
1195 * an interrupt will get us going again.
1197 * halting in an smp system can result in a startup latency for
1198 * processes that become ready.
1199 * if idle_spin is zero, we care more about saving energy
1200 * than reducing this latency.
1202 * the performance loss with idle_spin == 0 seems to be slight
1203 * and it reduces lock contention (thus system time and real time)
1204 * on many-core systems with large values of NPROC.
1209 extern int nrdy, idle_spin;
1213 else if(m->cpuidcx & Monitor)
1215 else if(idle_spin == 0)
1220 isaconfig(char *class, int ctlrno, ISAConf *isa)
1222 char cc[32], *p, *x;
1225 snprint(cc, sizeof cc, "%s%d", class, ctlrno);
1235 isa->nopt = tokenize(p, isa->opt, NISAOPT);
1236 for(i = 0; i < isa->nopt; i++){
1238 if(cistrncmp(p, "type=", 5) == 0)
1240 else if(cistrncmp(p, "port=", 5) == 0)
1241 isa->port = strtoul(p+5, &p, 0);
1242 else if(cistrncmp(p, "irq=", 4) == 0)
1243 isa->irq = strtoul(p+4, &p, 0);
1244 else if(cistrncmp(p, "dma=", 4) == 0)
1245 isa->dma = strtoul(p+4, &p, 0);
1246 else if(cistrncmp(p, "mem=", 4) == 0)
1247 isa->mem = strtoul(p+4, &p, 0);
1248 else if(cistrncmp(p, "size=", 5) == 0)
1249 isa->size = strtoul(p+5, &p, 0);
1250 else if(cistrncmp(p, "freq=", 5) == 0)
1251 isa->freq = strtoul(p+5, &p, 0);
1262 if((m->cpuiddx & (Mce|Cpumsr)) != (Mce|Cpumsr))
1264 if((m->cpuiddx & Mca) == 0){
1267 iprint("MCA %8.8llux MCT %8.8llux\n", v, w);
1272 iprint("MCG CAP %.16llux STATUS %.16llux\n", v, w);
1278 rdmsr(0x401 + bank*4, &v);
1279 if((v & (1ull << 63)) == 0)
1281 iprint("MC%d STATUS %.16llux", bank, v);
1282 if(v & (1ull << 58)){
1283 rdmsr(0x402 + bank*4, &w);
1284 iprint(" ADDR %.16llux", w);
1286 if(v & (1ull << 59)){
1287 rdmsr(0x403 + bank*4, &w);
1288 iprint(" MISC %.16llux", w);
1295 setupwatchpts(Proc *pr, Watchpt *wp, int nwp)
1302 error("there are four watchpoints.");
1304 memset(pr->dr, 0, sizeof(pr->dr));
1307 for(p = wp; p < wp + nwp; p++){
1309 case WATCHRD|WATCHWR: case WATCHWR:
1313 error("length must be 1 on breakpoints");
1316 error("type must be rw-, -w- or --x");
1319 case 1: case 2: case 4:
1322 if(m->havewatchpt8) break;
1324 error(m->havewatchpt8 ? "length must be 1,2,4,8" : "length must be 1,2,4");
1326 if((p->addr & p->len - 1) != 0)
1327 error("address must be aligned according to length");
1330 memset(pr->dr, 0, sizeof(pr->dr));
1331 pr->dr[6] = 0xffff8ff0;
1332 for(i = 0; i < nwp; i++){
1333 pr->dr[i] = wp[i].addr;
1335 case WATCHRD|WATCHWR: cfg = 3; break;
1336 case WATCHWR: cfg = 1; break;
1337 case WATCHEX: cfg = 0; break;
1342 case 2: cfg |= 4; break;
1343 case 4: cfg |= 12; break;
1344 case 8: cfg |= 8; break;
1347 pr->dr[7] |= cfg << 16 + 4 * i;
1348 pr->dr[7] |= 1 << 2 * i + 1;