1 typedef struct BIOS32si BIOS32si;
2 typedef struct BIOS32ci BIOS32ci;
3 typedef struct Conf Conf;
4 typedef struct Confmem Confmem;
5 typedef struct FPsave FPsave;
6 typedef struct ISAConf ISAConf;
7 typedef struct Label Label;
8 typedef struct Lock Lock;
9 typedef struct MMU MMU;
10 typedef struct Mach Mach;
11 typedef struct Notsave Notsave;
12 typedef struct PCArch PCArch;
13 typedef struct Pcidev Pcidev;
14 typedef struct PCMmap PCMmap;
15 typedef struct PCMslot PCMslot;
16 typedef struct Page Page;
17 typedef struct PMMU PMMU;
18 typedef struct Proc Proc;
19 typedef struct Segdesc Segdesc;
21 typedef struct Ureg Ureg;
22 typedef struct Vctl Vctl;
24 #pragma incomplete BIOS32si
25 #pragma incomplete Pcidev
26 #pragma incomplete Ureg
28 #define MAXSYSARG 5 /* for mount(fd, afd, mpt, flag, arg) */
31 * parameters for sysproc.c
33 #define AOUT_MAGIC (I_MAGIC)
63 /* the following is a bit that can be or'd into the state */
81 uchar regs[80]; /* floating point registers */
94 ulong nmach; /* processors */
95 ulong nproc; /* processes */
96 ulong monitor; /* has monitor? */
97 Confmem mem[4]; /* physical memory */
98 ulong npage; /* total physical pages of memory */
99 ulong upages; /* user page pool */
100 ulong nimage; /* number of page cache image headers */
101 ulong nswap; /* number of swap pages */
102 int nswppo; /* max # of pageouts per segment pass */
103 ulong base0; /* base of bank 0 */
104 ulong base1; /* base of bank 1 */
105 ulong copymode; /* 0 is copy on write, 1 is copy on reference */
106 ulong ialloc; /* max interrupt time allocation in bytes */
107 ulong pipeqsize; /* size in bytes of pipe queues */
108 int nuart; /* number of uart devices */
123 Page* mmupdb; /* page directory base */
124 Page* mmufree; /* unused page table pages */
125 Page* mmuused; /* used page table pages */
126 Page* kmaptable; /* page table used by kmap */
127 uint lastkmap; /* last entry used by kmap */
128 int nkmap; /* number of current kmaps */
130 Segdesc gdt[NPROCSEG]; /* per process descriptors */
131 Segdesc *ldt; /* local descriptor table */
132 int nldt; /* number of ldt descriptors allocated */
136 * things saved in the Proc structure during a notify
145 #include "../port/portdat.h"
148 ulong link; /* link (old TSS selector) */
149 ulong esp0; /* privilege level 0 stack pointer */
150 ulong ss0; /* privilege level 0 stack selector */
151 ulong esp1; /* privilege level 1 stack pointer */
152 ulong ss1; /* privilege level 1 stack selector */
153 ulong esp2; /* privilege level 2 stack pointer */
154 ulong ss2; /* privilege level 2 stack selector */
155 ulong xcr3; /* page directory base register - not used because we don't use trap gates */
156 ulong eip; /* instruction pointer */
157 ulong eflags; /* flags register */
158 ulong eax; /* general registers */
166 ulong es; /* segment selectors */
172 ulong ldt; /* selector for task's LDT */
173 ulong iomap; /* I/O map base address + T-bit */
178 int machno; /* physical id of processor (KNOWN TO ASSEMBLY) */
179 ulong splpc; /* pc of last caller to splhi */
181 ulong* pdb; /* page directory base for this processor (va) */
182 Tss* tss; /* tss for this processor */
183 Segdesc *gdt; /* gdt for this processor */
185 Proc* proc; /* current process on this processor */
186 Proc* externup; /* extern register Proc *up */
191 ulong ticks; /* of the clock since boot time */
192 Label sched; /* scheduler wakeup */
193 Lock alarmlock; /* access to alarm list */
194 void* alarm; /* alarms bound to this clock */
197 Proc* readied; /* for runproc */
198 ulong schedticks; /* next forced context switch */
207 int flushmmu; /* make current proc flush it's mmu state */
209 Perf perf; /* performance counters */
218 uvlong cyclefreq; /* Frequency of user readable cycle counter */
234 vlong mtrrvar[32]; /* 256 max. */
240 * KMap the structure doesn't exist, but the functions do.
242 typedef struct KMap KMap;
243 #define VA(k) ((void*)(k))
250 int machs; /* bitmap of active CPUs */
251 int exiting; /* shutdown */
252 int ispanic; /* shutdown in response to a panic */
253 int thunderbirdsarego; /* lets the added processors continue to schedinit */
257 * routines for things outside the PC model, like power management
262 int (*ident)(void); /* this should be in the model */
263 void (*reset)(void); /* this should be in the model */
264 int (*serialpower)(int); /* 1 == on, 0 == off */
265 int (*modempower)(int); /* 1 == on, 0 == off */
267 void (*intrinit)(void);
268 int (*intrenable)(Vctl*);
269 int (*intrvecno)(int);
270 int (*intrdisable)(int);
271 void (*introff)(void);
272 void (*intron)(void);
274 void (*clockenable)(void);
275 uvlong (*fastclock)(uvlong*);
276 void (*timerset)(uvlong);
279 /* cpuid instruction result register bits */
286 Vmex = 1<<1, /* virtual-mode extensions */
287 Pse = 1<<3, /* page size extensions */
288 Tsc = 1<<4, /* time-stamp counter */
289 Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */
290 Pae = 1<<6, /* physical-addr extensions */
291 Mce = 1<<7, /* machine-check exception */
294 Mtrr = 1<<12, /* memory-type range regs. */
295 Pge = 1<<13, /* page global extension */
296 Pse2 = 1<<17, /* more page size extensions */
298 Acpif = 1<<22, /* therm control msr */
300 Sse = 1<<25, /* thus sfence instr. */
301 Sse2 = 1<<26, /* thus mfence & lfence instr.s */
305 * a parsed plan9.ini line
322 extern PCArch *arch; /* PC architecture */
325 * Each processor sees its own Mach structure at address MACHADDR.
326 * However, the Mach structures must also be available via the per-processor
327 * MMU information array machp, mainly for disambiguation and access to
328 * the clock which is only maintained by the bootstrap processor (0).
330 Mach* machp[MAXMACH];
332 #define MACHP(n) (machp[n])
335 #define up (((Mach*)MACHADDR)->externup)
338 * hardware info about a device
347 ulong intnum; /* interrupt number */
348 char *type; /* card type, malloced */
349 int nports; /* Number of ports */
350 Devport *ports; /* The ports themselves */
353 typedef struct BIOS32ci { /* BIOS32 Calling Interface */