1 typedef struct BIOS32si BIOS32si;
2 typedef struct BIOS32ci BIOS32ci;
3 typedef struct Conf Conf;
4 typedef struct Confmem Confmem;
5 typedef union FPsave FPsave;
6 typedef struct FPssestate FPssestate;
7 typedef struct FPstate FPstate;
8 typedef struct ISAConf ISAConf;
9 typedef struct Label Label;
10 typedef struct Lock Lock;
11 typedef struct MMU MMU;
12 typedef struct Mach Mach;
13 typedef struct Notsave Notsave;
14 typedef struct PCArch PCArch;
15 typedef struct Pcidev Pcidev;
16 typedef struct PCMmap PCMmap;
17 typedef struct PCMslot PCMslot;
18 typedef struct Page Page;
19 typedef struct PMMU PMMU;
20 typedef struct Proc Proc;
21 typedef struct Segdesc Segdesc;
23 typedef struct Ureg Ureg;
24 typedef struct Vctl Vctl;
26 #pragma incomplete BIOS32si
27 #pragma incomplete Pcidev
28 #pragma incomplete Ureg
30 #define MAXSYSARG 5 /* for mount(fd, afd, mpt, flag, arg) */
33 * parameters for sysproc.c
35 #define AOUT_MAGIC (I_MAGIC)
65 /* the following is a bit that can be or'd into the state */
83 uchar regs[80]; /* floating point registers */
86 struct FPssestate /* SSE fp state */
88 ushort fcw; /* control */
89 ushort fsw; /* status */
91 ushort fop; /* opcode */
93 ushort cs; /* pc segment */
94 ushort rsrvd1; /* reserved */
95 ulong fpudp; /* data pointer */
96 ushort ds; /* data pointer segment */
98 ulong mxcsr; /* MXCSR register state */
99 ulong mxcsr_mask; /* MXCSR mask register */
100 uchar xregs[480]; /* extended registers */
101 uchar alignpad[FPalign];
105 * the FP regs must be stored here, not somewhere pointed to from here.
106 * port code assumes this.
123 ulong nmach; /* processors */
124 ulong nproc; /* processes */
125 ulong monitor; /* has monitor? */
126 Confmem mem[4]; /* physical memory */
127 ulong npage; /* total physical pages of memory */
128 ulong upages; /* user page pool */
129 ulong nimage; /* number of page cache image headers */
130 ulong nswap; /* number of swap pages */
131 int nswppo; /* max # of pageouts per segment pass */
132 ulong base0; /* base of bank 0 */
133 ulong base1; /* base of bank 1 */
134 ulong copymode; /* 0 is copy on write, 1 is copy on reference */
135 ulong ialloc; /* max interrupt time allocation in bytes */
136 ulong pipeqsize; /* size in bytes of pipe queues */
137 int nuart; /* number of uart devices */
152 Page* mmupdb; /* page directory base */
153 Page* mmufree; /* unused page table pages */
154 Page* mmuused; /* used page table pages */
155 Page* kmaptable; /* page table used by kmap */
156 uint lastkmap; /* last entry used by kmap */
157 int nkmap; /* number of current kmaps */
159 Segdesc gdt[NPROCSEG]; /* per process descriptors */
160 Segdesc *ldt; /* local descriptor table */
161 int nldt; /* number of ldt descriptors allocated */
165 * things saved in the Proc structure during a notify
174 #include "../port/portdat.h"
177 ulong link; /* link (old TSS selector) */
178 ulong esp0; /* privilege level 0 stack pointer */
179 ulong ss0; /* privilege level 0 stack selector */
180 ulong esp1; /* privilege level 1 stack pointer */
181 ulong ss1; /* privilege level 1 stack selector */
182 ulong esp2; /* privilege level 2 stack pointer */
183 ulong ss2; /* privilege level 2 stack selector */
184 ulong xcr3; /* page directory base register - not used because we don't use trap gates */
185 ulong eip; /* instruction pointer */
186 ulong eflags; /* flags register */
187 ulong eax; /* general registers */
195 ulong es; /* segment selectors */
201 ulong ldt; /* selector for task's LDT */
202 ulong iomap; /* I/O map base address + T-bit */
207 int machno; /* physical id of processor (KNOWN TO ASSEMBLY) */
208 ulong splpc; /* pc of last caller to splhi */
210 ulong* pdb; /* page directory base for this processor (va) */
211 Tss* tss; /* tss for this processor */
212 Segdesc *gdt; /* gdt for this processor */
214 Proc* proc; /* current process on this processor */
215 Proc* externup; /* extern register Proc *up */
220 ulong ticks; /* of the clock since boot time */
221 Label sched; /* scheduler wakeup */
222 Lock alarmlock; /* access to alarm list */
223 void* alarm; /* alarms bound to this clock */
226 Proc* readied; /* for runproc */
227 ulong schedticks; /* next forced context switch */
236 int flushmmu; /* make current proc flush it's mmu state */
238 Perf perf; /* performance counters */
246 uvlong cyclefreq; /* Frequency of user readable cycle counter */
262 vlong mtrrvar[32]; /* 256 max. */
268 * KMap the structure doesn't exist, but the functions do.
270 typedef struct KMap KMap;
271 #define VA(k) ((void*)(k))
278 int machs; /* bitmap of active CPUs */
279 int exiting; /* shutdown */
280 int ispanic; /* shutdown in response to a panic */
281 int thunderbirdsarego; /* lets the added processors continue to schedinit */
285 * routines for things outside the PC model, like power management
290 int (*ident)(void); /* this should be in the model */
291 void (*reset)(void); /* this should be in the model */
292 int (*serialpower)(int); /* 1 == on, 0 == off */
293 int (*modempower)(int); /* 1 == on, 0 == off */
295 void (*intrinit)(void);
296 int (*intrenable)(Vctl*);
297 int (*intrvecno)(int);
298 int (*intrdisable)(int);
299 void (*introff)(void);
300 void (*intron)(void);
302 void (*clockenable)(void);
303 uvlong (*fastclock)(uvlong*);
304 void (*timerset)(uvlong);
307 /* cpuid instruction result register bits */
314 Vmex = 1<<1, /* virtual-mode extensions */
315 Pse = 1<<3, /* page size extensions */
316 Tsc = 1<<4, /* time-stamp counter */
317 Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */
318 Pae = 1<<6, /* physical-addr extensions */
319 Mce = 1<<7, /* machine-check exception */
322 Mtrr = 1<<12, /* memory-type range regs. */
323 Pge = 1<<13, /* page global extension */
324 Mca = 1<<14, /* machine-check architecture */
325 Pse2 = 1<<17, /* more page size extensions */
327 Acpif = 1<<22, /* therm control msr */
329 Fxsr = 1<<24, /* have SSE FXSAVE/FXRSTOR */
330 Sse = 1<<25, /* thus sfence instr. */
331 Sse2 = 1<<26, /* thus mfence & lfence instr.s */
332 Rdrnd = 1<<30, /* RDRAND support bit */
336 * a parsed plan9.ini line
353 extern PCArch *arch; /* PC architecture */
356 * Each processor sees its own Mach structure at address MACHADDR.
357 * However, the Mach structures must also be available via the per-processor
358 * MMU information array machp, mainly for disambiguation and access to
359 * the clock which is only maintained by the bootstrap processor (0).
361 Mach* machp[MAXMACH];
363 #define MACHP(n) (machp[n])
366 #define up (((Mach*)MACHADDR)->externup)
369 * hardware info about a device
378 ulong intnum; /* interrupt number */
379 char *type; /* card type, malloced */
380 int nports; /* Number of ports */
381 Devport *ports; /* The ports themselves */
384 typedef struct BIOS32ci { /* BIOS32 Calling Interface */