1 typedef struct BIOS32si BIOS32si;
2 typedef struct BIOS32ci BIOS32ci;
3 typedef struct Conf Conf;
4 typedef struct Confmem Confmem;
5 typedef union FPsave FPsave;
6 typedef struct FPx87state FPx87state;
7 typedef struct FPssestate FPssestate;
8 typedef struct PFPU PFPU;
9 typedef struct ISAConf ISAConf;
10 typedef struct Label Label;
11 typedef struct Lock Lock;
12 typedef struct MMU MMU;
13 typedef struct Mach Mach;
14 typedef struct PCArch PCArch;
15 typedef struct Pcidev Pcidev;
16 typedef struct PCMmap PCMmap;
17 typedef struct PCMslot PCMslot;
18 typedef struct Page Page;
19 typedef struct PMMU PMMU;
20 typedef struct Proc Proc;
21 typedef struct Segdesc Segdesc;
23 typedef struct Ureg Ureg;
24 typedef struct Vctl Vctl;
26 #pragma incomplete BIOS32si
27 #pragma incomplete Pcidev
28 #pragma incomplete Ureg
30 #define MAXSYSARG 5 /* for mount(fd, afd, mpt, flag, arg) */
33 * parameters for sysproc.c
35 #define AOUT_MAGIC (I_MAGIC)
54 struct FPx87state /* x87 fp state */
68 uchar regs[80]; /* floating point registers */
71 struct FPssestate /* SSE fp state */
73 ushort fcw; /* control */
74 ushort fsw; /* status */
76 ushort fop; /* opcode */
78 ushort cs; /* pc segment */
79 ushort rsrvd1; /* reserved */
80 ulong fpudp; /* data pointer */
81 ushort ds; /* data pointer segment */
83 ulong mxcsr; /* MXCSR register state */
84 ulong mxcsr_mask; /* MXCSR mask register */
85 uchar xregs[480]; /* extended registers */
101 /* this is a state */
106 /* the following is a bit that can be or'd into the state */
120 ulong nmach; /* processors */
121 ulong nproc; /* processes */
122 ulong monitor; /* has monitor? */
123 Confmem mem[4]; /* physical memory */
124 ulong npage; /* total physical pages of memory */
125 ulong upages; /* user page pool */
126 ulong nimage; /* number of page cache image headers */
127 ulong nswap; /* number of swap pages */
128 int nswppo; /* max # of pageouts per segment pass */
129 ulong base0; /* base of bank 0 */
130 ulong base1; /* base of bank 1 */
131 ulong copymode; /* 0 is copy on write, 1 is copy on reference */
132 ulong ialloc; /* max interrupt time allocation in bytes */
133 ulong pipeqsize; /* size in bytes of pipe queues */
134 int nuart; /* number of uart devices */
149 Page* mmupdb; /* page directory base */
150 Page* mmufree; /* unused page table pages */
151 Page* mmuused; /* used page table pages */
152 Page* kmaptable; /* page table used by kmap */
153 uint lastkmap; /* last entry used by kmap */
154 int nkmap; /* number of current kmaps */
156 Segdesc gdt[NPROCSEG]; /* per process descriptors */
157 Segdesc *ldt; /* local descriptor table */
158 int nldt; /* number of ldt descriptors allocated */
160 u32int dr[8]; /* debug registers */
164 #include "../port/portdat.h"
167 ulong link; /* link (old TSS selector) */
168 ulong esp0; /* privilege level 0 stack pointer */
169 ulong ss0; /* privilege level 0 stack selector */
170 ulong esp1; /* privilege level 1 stack pointer */
171 ulong ss1; /* privilege level 1 stack selector */
172 ulong esp2; /* privilege level 2 stack pointer */
173 ulong ss2; /* privilege level 2 stack selector */
174 ulong xcr3; /* page directory base register - not used because we don't use trap gates */
175 ulong eip; /* instruction pointer */
176 ulong eflags; /* flags register */
177 ulong eax; /* general registers */
185 ulong es; /* segment selectors */
191 ulong ldt; /* selector for task's LDT */
192 ulong iomap; /* I/O map base address + T-bit */
197 int machno; /* physical id of processor (KNOWN TO ASSEMBLY) */
198 ulong splpc; /* pc of last caller to splhi */
200 ulong* pdb; /* page directory base for this processor (va) */
201 Tss* tss; /* tss for this processor */
202 Segdesc *gdt; /* gdt for this processor */
204 Proc* proc; /* current process on this processor */
205 Proc* externup; /* extern register Proc *up */
210 ulong ticks; /* of the clock since boot time */
211 Label sched; /* scheduler wakeup */
212 Lock alarmlock; /* access to alarm list */
213 void* alarm; /* alarms bound to this clock */
216 Proc* readied; /* for runproc */
217 ulong schedticks; /* next forced context switch */
226 int flushmmu; /* make current proc flush it's mmu state */
228 Perf perf; /* performance counters */
236 uvlong cyclefreq; /* Frequency of user readable cycle counter */
250 u32int dr7; /* shadow copy of dr7 */
258 * KMap the structure doesn't exist, but the functions do.
260 typedef struct KMap KMap;
261 #define VA(k) ((void*)(k))
265 extern u32int MemMin;
269 char machs[MAXMACH]; /* active CPUs */
270 int exiting; /* shutdown */
274 * routines for things outside the PC model, like power management
279 int (*ident)(void); /* this should be in the model */
280 void (*reset)(void); /* this should be in the model */
281 int (*serialpower)(int); /* 1 == on, 0 == off */
282 int (*modempower)(int); /* 1 == on, 0 == off */
284 void (*intrinit)(void);
285 int (*intrenable)(Vctl*);
286 int (*intrvecno)(int);
287 int (*intrdisable)(int);
288 void (*introff)(void);
289 void (*intron)(void);
291 void (*clockenable)(void);
292 uvlong (*fastclock)(uvlong*);
293 void (*timerset)(uvlong);
296 /* cpuid instruction result register bits */
303 Vmex = 1<<1, /* virtual-mode extensions */
304 Pse = 1<<3, /* page size extensions */
305 Tsc = 1<<4, /* time-stamp counter */
306 Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */
307 Pae = 1<<6, /* physical-addr extensions */
308 Mce = 1<<7, /* machine-check exception */
311 Mtrr = 1<<12, /* memory-type range regs. */
312 Pge = 1<<13, /* page global extension */
313 Mca = 1<<14, /* machine-check architecture */
314 Pat = 1<<16, /* page attribute table */
315 Pse2 = 1<<17, /* more page size extensions */
317 Acpif = 1<<22, /* therm control msr */
319 Fxsr = 1<<24, /* have SSE FXSAVE/FXRSTOR */
320 Sse = 1<<25, /* thus sfence instr. */
321 Sse2 = 1<<26, /* thus mfence & lfence instr.s */
322 Rdrnd = 1<<30, /* RDRAND support bit */
325 /* model-specific registers, for compatibility with pc64 code */
327 Efer = 0xc0000080, /* Extended Feature Enable */
328 Star = 0xc0000081, /* Legacy Target IP and [CS]S */
329 Lstar = 0xc0000082, /* Long Mode Target IP */
330 Cstar = 0xc0000083, /* Compatibility Target IP */
331 Sfmask = 0xc0000084, /* SYSCALL Flags Mask */
332 FSbase = 0xc0000100, /* 64-bit FS Base Address */
333 GSbase = 0xc0000101, /* 64-bit GS Base Address */
334 KernelGSbase = 0xc0000102, /* SWAPGS instruction */
338 * a parsed plan9.ini line
355 extern PCArch *arch; /* PC architecture */
358 * Each processor sees its own Mach structure at address MACHADDR.
359 * However, the Mach structures must also be available via the per-processor
360 * MMU information array machp, mainly for disambiguation and access to
361 * the clock which is only maintained by the bootstrap processor (0).
363 Mach* machp[MAXMACH];
365 #define MACHP(n) (machp[n])
368 #define up (((Mach*)MACHADDR)->externup)
371 * hardware info about a device
380 ulong intnum; /* interrupt number */
381 char *type; /* card type, malloced */
382 int nports; /* Number of ports */
383 Devport *ports; /* The ports themselves */
386 typedef struct BIOS32ci { /* BIOS32 Calling Interface */