2 #include "../port/lib.h"
7 #include "../port/error.h"
8 #include "../port/audioif.h"
10 typedef struct Ring Ring;
11 typedef struct Hwdesc Hwdesc;
12 typedef struct Ctlr Ctlr;
26 Bufsize = 32768, /* bytes, must be divisible by ndesc */
27 Blocksize = Bufsize/Ndesc,
28 Maxbusywait = 500000, /* microseconds, roughly */
44 /* keep these first, they want to be 8-aligned */
46 Hwdesc outdesc[Ndesc];
47 Hwdesc micdesc[Ndesc];
54 Ring inring, micring, outring;
64 #define iorl(c, r) (inl((c)->port+(r)))
65 #define iowl(c, r, l) (outl((c)->port+(r), (ulong)(l)))
71 Bar = 0x00, /* Base address register, 8-byte aligned */
72 /* a 32-bit read at 0x04 can be used to get civ:lvi:sr in one step */
73 Civ = 0x04, /* current index value (desc being processed) */
74 Lvi = 0x05, /* Last valid index (index of first unused entry!) */
75 Sr = 0x06, /* status register */
76 Fifoe = 1<<4, /* fifo error (r/wc) */
77 Bcis = 1<<3, /* buffer completion interrupt status (r/wc) */
78 Lvbci = 1<<2, /* last valid buffer completion(in)/fetched(out) interrupt (r/wc) */
79 Celv = 1<<1, /* current equals last valid (ro) */
80 Dch = 1<<0, /* dma controller halted (ro) */
81 Picb = 0x08, /* position in current buffer */
82 Piv = 0x0a, /* prefetched index value */
83 Cr = 0x0b, /* control register */
84 Ioce = 1<<4, /* interrupt on buffer completion (if bit set in hwdesc.size) (rw) */
85 Feie = 1<<3, /* fifo error interrupt enable (rw) */
86 Lvbie = 1<<2, /* last valid buffer interrupt enable (rw) */
87 RR = 1<<1, /* reset busmaster related regs, excl. ioce,feie,lvbie (rw) */
88 Rpbm = 1<<0, /* run/pause busmaster. 0 stops, 1 starts (rw) */
89 Cnt = 0x2c, /* global control */
96 Sr2ie = 1<<6, /* sdin2 interrupt enable (rw) */
97 Srie = 1<<5, /* sdin1 interrupt enable (rw) */
98 Prie = 1<<4, /* sdin0 interrupt enable (rw) */
99 Aclso = 1<<3, /* ac link shut-off (rw) */
100 Acwr = 1<<2, /* ac 97 warm reset (rw) */
101 Accr = 1<<1, /* ac 97 cold reset (rw) */
102 GPIie = 1<<0, /* GPI interrupt enable (rw) */
103 Sta = 0x30, /* global status */
106 Md3 = 1<<17, /* modem powerdown semaphore */
107 Ad3 = 1<<16, /* audio powerdown semaphore */
108 Rcs = 1<<15, /* read completion status (r/wc) */
109 S2ri = 1<<29, /* sdin2 resume interrupt (r/wc) */
110 Sri = 1<<11, /* sdin1 resume interrupt (r/wc) */
111 Pri = 1<<10, /* sdin0 resume interrupt (r/wc) */
112 S2cr = 1<<28, /* sdin2 codec ready (ro) */
113 Scr = 1<<9, /* sdin1 codec ready (ro) */
114 Pcr = 1<<8, /* sdin0 codec ready (ro) */
115 Mint = 1<<7, /* microphone in inetrrupt (ro) */
116 Point = 1<<6, /* pcm out interrupt (ro) */
117 Piint = 1<<5, /* pcm in interrupt (ro) */
118 Moint = 1<<2, /* modem out interrupt (ro) */
119 Miint = 1<<1, /* modem in interrupt (ro) */
120 Gsci = 1<<0, /* GPI status change interrupt */
121 Cas = 0x34, /* codec access semaphore */
122 Casp = 1<<0, /* set to 1 on read if zero, cleared by hardware */
135 return r->nbuf - (ri - wi);
143 m = (r->nbuf - BytesPerSample) - buffered(r);
150 readring(Ring *r, uchar *p, long n)
156 if((m = buffered(r)) <= 0)
161 if(r->ri + m > r->nbuf)
163 memmove(p, r->buf + r->ri, m);
166 r->ri = (r->ri + m) % r->nbuf;
173 writering(Ring *r, uchar *p, long n)
179 if((m = available(r)) <= 0)
184 if(r->wi + m > r->nbuf)
186 memmove(r->buf + r->wi, p, m);
189 r->wi = (r->wi + m) % r->nbuf;
195 #define csr8r(c, r) (inb((c)->port+(r)))
196 #define csr16r(c, r) (ins((c)->port+(r)))
197 #define csr32r(c, r) (inl((c)->port+(r)))
198 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
199 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
200 #define csr32w(c, r, w) (outl((c)->port+(r), (ulong)(w)))
203 extern void ac97mixreset(Audio *,
204 void (*wr)(Audio*,int,ushort),
205 ushort (*rr)(Audio*,int));
208 ac97waitcodec(Audio *adev)
213 for(i = 0; i < Maxbusywait/10; i++){
214 if((csr8r(ctlr, Cas) & Casp) == 0)
219 print("#A%d: ac97 exhausted waiting codec access\n", adev->ctlrno);
223 ac97mixw(Audio *adev, int port, ushort val)
228 outs(ctlr->mixport+port, val);
232 ac97mixr(Audio *adev, int port)
237 return ins(ctlr->mixport+port);
241 ac97interrupt(Ureg *, void *arg)
250 stat = csr32r(ctlr, Sta);
251 stat &= S2ri | Sri | Pri | Mint | Point | Piint | Moint | Miint | Gsci;
255 csr16w(ctlr, Out + Picb, csr16r(ctlr, Out + Picb) & ~Dch);
257 csr16w(ctlr, Out + Sr, csr16r(ctlr, Out + Sr) & ~Dch);
258 ring = &ctlr->outring;
259 ring->ri = csr8r(ctlr, Out + Civ) * Blocksize;
264 if(stat) /* have seen 0x400, which is sdin0 resume */
265 iprint("#A%d: ac97 unhandled interrupt(s): stat 0x%lux\n",
270 ac97buffered(Audio *adev)
272 Ctlr *ctlr = adev->ctlr;
273 return buffered(&ctlr->outring);
277 ac97status(Audio *adev, void *a, long n, vlong)
279 Ctlr *ctlr = adev->ctlr;
280 return snprint((char*)a, n, "bufsize %6d buffered %6ld\n",
281 Blocksize, buffered(&ctlr->outring));
288 return available(&ctlr->outring);
295 int delay = ctlr->adev->delay*BytesPerSample;
296 return (delay <= 0) || (buffered(&ctlr->outring) <= delay);
300 ac97write(Audio *adev, void *vp, long n, vlong)
310 ring = &ctlr->outring;
312 oi = ring->wi / Blocksize;
313 if((n = writering(ring, p, e - p)) <= 0){
314 sleep(&ring->r, outavail, ctlr);
317 ni = ring->wi / Blocksize;
319 csr8w(ctlr, Out+Lvi, oi);
320 csr8w(ctlr, Out+Cr, Ioce | Rpbm);
321 oi = (oi + 1) % Ndesc;
325 sleep(&ring->r, outrate, ctlr);
326 return p - (uchar*)vp;
330 ac97close(Audio *adev)
338 ring = &ctlr->outring;
339 while(ring->wi % Blocksize)
340 ac97write(adev, z, sizeof(z), 0);
346 /* not all of the matched devices have been tested */
347 while(p = pcimatch(p, 0, 0))
348 switch((p->vid<<16)|p->did){
349 case (0x1039<<16)|0x7012:
350 case (0x1022<<16)|0x746d:
351 case (0x1022<<16)|0x7445:
352 case (0x10de<<16)|0x01b1:
353 case (0x10de<<16)|0x006a:
354 case (0x10de<<16)|0x00da:
355 case (0x10de<<16)|0x00ea:
356 case (0x8086<<16)|0x2415:
357 case (0x8086<<16)|0x2425:
358 case (0x8086<<16)|0x2445:
359 case (0x8086<<16)|0x2485:
360 case (0x8086<<16)|0x24c5:
361 case (0x8086<<16)|0x24d5:
362 case (0x8086<<16)|0x25a6:
363 case (0x8086<<16)|0x266e:
364 case (0x8086<<16)|0x7195:
371 sethwp(Ctlr *ctlr, long off, void *ptr)
373 csr8w(ctlr, off+Cr, RR);
374 csr32w(ctlr, off+Bar, PCIWADDR(ptr));
375 csr8w(ctlr, off+Lvi, 0);
379 ac97reset(Audio *adev)
381 static Ctlr *cards = nil;
387 /* make a list of all ac97 cards if not already done */
390 while(p = ac97match(p)){
391 ctlr = xspanalloc(sizeof(Ctlr), 8, 0);
392 memset(ctlr, 0, sizeof(Ctlr));
399 /* pick a card from the list */
400 for(ctlr = cards; ctlr; ctlr = ctlr->next){
401 if(p = ctlr->pcidev){
411 if(p->vid == 0x1039 && p->did == 0x7012)
414 if(p->mem[0].size == 64){
415 ctlr->port = p->mem[0].bar & ~3;
416 ctlr->mixport = p->mem[1].bar & ~3;
417 } else if(p->mem[1].size == 64){
418 ctlr->port = p->mem[1].bar & ~3;
419 ctlr->mixport = p->mem[0].bar & ~3;
420 } else if(p->mem[0].size == 256){ /* sis7012 */
421 ctlr->port = p->mem[1].bar & ~3;
422 ctlr->mixport = p->mem[0].bar & ~3;
423 } else if(p->mem[1].size == 256){
424 ctlr->port = p->mem[0].bar & ~3;
425 ctlr->mixport = p->mem[1].bar & ~3;
431 print("#A%d: ac97 port 0x%04lux mixport 0x%04lux irq %d\n",
432 adev->ctlrno, ctlr->port, ctlr->mixport, irq);
437 ctlr->micring.buf = xspanalloc(Bufsize, 8, 0);
438 ctlr->micring.nbuf = Bufsize;
439 ctlr->micring.ri = 0;
440 ctlr->micring.wi = 0;
442 ctlr->inring.buf = xspanalloc(Bufsize, 8, 0);
443 ctlr->inring.nbuf = Bufsize;
447 ctlr->outring.buf = xspanalloc(Bufsize, 8, 0);
448 ctlr->outring.nbuf = Bufsize;
449 ctlr->outring.ri = 0;
450 ctlr->outring.wi = 0;
452 for(i = 0; i < Ndesc; i++){
453 int size, off = i * Blocksize;
458 size = Blocksize / 2;
459 ctlr->micdesc[i].addr = PCIWADDR(ctlr->micring.buf + off);
460 ctlr->micdesc[i].size = Ioc | size;
461 ctlr->indesc[i].addr = PCIWADDR(ctlr->inring.buf + off);
462 ctlr->indesc[i].size = Ioc | size;
463 ctlr->outdesc[i].addr = PCIWADDR(ctlr->outring.buf + off);
464 ctlr->outdesc[i].size = Ioc | size;
467 ctl = csr32r(ctlr, Cnt);
468 ctl &= ~(EnaRESER | Aclso);
470 if((ctl & Accr) == 0){
471 print("#A%d: ac97 cold reset\n", adev->ctlrno);
474 print("#A%d: ac97 warm reset\n", adev->ctlrno);
478 csr32w(ctlr, Cnt, ctl);
479 for(i = 0; i < Maxbusywait; i++){
480 if((csr32r(ctlr, Cnt) & Acwr) == 0)
485 print("#A%d: ac97 gave up waiting Acwr to go down\n", adev->ctlrno);
487 for(i = 0; i < Maxbusywait; i++){
488 if((stat = csr32r(ctlr, Sta)) & (Pcr | Scr | S2cr))
493 print("#A%d: ac97 gave up waiting codecs become ready\n", adev->ctlrno);
495 print("#A%d: ac97 codecs ready:%s%s%s\n", adev->ctlrno,
496 (stat & Pcr) ? " sdin0" : "",
497 (stat & Scr) ? " sdin1" : "",
498 (stat & S2cr) ? " sdin2" : "");
500 print("#A%d: ac97 codecs resumed:%s%s%s\n", adev->ctlrno,
501 (stat & Pri) ? " sdin0" : "",
502 (stat & Sri) ? " sdin1" : "",
503 (stat & S2ri) ? " sdin2" : "");
505 sethwp(ctlr, In, ctlr->indesc);
506 sethwp(ctlr, Out, ctlr->outdesc);
507 sethwp(ctlr, Mic, ctlr->micdesc);
509 csr8w(ctlr, In+Cr, Ioce); /* | Lvbie | Feie */
510 csr8w(ctlr, Out+Cr, Ioce); /* | Lvbie | Feie */
511 csr8w(ctlr, Mic+Cr, Ioce); /* | Lvbie | Feie */
513 ac97mixreset(adev, ac97mixw, ac97mixr);
515 adev->write = ac97write;
516 adev->close = ac97close;
517 adev->buffered = ac97buffered;
518 adev->status = ac97status;
520 intrenable(irq, ac97interrupt, adev, tbdf, adev->name);
528 addaudiocard("ac97", ac97reset);