2 #include "../port/lib.h"
10 enum { /* Local APIC registers */
11 LapicID = 0x0020, /* ID */
12 LapicVER = 0x0030, /* Version */
13 LapicTPR = 0x0080, /* Task Priority */
14 LapicAPR = 0x0090, /* Arbitration Priority */
15 LapicPPR = 0x00A0, /* Processor Priority */
16 LapicEOI = 0x00B0, /* EOI */
17 LapicLDR = 0x00D0, /* Logical Destination */
18 LapicDFR = 0x00E0, /* Destination Format */
19 LapicSVR = 0x00F0, /* Spurious Interrupt Vector */
20 LapicISR = 0x0100, /* Interrupt Status (8 registers) */
21 LapicTMR = 0x0180, /* Trigger Mode (8 registers) */
22 LapicIRR = 0x0200, /* Interrupt Request (8 registers) */
23 LapicESR = 0x0280, /* Error Status */
24 LapicICRLO = 0x0300, /* Interrupt Command */
25 LapicICRHI = 0x0310, /* Interrupt Command [63:32] */
26 LapicTIMER = 0x0320, /* Local Vector Table 0 (TIMER) */
27 LapicPCINT = 0x0340, /* Performance Counter LVT */
28 LapicLINT0 = 0x0350, /* Local Vector Table 1 (LINT0) */
29 LapicLINT1 = 0x0360, /* Local Vector Table 2 (LINT1) */
30 LapicERROR = 0x0370, /* Local Vector Table 3 (ERROR) */
31 LapicTICR = 0x0380, /* Timer Initial Count */
32 LapicTCCR = 0x0390, /* Timer Current Count */
33 LapicTDCR = 0x03E0, /* Timer Divide Configuration */
37 LapicENABLE = 0x00000100, /* Unit Enable */
38 LapicFOCUS = 0x00000200, /* Focus Processor Checking Disable */
41 enum { /* LapicICRLO */
42 /* [14] IPI Trigger Mode Level (RW) */
43 LapicDEASSERT = 0x00000000, /* Deassert level-sensitive interrupt */
44 LapicASSERT = 0x00004000, /* Assert level-sensitive interrupt */
46 /* [17:16] Remote Read Status */
47 LapicINVALID = 0x00000000, /* Invalid */
48 LapicWAIT = 0x00010000, /* In-Progress */
49 LapicVALID = 0x00020000, /* Valid */
51 /* [19:18] Destination Shorthand */
52 LapicFIELD = 0x00000000, /* No shorthand */
53 LapicSELF = 0x00040000, /* Self is single destination */
54 LapicALLINC = 0x00080000, /* All including self */
55 LapicALLEXC = 0x000C0000, /* All Excluding self */
59 LapicSENDCS = 0x00000001, /* Send CS Error */
60 LapicRCVCS = 0x00000002, /* Receive CS Error */
61 LapicSENDACCEPT = 0x00000004, /* Send Accept Error */
62 LapicRCVACCEPT = 0x00000008, /* Receive Accept Error */
63 LapicSENDVECTOR = 0x00000020, /* Send Illegal Vector */
64 LapicRCVVECTOR = 0x00000040, /* Receive Illegal Vector */
65 LapicREGISTER = 0x00000080, /* Illegal Register Address */
68 enum { /* LapicTIMER */
69 /* [17] Timer Mode (RW) */
70 LapicONESHOT = 0x00000000, /* One-shot */
71 LapicPERIODIC = 0x00020000, /* Periodic */
73 /* [19:18] Timer Base (RW) */
74 LapicCLKIN = 0x00000000, /* use CLKIN as input */
75 LapicTMBASE = 0x00040000, /* use TMBASE */
76 LapicDIVIDER = 0x00080000, /* use output of the divider */
79 static uchar lapictdxtab[] = { /* LapicTDCR */
80 0x0B, /* divide by 1 */
81 0x00, /* divide by 2 */
82 0x01, /* divide by 4 */
83 0x02, /* divide by 8 */
84 0x03, /* divide by 16 */
85 0x08, /* divide by 32 */
86 0x09, /* divide by 64 */
87 0x0A, /* divide by 128 */
90 static ulong* lapicbase;
104 return *(lapicbase+(r/sizeof(*lapicbase)));
108 lapicw(int r, ulong data)
110 *(lapicbase+(r/sizeof(*lapicbase))) = data;
111 data = *(lapicbase+(LapicID/sizeof(*lapicbase)));
119 * Reload the timer to de-synchronise the processors,
120 * then lower the task priority to allow interrupts to be
121 * accepted by the APIC.
123 microdelay((TK2MS(1)*1000/conf.nmach) * m->machno);
124 lapicw(LapicTICR, lapictimer.max);
125 lapicw(LapicTIMER, LapicCLKIN|LapicPERIODIC|(VectorPIC+IrqTIMER));
131 * use the i8253 clock to figure out our lapic timer rate.
137 lapicw(LapicTDCR, lapictdxtab[lapictimer.tdx]);
138 lapicw(LapicTIMER, ApicIMASK|LapicCLKIN|LapicONESHOT|(VectorPIC+IrqTIMER));
140 if(lapictimer.hz == 0ULL){
145 lapicw(LapicTICR, 0xffffffff);
150 v = (0xffffffffUL-lapicr(LapicTCCR))*10;
152 if(v > hz+(hz/10) && lapictimer.tdx < nelem(lapictdxtab)-1){
161 lapictimer.div = hz/lapictimer.hz;
162 lapictimer.max = lapictimer.hz/HZ;
163 lapictimer.min = lapictimer.hz/(100*HZ);
168 lapicinit(Apic* apic)
173 lapicbase = apic->addr;
176 * These don't really matter in Physical mode;
177 * set the defaults anyway.
179 if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0)
185 lapicw(LapicDFR, dfr);
186 lapicw(LapicLDR, ldr);
187 lapicw(LapicTPR, 0xff);
188 lapicw(LapicSVR, LapicENABLE|(VectorPIC+IrqSPURIOUS));
193 * Some Pentium revisions have a bug whereby spurious
194 * interrupts are generated in the through-local mode.
196 switch(m->cpuidax & 0xFFF){
197 case 0x526: /* stepping cB1 */
198 case 0x52B: /* stepping E0 */
199 case 0x52C: /* stepping cC0 */
200 wrmsr(0x0E, 1<<14); /* TR12 */
205 * Set the local interrupts. It's likely these should just be
206 * masked off for SMP mode as some Pentium Pros have problems if
207 * LINT[01] are set to ExtINT.
208 * Acknowledge any outstanding interrupts.
209 lapicw(LapicLINT0, apic->lintr[0]);
210 lapicw(LapicLINT1, apic->lintr[1]);
214 lvt = (lapicr(LapicVER)>>16) & 0xFF;
216 lapicw(LapicPCINT, ApicIMASK);
217 lapicw(LapicERROR, VectorPIC+IrqERROR);
222 * Issue an INIT Level De-Assert to synchronise arbitration ID's.
224 lapicw(LapicICRHI, 0);
225 lapicw(LapicICRLO, LapicALLINC|ApicLEVEL|LapicDEASSERT|ApicINIT);
226 while(lapicr(LapicICRLO) & ApicDELIVS)
230 * Do not allow acceptance of interrupts until all initialisation
231 * for this processor is done. For the bootstrap processor this can be
232 * early duing initialisation. For the application processors this should
233 * be after the bootstrap processor has lowered priority and is accepting
240 lapicstartap(Apic* apic, int v)
245 /* make apic's processor do a warm reset */
246 crhi = apic->apicno<<24;
247 lapicw(LapicICRHI, crhi);
248 lapicw(LapicICRLO, LapicFIELD|ApicLEVEL|LapicASSERT|ApicINIT);
250 lapicw(LapicICRLO, LapicFIELD|ApicLEVEL|LapicDEASSERT|ApicINIT);
253 /* assumes apic is not an 82489dx */
254 for(i = 0; i < 2; i++){
255 lapicw(LapicICRHI, crhi);
256 /* make apic's processor start at v in real mode */
257 lapicw(LapicICRLO, LapicFIELD|ApicEDGE|ApicSTARTUP|(v/BY2PG));
263 lapicerror(Ureg*, void*)
268 esr = lapicr(LapicESR);
269 switch(m->cpuidax & 0xFFF){
270 case 0x526: /* stepping cB1 */
271 case 0x52B: /* stepping E0 */
272 case 0x52C: /* stepping cC0 */
275 print("cpu%d: lapicerror: 0x%8.8luX\n", m->machno, esr);
279 lapicspurious(Ureg*, void*)
281 print("cpu%d: lapicspurious\n", m->machno);
289 isr = lapicr(LapicISR + (v/32));
291 return isr & (1<<(v%32));
303 lapicicrw(ulong hi, ulong lo)
305 lapicw(LapicICRHI, hi);
306 lapicw(LapicICRLO, lo);
310 ioapicrdtr(Apic* apic, int sel, int* hi, int* lo)
314 iowin = apic->addr+(0x10/sizeof(ulong));
315 sel = IoapicRDT + 2*sel;
328 ioapicrdtw(Apic* apic, int sel, int hi, int lo)
332 iowin = apic->addr+(0x10/sizeof(ulong));
333 sel = IoapicRDT + 2*sel;
344 ioapicinit(Apic* apic, int apicno)
350 * Initialise the I/O APIC.
351 * The MultiProcessor Specification says it is the responsibility
352 * of the O/S to set the APIC id.
353 * Make sure interrupts are all masked off for now.
355 iowin = apic->addr+(0x10/sizeof(ulong));
357 *apic->addr = IoapicVER;
358 apic->mre = (*iowin>>16) & 0xFF;
360 *apic->addr = IoapicID;
366 for(v = 0; v <= apic->mre; v++)
367 ioapicrdtw(apic, v, hi, lo);
371 lapictimerset(uvlong next)
377 lock(&m->apictimerlock);
379 period = lapictimer.max;
381 period = next - fastticks(nil);
382 period /= lapictimer.div;
384 if(period < lapictimer.min)
385 period = lapictimer.min;
386 else if(period > lapictimer.max - lapictimer.min)
387 period = lapictimer.max;
389 lapicw(LapicTICR, period);
391 unlock(&m->apictimerlock);
396 lapicclock(Ureg *u, void*)
399 * since the MTRR updates need to be synchronized across processors,
400 * we want to do this within the clock tick.
415 lapicw(LapicTPR, 0xFF);
421 lapicw(LapicPCINT, ApicNMI);
425 lapicnmidisable(void)
427 lapicw(LapicPCINT, ApicIMASK);