3 /* arm v7 arch defines these */
4 #define WFI WORD $0xe320f003 /* wait for interrupt */
5 #define DMB WORD $0xf57ff05f /* data mem. barrier; last f = SY */
6 #define DSB WORD $0xf57ff04f /* data synch. barrier; last f = SY */
7 #define ISB WORD $0xf57ff06f /* instr. sync. barrier; last f = SY */
8 #define NOOP WORD $0xe320f000
9 #define CLZ(s, d) WORD $(0xe16f0f10 | (d) << 12 | (s)) /* count leading 0s */
10 #define CPSIE WORD $0xf1080080 /* intr enable: zeroes I bit */
11 #define CPSID WORD $0xf10c0080 /* intr disable: sets I bit */
14 MOVW $0x48020000, R0; \
19 MOVW $0xE0000000, R0; \
23 #define LDREX(a,r) WORD $(0xe<<28|0x01900f9f | (a)<<16 | (r)<<12)
24 #define STREX(a,v,r) WORD $(0xe<<28|0x01800f90 | (a)<<16 | (r)<<12 | (v)<<0)
25 #define CLREX WORD $0xf57ff01f
29 MCR CpSC, 0, R11, C(CpCACHE), C(CpCACHEinvi), CpCACHEflushbtc; \