2 cortex-a8 cpu: arm v7-a arch. rev 3, 500MHz, dual-issue
3 OMAP3530-GP rev 2, CPU-OPP2 L3-165MHz
4 OMAP3 Beagle board + LPDDR/NAND
8 Serial #784200230000000004013f790401d018
11 cortex-a8 cpu: arm v7-a arch. rev 3, 720MHz, dual-issue
12 OMAP3530-GP ES3.1, CPU-OPP2 L3-165MHz
13 IGEP v2.x rev. B + LPDDR/ONENAND
15 Muxed OneNAND(DDP) 512MB 1.8V 16-bit (0x58)
16 OneNAND version = 0x0031
17 Chip support all block unlock
19 Scanning device for bad blocks
20 Bad eraseblock 3134 at 0x187c0000
21 Bad eraseblock 3135 at 0x187e0000
25 CORE_CLK runs at 26MHz
26 see spruf98d from ti.com (/public/doc/ti/omap35x.ref.spruf98d.pdf)
28 separate i & d tlbs, each 32 entries
29 can invalidate i, d or both tlbs by { all, mva, or asid match }
31 i & d L1 caches, 16K each, 4 ways, 64 sets, 64-byte lines
33 no `test and clean D & U all' operations
34 no prefetching, no cache maintenance
35 can invalidate i, d or both cache but not D & U all
36 can invalidate entire i-cache only
37 can clean or invalidate by set and way data/unified cache
38 unified L2 PIPT cache, 256K, 8 ways, 512 sets, 64-byte lines
39 no hardware cache coherence
41 l3 interconnect firewalls are all off at boot time, except for a bit of
43 sram at 0x40200000 size 1MB
44 l4 interconnect firewalls seem to be sane at boot time
47 The state of the Beagleboard/IGEPv2 (TI OMAP35 SoC, Cortex-A8) port.
49 Plan 9 runs on the IGEPv2 and Gumstix Overo boards.
51 On the Beagleboard, Plan 9 is not yet usable but it gets as far as
52 trying to access the USB ethernet (since the Beagleboard has no
53 built-in ethernet and must use USB ethernet).
55 IGEP & Gumstix Ethernet
57 The smsc9221 ethernet consumes a lot of system time. The design
58 decision to use fifos rather than buffer rings and to not incorporate
59 dma into the ethernet controller is probably responsible. With only a
60 single core, running the 9221 consumes a lot of the available CPU
61 time. It's probably worth trying to use the system dma controller again.
65 The ohci and ehci controllers are seen, but no devices yet.
67 There are four USB errata that need to be looked into for the igepv2
68 (silicon 3.1) at least. From the omap3530 errata (rev e):
70 - 3.1.1.130 only one usb dma channel (rx or tx) can be active
71 at one time: use interrupt mode instead
72 - 3.1.1.144 otg soft reset doesn't work right
73 - 3.1.1.183 ohci and ehci controllers cannot work concurrently
74 - §3.1.3 usb limitations: all ports must be configured to identical speeds
79 access to nand flash would be handy for nvram and paqfs or sacfs file
82 In the flash, x-loader occupies up to 0x20000, then u-boot from
83 0x80000 to 0x1e0000, and there's a linux kernel after that (if you
84 care). The beagle's flash chip is a micron pop 2Gb nand
85 mt29f2g16abdhc-et (physical marking jw256), and the igep's is a
90 The Cortex-A8 has VFPv3 floating point, which uses different opcodes
91 than 5c/5l currently generate. New 5c or 5l is in the works.
95 The display subsystem for omap3 (dss) is divided into 3 parts, called lcd,
96 video and dsi (ignoring the various accelerators). The system only
97 supports the lcd via dvi interface so far because it's the only one we
98 have been able to test. 1280x1024x16 is the default resolution, this
99 might be changed. Writing to /dev/dssctl (e.g., echo 1024x768x16
100 >/dev/dssctl) changes the resolution. Currently the system does not
101 use the rfbi since it seems like an unnecessary optimisation at this
102 point. Per Odlund wrote the first draft of the video driver for a
103 Google Summer of Code project.
107 IRQs 56 and 57 are I2C. 83, 86 and 94 are MMC.
111 The code is fairly heavy-handed with the use of barrier instructions
112 (BARRIERS in assembler, coherence in C), partly in reaction to bad
113 experience doing Power PC ports, but also just as precautions against
114 modern processors, which may feel free to execute instructions out of
115 order or some time later, store to memory out of order or some time
116 later, otherwise break the model of traditional sequential processors,
117 or any combination of the above.
120 There are a few rough edges:
122 - the clock.c scheduling rate (HZ) is quite approximate. The OMAP
123 timers are complex, but one could eventually do better (or just let
124 timesync compensate).
126 - User processes are limited to 512MB virtual (mainly by the IGEPv2 Ethernet
127 being at 0x2c000000), which isn't a problem since Beagleboards only
128 have 256MB of dram and IGEPv2s have 512MB, and we don't want to swap.
130 - might use ucalloc.c to allocate uncached scratch space for generated code
133 - the C implementation of cache primitives failed with mmu off; still true?
135 - unlock, setup: protect module register target APE (PM_RT) per spruf98c §1.6.7
137 - setup mpp (multi-purpose pins)?
140 memory map (mostly from omap35x ref)
143 0 16MB physical address of flash registers, buffers
144 20000000 16MB virtual address of flash registers, buffers
145 2c000000 ? smc 9221 ethernet
146 38000000 16MB 256MB (beagle) or 512MB (igep) nand flash mapped here
148 40000000 112K boot rom, top of user space
151 48000000 16MB L4 core
152 48002000 8K system control (scm)
153 48004000 16K clock manager
154 48040000 8K L4-core config
157 48064000 1K usb uhh_config
160 4806a000 8K 8250 uart0
161 4806c000 8K 8250 uart1
162 48086000 4K gptimer10
163 48088000 4K gptimer11
164 4809c000 8K mmc/sd goo
165 480ab000 8K hs usb otg
166 480ad000 8K mmc/sd goo
167 480b4000 8K mmc/sd goo
168 480c7000 device intr controller
169 48200000 2K intr ctlr (intc)
171 48300000 256K L4-wakeup
172 48304000 4K gptimer12
175 49000000 1MB L4 peripherals
176 49020000 8K 8250 uart2 (with exposed connector for console)
185 50000000 64K graphics accelerator
187 68000000 1K L3 config (rt)
188 68004000 1K L3 hs usb host
189 68004400 1K L3 hs usb otg
190 68005400 1K L3 graphics
191 68006800 1K L4-core config
192 68010000 L3 protection mechanism
196 80000000 256MB dram on beagle
199 c0000000 1GB kernel virtual space, mapped to 80000000
201 apparently the vector address (0 or 0xffff0000) is virtual,
202 so we're expected to map it to ram.