2 * OMAP3-specific code for
3 * USB Enhanced Host Controller Interface (EHCI) driver
8 #include "../port/lib.h"
13 #include "../port/error.h"
14 #include "../port/usb.h"
17 static Ctlr* ctlrs[Nhcis];
26 dprint("ehci %#p reset\n", ctlr->capio);
30 * Turn off legacy mode. Some controllers won't
31 * interrupt us as expected otherwise.
35 /* clear high 32 bits of address signals if it's 64 bits capable.
36 * This is probably not needed but it does not hurt and others do it.
38 if((ctlr->capio->capparms & C64) != 0){
39 dprint("ehci: 64 bits\n");
43 opio->cmd |= Chcreset; /* controller reset */
45 for(i = 0; i < 100; i++){
46 if((opio->cmd & Chcreset) == 0)
51 print("ehci %#p controller reset timed out\n", ctlr->capio);
53 /* requesting more interrupts per µframe may miss interrupts */
54 opio->cmd |= 0x10000; /* 1 intr. per ms */
56 switch(opio->cmd & Cflsmask){
67 panic("ehci: unknown fls %ld", opio->cmd & Cflsmask);
70 dprint("ehci: %d frames\n", ctlr->nframes);
90 opio->cmd |= Chcreset; /* controller reset */
92 for(i = 0; i < 100; i++){
93 if((opio->cmd & Chcreset) == 0)
98 print("ehci %#p controller reset timed out\n", ctlr->capio);
107 * omap3-specific ehci code
111 /* opio->insn[5] bits */
112 Control = 1<<31, /* set to start access, cleared when done */
116 Regaddrsh = 16, /* 0x2f means use extended reg addr */
119 /* phy reg addresses */
123 Phystppullupoff = 0x90, /* on is 0x10 */
125 Phyrstport2 = 147, /* gpio # */
130 wrulpi(Eopio *opio, int port, int reg, uchar data)
132 opio->insn[5] = Control | port << Portsh | Write | reg << Regaddrsh |
136 * this seems contrary to the skimpy documentation in the manual
137 * but inverting the test hangs forever.
139 while (!(opio->insn[5] & Control))
156 if(getconf("*nousbehci") != nil || probeaddr(PHYSEHCI) < 0)
159 ctlr = smalloc(sizeof(Ctlr));
161 * don't bother with vmap; i/o space is all mapped anyway,
162 * and a size less than 1MB will blow an assertion in mmukmap.
164 ctlr->capio = capio = (Ecapio *)PHYSEHCI;
165 ctlr->opio = opio = (Eopio*)((uintptr)capio + (capio->cap & 0xff));
168 hp->port = (uintptr)ctlr->capio;
170 hp->nports = capio->parms & Cnports;
172 ddprint("echi: %s, ncc %lud npcc %lud\n",
173 capio->parms & 0x10000 ? "leds" : "no leds",
174 (capio->parms >> 12) & 0xf, (capio->parms >> 8) & 0xf);
175 ddprint("ehci: routing %s, %sport power ctl, %d ports\n",
176 capio->parms & 0x40 ? "explicit" : "automatic",
177 capio->parms & 0x10 ? "" : "no ", hp->nports);
179 ctlr->tdalloc = ucallocalign;
180 ctlr->dmaalloc = ucalloc;
181 ctlr->dmafree = ucfree;
186 /* omap35-specific set up */
187 /* bit 5 `must be set to 1 for proper behavior', spruf98d §23.2.6.7.17 */
188 opio->insn[4] |= 1<<5;
191 /* insn[5] is for both utmi and ulpi, depending on hostconfig mode */
192 uhh = (Uhh *)PHYSUHH;
193 if (uhh->hostconfig & P1ulpi_bypass) { /* utmi port 1 active */
195 iprint("usbehci: bypassing ulpi on port 1!\n");
196 opio->insn[5] &= ~(MASK(4) << 13);
197 opio->insn[5] |= 1 << 13; /* select port 1 */
199 } else { /* ulpi port 1 active */
200 /* TODO may need to reset gpio port2 here */
202 /* disable integrated stp pull-up resistor */
203 wrulpi(opio, 1, Ifcctlreg, Phystppullupoff);
205 /* force phy to `high-speed' */
206 wrulpi(opio, 1, Funcctlreg, 0x40);
210 * Linkage to the generic HCI driver.
213 hp->shutdown = shutdown;
214 hp->debug = setdebug;
216 intrenable(78, hp->interrupt, hp, UNKNOWN, "usbtll");
217 intrenable(92, hp->interrupt, hp, UNKNOWN, "usb otg");
218 intrenable(93, hp->interrupt, hp, UNKNOWN, "usb otg dma");
220 intrenable(hp->irq, hp->interrupt, hp, UNKNOWN, hp->type);
228 addhcitype("ehci", reset);