2 * Memory and machine-specific definitions. Used in C and assembler.
4 #define KiB 1024u /* Kibi 0x0000000000000400 */
5 #define MiB 1048576u /* Mebi 0x0000000000100000 */
6 #define GiB 1073741824u /* Gibi 000000000040000000 */
8 #define HOWMANY(x, y) (((x)+((y)-1))/(y))
9 #define ROUNDUP(x, y) (HOWMANY((x), (y))*(y)) /* ceiling */
10 #define ROUNDDN(x, y) (((x)/(y))*(y)) /* floor */
11 #define MIN(a, b) ((a) < (b)? (a): (b))
12 #define MAX(a, b) ((a) > (b)? (a): (b))
15 * Not sure where these macros should go.
16 * This probably isn't right but will do for now.
17 * The macro names are problematic too.
20 * In B(o), 'o' is the bit offset in the register.
21 * For multi-bit fields use F(v, o, w) where 'v' is the value
22 * of the bit-field of width 'w' with LSb at bit offset 'o'.
25 #define F(v, o, w) (((v) & ((1<<(w))-1))<<(o))
27 #define FCLR(d, o, w) ((d) & ~(((1<<(w))-1)<<(o)))
28 #define FEXT(d, o, w) (((d)>>(o)) & ((1<<(w))-1))
29 #define FINS(d, o, w, v) (FCLR((d), (o), (w))|F((v), (o), (w)))
30 #define FSET(d, o, w) ((d)|(((1<<(w))-1)<<(o)))
32 #define FMASK(o, w) (((1<<(w))-1)<<(o))
37 #define BY2PG (4*KiB) /* bytes per page */
38 #define PGSHIFT 12 /* log(BY2PG) */
39 #define PGROUND(s) ROUNDUP(s, BY2PG)
40 #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
42 #define MAXMACH 1 /* max # cpus system can run */
43 #define MACHSIZE BY2PG
45 #define KSTKSIZE (16*KiB) /* was 8K */
46 #define STACKALIGN(sp) ((sp) & ~3) /* bug: assure with alloc */
50 * KTZERO is used by kprof and dumpstack (if any).
52 * KZERO (0xc0000000) is mapped to physical 0x80000000 (start of dram).
53 * u-boot claims to occupy the first 3 MB of dram, but we're willing to
54 * step on it once we're loaded. Expect plan9.ini in the first 64K past 3MB.
56 * L2 PTEs are stored in 1K before Mach (11K to 12K above KZERO).
57 * cpu0's Mach struct is at L1 - MACHSIZE(4K) to L1 (12K to 16K above KZERO).
58 * L1 PTEs are stored from L1 to L1+32K (16K to 48K above KZERO).
59 * KTZERO may be anywhere after that (but probably shouldn't collide with
61 * This should leave over 8K from KZERO to L2 PTEs.
63 #define KSEG0 0xC0000000 /* kernel segment */
64 /* mask to check segment; good for 512MB dram */
65 #define KSEGM 0xE0000000
66 #define KZERO KSEG0 /* kernel address space */
67 #define L1 (KZERO+16*KiB) /* tt ptes: 16KiB aligned */
68 #define CONFADDR (KZERO+0x300000) /* unparsed plan9.ini */
69 /* KTZERO must match loadaddr in mkfile */
70 #define KTZERO (KZERO+0x310000) /* kernel text start */
72 #define UZERO 0 /* user segment */
73 #define UTZERO (UZERO+BY2PG) /* user text start */
74 #define UTROUND(t) ROUNDUP((t), BY2PG)
75 /* moved USTKTOP down to 512MB to keep MMIO space out of user space. */
76 #define USTKTOP 0x20000000 /* user segment end +1 */
77 #define USTKSIZE (8*1024*1024) /* user stack size */
78 #define TSTKTOP (USTKTOP-USTKSIZE) /* sysexec temporary stack */
81 /* address at which to copy and execute rebootcode */
82 #define REBOOTADDR KADDR(0x100)
87 #define BLOCKALIGN 32 /* only used in allocb.c */
88 #define KSTACK KSTKSIZE
93 #define BI2BY 8 /* bits per byte */
96 #define BY2V 8 /* only used in xalloc.c */
98 #define CACHELINESZ 64 /* bytes per cache line */
99 #define PTEMAPMEM (1024*1024)
100 #define PTEPERTAB (PTEMAPMEM/BY2PG)
101 #define SEGMAPSIZE 1984 /* magic 16*124 */
102 #define SSEGMAPSIZE 16 /* magic */
103 #define PPN(x) ((x)&~(BY2PG-1)) /* pure page number? */
106 * With a little work these move to port.
108 #define PTEVALID (1<<0)
110 #define PTEWRITE (1<<1)
111 #define PTEUNCACHED (1<<2)
112 #define PTEKERNEL (1<<3)
115 * Physical machine information from here on.
118 /* gpmc-controlled address space 0—1G */
119 #define PHYSNAND 1 /* cs0 is onenand flash */
120 #define PHYSETHER 0x2c000000
122 #define PHYSIO 0x48000000 /* L4 ctl */
124 #define PHYSSCM 0x48002000 /* system control module */
126 /* core control pad cfg 0x48002030—0x480021e4, */
127 /* core control d2d pad cfg 0x480021e4—0x48002264 */
128 #define PHYSSCMPCONF 0x48002270 /* general device config */
129 #define PHYSOMAPSTS 0x4800244c /* standalone short: has l2 size */
130 /* core control pad cfg (2) 0x480025d8—0x480025fc */
131 #define PHYSSWBOOTCFG 0x48002910 /* sw booting config */
132 /* wakeup control pad cfg 0x48002a00—0x48002a54 */
134 #define PHYSSCMMPU 0x48004900 /* actually CPU */
135 #define PHYSSCMCORE 0x48004a00
136 #define PHYSSCMWKUP 0x48004c00
137 #define PHYSSCMPLL 0x48004d00 /* clock ctl for dpll[3-5] */
138 #define PHYSSCMDSS 0x48004e00
139 #define PHYSSCMPER 0x48005000
140 #define PHYSSCMUSB 0x48005400
142 #define PHYSL4CORE 0x48040100 /* l4 ap */
143 #define PHYSDSS 0x48050000 /* start of dss registers */
144 #define PHYSDISPC 0x48050400
145 #define PHYSGFX 0x48050480 /* part of dispc */
147 #define PHYSSDMA 0x48056000 /* system dma */
148 #define PHYSDMA 0x48060000
150 #define PHYSUSBTLL 0x48062000 /* usb: transceiver-less link */
151 #define PHYSUHH 0x48064000 /* usb: `high-speed usb host' ctlr or subsys */
152 #define PHYSOHCI 0x48064400 /* usb 1.0: slow */
153 #define PHYSEHCI 0x48064800 /* usb 2.0: medium */
154 #define PHYSUART0 0x4806a000
155 #define PHYSUART1 0x4806c000
156 #define PHYSMMCHS1 0x4809c000 /* mmc/sdio */
157 #define PHYSUSBOTG 0x480ab000 /* on-the-go usb */
158 #define PHYSMMCHS3 0x480ad000
159 #define PHYSMMCHS2 0x480b4000
161 #define PHYSINTC 0x48200000 /* interrupt controller */
163 #define PHYSPRMIVA2 0x48206000 /* prm iva2 regs */
164 /* 48306d40 sys_clkin_sel */
165 #define PHYSPRMGLBL 0x48307200 /* prm global regs */
166 #define PHYSPRMWKUSB 0x48307400
168 #define PHYSCNTRL 0x4830a200 /* SoC id, etc. */
169 #define PHYSWDT1 0x4830c000 /* wdt1, not on GP omaps */
171 #define PHYSGPIO1 0x48310000 /* contains dss gpio */
173 #define PHYSWDOG 0x48314000 /* watchdog timer, wdt2 */
174 #define PHYSWDT2 0x48314000 /* watchdog timer, wdt2 */
175 #define PHYSTIMER1 0x48318000
177 #define PHYSL4WKUP 0x48328100 /* l4 wkup */
178 #define PHYSL4PER 0x49000100 /* l4 per */
180 #define PHYSCONS 0x49020000 /* uart console (third one) */
182 #define PHYSWDT3 0x49030000 /* wdt3 */
183 #define PHYSTIMER2 0x49032000
184 #define PHYSTIMER3 0x49034000
185 #define PHYSGPIO5 0x49056000
186 #define PHYSGPIO6 0x49058000 /* contains igep ether gpio */
188 #define PHYSIOEND 0x49100000 /* end of PHYSIO identity map */
190 #define PHYSL4EMU 0x54006100 /* l4 emu */
191 #define PHYSL4PROT 0x54728000 /* l4 protection regs */
193 #define PHYSL3 0x68000000 /* l3 interconnect control */
194 #define PHYSL3GPMCCFG 0x68002000 /* l3 gpmc target port agent cfg */
195 #define PHYSL3USB 0x68004000 /* l3 regs for usb */
196 #define PHYSL3USBOTG 0x68004400 /* l3 regs for usb otg */
197 /* (target port) protection registers */
198 #define PHYSL3PMRT 0x68010000 /* l3 PM register target prot. */
199 #define PHYSL3GPMCPM 0x68012400 /* l3 gpmc target port protection */
200 #define PHYSL3OCTRAM 0x68012800 /* l3 ocm ram */
201 #define PHYSL3OCTROM 0x68012c00 /* l3 ocm rom */
202 #define PHYSL3MAD2D 0x68013000 /* l3 die-to-die */
203 #define PHYSL3IVA 0x68014000 /* l3 die-to-die */
205 #define PHYSSMS 0x6c000000 /* cfg regs: sms addr space 2 */
206 #define PHYSDRC 0x6d000000 /* sdram ctlr, addr space 3 */
207 #define PHYSGPMC 0x6e000000 /* flash, non-dram memory ctlr */
209 #define PHYSDRAM 0x80000000
211 #define VIRTNAND 0x20000000 /* fixed by u-boot */
212 #define VIRTIO PHYSIO