2 * SMSC 9221 Ethernet driver
3 * specifically for the ISEE IGEPv2 board,
4 * where it is assigned to Chip Select 5,
5 * its registers are at 0x2c000000 (inherited from u-boot),
6 * and irq is 34 from gpio pin 176, thus gpio module 6.
8 * it's slow due to the use of fifos instead of buffer rings.
9 * the slow system dma just makes it worse.
11 * igepv2 u-boot uses pin 64 on gpio 3 as an output pin to reset the 9221.
14 #include "../port/lib.h"
19 #include "../port/error.h"
20 #include "../port/netif.h"
24 /* currently using kprocs is a lot slower than not (87 s. to boot vs 60) */
29 Slop = 4, /* beyond ETHERMAXTU */
32 typedef struct Regs Regs;
36 uchar _pad0[0x20 - 4];
38 uchar _pad1[0x40 - 0x24];
44 /* control & status */
45 ushort rev; /* chip revision */
46 ushort id; /* chip id, 0x9221 */
52 ulong fifoint; /* fifo level interrupts */
56 ulong rxdpctl; /* rx data path control */
59 ulong pmtctl; /* power mgmt. control */
61 ulong gptcfg; /* timer */
65 ulong freerun; /* counters */
69 * mac registers are accessed indirectly via the mac csr registers.
70 * phy registers are doubly indirect, via the mac csr mii_acc &
71 * mii_data mac csr registers.
73 ulong maccsrcmd; /* mac csr synchronizer */
75 ulong afccfg; /* automatic flow control cfg. */
76 ulong eepcmd; /* eeprom */
88 Bufendalign = 3<<24, /* mask */
89 Datastoff = 037<<16, /* mask */
95 Pkttag = MASK(16) << 16,
99 Pktlen = (1<<1) - 1, /* mask */
102 Txsdump = 1<<15, /* flush tx status fifo */
103 Txddump = 1<<14, /* flush tx data fifo */
108 Mbo = 1<<20, /* must be one */
109 Srstto = 1<<1, /* soft reset time-out */
113 Rxdmacntshift = 16, /* ulong count, 12 bits wide */
114 Rxdmacntmask = MASK(12) << Rxdmacntshift,
115 Rxdump = 1<<15, /* flush rx fifos */
118 Rxpktlenshift = 16, /* byte count */
119 Rxpktlenmask = MASK(14) << Rxpktlenshift,
123 Rxstsusedshift = 16, /* ulong count */
124 Rxstsusedmask = MASK(8) << Rxstsusedshift,
125 Rxdatausedmask = MASK(16), /* byte count */
128 Txstsusedshift = 16, /* ulong count */
129 Txstsusedmask = MASK(8) << Txstsusedshift,
130 Txdatafreemask = MASK(16), /* byte count */
137 Csrread = 1<<30, /* not write */
139 Csraddrmask = MASK(8) - 1,
141 /* mac registers' indices */
147 Macmiiacc, /* for doubly-indirect phy access */
158 Rcvown = 1<<23, /* don't receive own transmissions */
159 Fdpx = 1<<20, /* full duplex */
160 Mcpas = 1<<19, /* pass all multicast */
161 Prms = 1<<18, /* promiscuous */
162 Ho = 1<<15, /* hash-only filtering */
163 Hpfilt = 1<<13, /* hash/perfect filtering */
164 Padstr = 1<<8, /* strip padding & fcs (crc) */
169 Irqdeasclr = 1<<14, /* deassertion intv'l clear */
170 Irqdeassts = 1<<13, /* deassertion intv'l status */
171 Irqint = 1<<12, /* intr being asserted? (ro) */
173 Irqpol = 1<<4, /* irq output is active high */
174 Irqpushpull = 1<<0, /* irq output is push/pull driver */
176 /* intsts/inten bits */
177 Swint = 1<<31, /* generate an interrupt */
184 Rxe = 1<<14, /* errors */
186 Tdfo = 1<<10, /* tx data fifo overrun */
187 Tdfa = 1<<9, /* tx data fifo available */
188 Tsff = 1<<8, /* tx status fifo full */
189 Tsfl = 1<<7, /* tx status fifo level */
190 Rsff = 1<<4, /* rx status fifo full */
191 Rsfl = 1<<3, /* rx status fifo level */
195 Epccmdshift = 28, /* interesting one is Reload (7) */
202 Rxintrs = Rsff | Rsfl | Rxe,
203 Txintrs = Tsff | Tsfl | Txe | Txioc,
206 /* wake-up frame filter */
208 ulong bytemask[4]; /* index is filter # */
209 uchar filt0cmd; /* filter 0 command */
217 uchar offset[4]; /* index is filter # */
218 ushort crc16[4]; /* " */
221 typedef struct Ctlr Ctlr;
234 QLock alock; /* attach */
235 int nrb; /* how many this Ctlr has in the pool */
239 int im; /* interrupt mask */
248 uint statistics[Nstatistics];
256 uchar ra[Eaddrlen]; /* receive address */
257 ulong mta[128]; /* multicast table array */
270 #define csr32r(c, r) (*((c)->nic+((r)/4)))
271 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
273 static Ctlr *smcctlrhead, *smcctlrtail;
275 static char* statistics[Nstatistics] = { "dummy", };
277 static uchar mymac[] = { 0xb0, 0x0f, 0xba, 0xbe, 0x00, 0x00, };
279 static void etherclock(void);
280 static void smcreceive(Ether *edev);
281 static void smcinterrupt(Ureg*, void* arg);
283 static Ether *thisether;
293 if (!beenhere && edev != nil) {
295 /* simulate interrupts if we don't know the irq */
296 if (edev->irq < 0) { /* poll as backup */
298 addclock0link(etherclock, 1000/HZ);
306 * indirect (mac) register access
314 for (bound = 400*Mhz; regs->maccsrcmd & Csrbusy && bound > 0; bound--)
317 iprint("smc: mac registers didn't come ready\n");
321 macrd(Regs *regs, uchar index)
324 regs->maccsrcmd = Csrbusy | Csrread | index;
325 coherence(); /* back-to-back write/read delay per §6.2.1 */
327 return regs->maccsrdata;
331 macwr(Regs *regs, uchar index, ulong val)
334 regs->maccsrdata = val;
335 regs->maccsrcmd = Csrbusy | index; /* fire */
341 smcifstat(Ether* edev, void* a, long n, ulong offset)
351 for(i = 0; i < Nstatistics; i++){
352 // read regs->rxdrop TODO
354 if((s = statistics[i]) == nil)
358 ctlr->statistics[i] += r;
359 if(ctlr->statistics[i] == 0)
361 l += snprint(p+l, READSTR-l, "%s: %ud %ud\n",
362 s, ctlr->statistics[i], r);
367 l += snprint(p+l, READSTR-l, "lintr: %ud %ud\n",
368 ctlr->lintr, ctlr->lsleep);
369 l += snprint(p+l, READSTR-l, "rintr: %ud %ud\n",
370 ctlr->rintr, ctlr->rsleep);
371 l += snprint(p+l, READSTR-l, "tintr: %ud %ud\n",
372 ctlr->tintr, ctlr->tsleep);
374 l += snprint(p+l, READSTR-l, "eeprom:");
375 for(i = 0; i < 0x40; i++){
376 if(i && ((i & 0x07) == 0))
377 l += snprint(p+l, READSTR-l, "\n ");
378 l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->eeprom[i]);
380 l += snprint(p+l, READSTR-l, "\n");
383 n = readstr(offset, a, n, p);
385 qunlock(&ctlr->slock);
391 smcpromiscuous(void* arg, int on)
401 rctl = macrd(regs, Maccr);
406 macwr(regs, Maccr, rctl);
410 smcmulticast(void*, uchar*, int)
412 /* nothing to do, we allow all multicast packets in */
416 iswrcpydone(void *arg)
418 return ((Ctlr *)arg)->wrcpydone;
422 smctxstart(Ctlr *ctlr, uchar *ubuf, uint len)
427 static ulong buf[ROUNDUP(ETHERMAXTU, sizeof(ulong)) / sizeof(ulong)];
430 iprint("smctxstart: too soon to send\n");
431 return -1; /* toss it */
435 /* is there room for a packet in the tx data fifo? */
436 if (len < ETHERMINTU)
437 iprint("sending too-short (%d) pkt\n", len);
438 else if (len > ETHERMAXTU)
439 iprint("sending jumbo (%d) pkt\n", len);
441 ruplen = ROUNDUP(len, sizeof(ulong));
442 coherence(); /* back-to-back read/read delay per §6.2.2 */
443 if ((regs->txfifoinf & Txdatafreemask) < ruplen + 2*sizeof(ulong))
444 return -1; /* not enough room for data + command words */
446 if ((uintptr)ubuf & MASK(2)) { /* ensure word alignment */
447 memmove(buf, ubuf, len);
451 /* tx cmd a: length is bytes in this buffer */
452 txdp = ®s->txdata;
453 *txdp = Intcompl | Firstseg | Lastseg | len;
454 /* tx cmd b: length is bytes in this packet (could be multiple buf.s) */
457 /* shovel pkt into tx fifo, which triggers transmission due to Txon */
459 for (wds = ruplen / sizeof(ulong) + 1; --wds > 0; )
462 regs->intsts = Txintrs; /* dismiss intr */
464 regs->inten |= Txintrs;
465 coherence(); /* back-to-back write/read delay per §6.2.1 */
470 smctransmit(Ether* edev)
477 panic("smctransmit: nil ctlr");
480 * Try to fill the chip's buffers back up, via the tx fifo.
482 while ((bp = qget(edev->oq)) != nil)
483 if (smctxstart(ctlr, bp->rp, BLEN(bp)) < 0) {
484 qputback(edev->oq, bp); /* retry the block later */
485 iprint("smctransmit: tx data fifo full\n");
489 iunlock(&ctlr->tlock);
493 smctransmitcall(Ether *edev) /* called from devether.c */
500 wakeup(&ctlr->trendez);
509 return ((Ctlr*)ctlr)->gotinput;
522 sleep(&ctlr->rrendez, smcrim, ctlr);
524 /* process any newly-arrived packets and pass to etheriq */
531 smcgotout(void* ctlr)
533 return ((Ctlr*)ctlr)->gotoutput;
546 sleep(&ctlr->trendez, smcgotout, ctlr);
548 /* process any newly-arrived packets and pass to etheriq */
554 void gpioirqclr(void);
557 smcattach(Ether* edev)
567 qunlock(&ctlr->alock);
573 snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
574 kproc(name, smcrproc, edev);
576 snprint(name, KNAMELEN, "#l%dtproc", edev->ctlrno);
577 kproc(name, smctproc, edev);
580 iprint("smcattach:");
582 iprint(" with kprocs");
584 iprint(" no kprocs");
587 /* can now accept real or simulated interrupts */
593 qunlock(&ctlr->alock);
598 isrdcpydone(void *arg)
600 return ((Ctlr *)arg)->rdcpydone;
604 smcreceive(Ether *edev)
614 coherence(); /* back-to-back read/read delay per §6.2.2 */
616 * is there a full packet in the rx data fifo?
618 while (((regs->rxfifoinf & Rxstsusedmask) >> Rxstsusedshift) != 0) {
620 sts = regs->rxsts; /* pop rx status */
622 iprint("smcreceive: rx error\n");
623 len = (sts & Rxpktlenmask) >> Rxpktlenshift;
624 if (len > ETHERMAXTU + Slop)
625 iprint("smcreceive: oversized rx pkt (%d)\n", len);
626 else if (len < ETHERMINTU)
627 iprint("smcreceive: too-short (%d) pkt\n", len);
628 wds = ROUNDUP(len, sizeof(ulong)) / sizeof(ulong);
630 /* copy aligned words from rx fifo into a Block */
631 bp = iallocb(len + sizeof(ulong) /* - 1 */);
633 panic("smcreceive: nil Block*");
635 /* bp->rp should be 32-byte aligned, more than we need */
636 assert(((uintptr)bp->rp & (sizeof(ulong) - 1)) == 0);
637 wdp = (ulong *)bp->rp;
638 rxdp = ®s->rxdata;
639 wds = ROUNDUP(len, sizeof(ulong)) / sizeof(ulong) + 1;
642 bp->wp = bp->rp + len;
644 /* and push the Block upstream */
646 etheriq(edev, bp, 1);
650 regs->intsts = Rxintrs; /* dismiss intr */
652 regs->inten |= Rxintrs;
656 regs->inten |= Rxintrs;
661 * disable the stsclr bits in inten and write them to intsts to ack and dismiss
662 * the interrupt source.
665 ackintr(Regs *regs, ulong stsclr)
670 regs->inten &= ~stsclr;
673 // regs->intsts = stsclr; /* acknowledge & clear intr(s) */
678 smcinterrupt(Ureg*, void* arg)
681 unsigned intsts, intr;
688 ilock(&ctlr->imlock);
693 coherence(); /* back-to-back read/read delay per §6.2.2 */
694 intsts = regs->intsts;
697 intsts &= ~MASK(3); /* ignore gpio bits */
698 if (0 && intsts == 0) {
700 iprint("smc: interrupt without a cause; insts %#ux (vs inten %#lux)\n",
701 intsts, regs->inten);
704 intr = intsts & Rxintrs;
706 /* disable interrupt sources; kproc/smcreceive will reenable */
712 wakeup(&ctlr->rrendez);
718 while(((regs->txfifoinf & Txstsusedmask) >> Txstsusedshift) != 0) {
719 /* probably indicates tx completion, just toss it */
720 junk = regs->txsts; /* pop tx sts */
725 intr = intsts & Txintrs;
726 if (ctlr->gotoutput || intr) {
727 /* disable interrupt sources; kproc/smctransmit will reenable */
733 wakeup(&ctlr->trendez);
739 iunlock(&ctlr->imlock);
745 smcinterrupt(nil, thisether);
755 smcdetach(Ctlr* ctlr)
759 if (ctlr == nil || ctlr->regs == nil)
762 /* verify that it's real by reading a few registers */
767 print("smc: unknown chip id %#ux\n", regs->id);
770 regs->inten = 0; /* no interrupts */
771 regs->intsts = ~0; /* clear any pending */
774 regs->rxcfg = Rxdump;
775 regs->txcfg = Txsdump | Txddump;
776 regs->irqcfg &= ~Irqen;
782 smcshutdown(Ether* ether)
784 smcdetach(ether->ctlr);
788 powerwait(Regs *regs)
792 regs->bytetest = 0; /* bring power on */
793 for (bound = 400*Mhz; !(regs->pmtctl & Dready) && bound > 0; bound--)
796 iprint("smc: pmtctl didn't come ready\n");
804 static char zea[Eaddrlen];
812 /* verify that it's real by reading a few registers */
817 print("smc: unknown chip id %#ux\n", regs->id);
820 if (regs->bytetest != 0x87654321) {
821 print("smc: bytetest reg %#p (%#lux) != 0x87654321\n",
822 ®s->bytetest, regs->bytetest);
826 #ifdef TODO /* read MAC from EEPROM */
827 // int ctrl, i, pause, swdpio, txcw;
829 * Snarf and set up the receive addresses.
830 * There are 16 addresses. The first should be the MAC address.
831 * The others are cleared and not marked valid (MS bit of Rah).
833 for(i = Ea; i < Eaddrlen/2; i++){
834 ctlr->ra[2*i] = ctlr->eeprom[i];
835 ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
839 * Clear the Multicast Table Array.
840 * It's a 4096 bit vector accessed as 128 32-bit registers.
842 memset(ctlr->mta, 0, sizeof(ctlr->mta));
843 for(i = 0; i < 128; i++)
844 csr32w(ctlr, Mta+i*4, 0);
848 /* don't overwrite existing ea */
849 // if (memcmp(edev->ea, zea, Eaddrlen) == 0)
850 // memmove(edev->ea, ctlr->ra, Eaddrlen);
852 r = ctlr->ra[3]<<24 | ctlr->ra[2]<<16 | ctlr->ra[1]<<8 | ctlr->ra[0];
853 macwr(regs, Macaddrl, r);
854 macwr(regs, Macaddrh, ctlr->ra[5]<<8 | ctlr->ra[4]);
856 /* turn on the controller */
857 macwr(regs, Maccoe, 0);
858 regs->inten = 0; /* no interrupts yet */
859 regs->intsts = ~0; /* clear any pending */
862 regs->rxcfg = Rxdump;
863 regs->txcfg = Txsdump | Txddump | Txon;
864 regs->fifoint = 72<<24; /* default values */
865 macwr(regs, Maccr, Rxall | Rcvown | Fdpx | Mcpas | Txen | Rxen);
866 coherence(); /* back-to-back write/read delay per §6.2.1 */
867 regs->irqcfg = 1<<24 | Irqen | Irqpushpull; /* deas for 10µs (linux) */
868 coherence(); /* back-to-back write/read delay per §6.2.1 */
869 regs->inten = Rxintrs | Txintrs;
887 if (probeaddr(PHYSETHER) < 0)
889 ctlr = malloc(sizeof(Ctlr));
890 ctlr->id = Vid9221<<16 | 0x0424; /* smsc 9221 */
891 ctlr->port = PHYSETHER;
892 ctlr->nic = (int *)PHYSETHER;
893 ctlr->regs = (Regs *)PHYSETHER;
899 if(smcctlrhead != nil)
900 smcctlrtail->next = ctlr;
910 static char zea[Eaddrlen];
912 if(smcctlrhead == nil)
916 * Any adapter matches if no edev->port is supplied,
917 * otherwise the ports must match.
919 for(ctlr = smcctlrhead; ctlr != nil; ctlr = ctlr->next){
922 if(edev->port == 0 || edev->port == ctlr->port){
931 ctlr->edev = edev; /* point back to Ether* */
932 edev->port = ctlr->port;
934 // TODO: verify speed (100Mb/s) and duplicity (full-duplex)
937 /* don't overwrite existing ea */
938 if (memcmp(edev->ea, zea, Eaddrlen) == 0)
939 memmove(edev->ea, ctlr->ra, Eaddrlen);
942 * Linkage to the generic ethernet driver.
944 edev->attach = smcattach;
945 edev->transmit = smctransmitcall;
946 edev->interrupt = smcinterrupt;
947 edev->ifstat = smcifstat;
948 /* edev->ctl = smcctl; /* no ctl msgs supported */
951 edev->promiscuous = smcpromiscuous;
952 edev->multicast = smcmulticast;
953 edev->shutdown = smcshutdown;
960 addethercard("9221", smcpnp);