4 * HZ should divide 1000 evenly, ideally.
5 * 100, 125, 200, 250 and 333 are okay.
7 #define HZ 100 /* clock frequency */
8 #define MS2HZ (1000/HZ) /* millisec per clock tick */
9 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
18 #define MS2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000))
19 #define US2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000000))
22 * we ignore the first 2 uarts on the omap3530 (see uarti8250.c) and use the
23 * third one but call it 0.
27 typedef struct Conf Conf;
28 typedef struct Confmem Confmem;
29 typedef struct FPsave FPsave;
30 typedef struct PFPU PFPU;
31 typedef struct ISAConf ISAConf;
32 typedef struct Label Label;
33 typedef struct Lock Lock;
34 typedef struct Memcache Memcache;
35 typedef struct MMMU MMMU;
36 typedef struct Mach Mach;
37 typedef u32int Mreg; /* Msr - bloody UART */
38 typedef struct Page Page;
39 typedef struct PhysUart PhysUart;
40 typedef struct PMMU PMMU;
41 typedef struct Proc Proc;
43 typedef struct Uart Uart;
44 typedef struct Ureg Ureg;
47 #pragma incomplete Ureg
49 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */
52 * parameters for sysproc.c
54 #define AOUT_MAGIC (E_MAGIC)
73 * emulated floating point
83 ulong regs[Nfpctlregs][3];
114 ulong nmach; /* processors */
115 ulong nproc; /* processes */
116 Confmem mem[1]; /* physical memory */
117 ulong npage; /* total physical pages of memory */
118 ulong upages; /* user page pool */
119 ulong copymode; /* 0 is copy on write, 1 is copy on reference */
120 ulong ialloc; /* max interrupt time allocation in bytes */
121 ulong pipeqsize; /* size in bytes of pipe queues */
122 ulong nimage; /* number of page cache image headers */
123 ulong nswap; /* number of swap pages */
124 int nswppo; /* max # of pageouts per segment pass */
125 ulong hz; /* processor cycle freq */
127 int monitor; /* flag */
135 PTE* mmul1; /* l1 for this processor */
144 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */
148 Page* mmul2cache; /* free mmu pages */
151 #include "../port/portdat.h"
155 int machno; /* physical id of processor */
156 uintptr splpc; /* pc of last caller to splhi */
157 Proc* proc; /* current process */
159 /* end of offsets known to asm */
163 uvlong fastclock; /* last sampled value */
169 uvlong cpuhz; /* speed of cpu */
171 /* save areas for exceptions, hold R0-R4 */
176 u32int smon[5]; /* probably not needed */
186 #define VA(k) ((uintptr)(k))
187 #define kmap(p) (KMap*)((p)->pa|kseg0)
192 char machs[MAXMACH]; /* active CPUs */
193 int exiting; /* shutdown */
196 extern register Mach* m; /* R10 */
197 extern register Proc* up; /* R9 */
198 extern uintptr kseg0;
199 extern Mach* machaddr[MAXMACH];
200 extern ulong memsize;
201 extern int normalprint;
204 * a parsed plan9.ini line
221 #define BUSUNKNOWN -1
223 #define MACHP(n) (machaddr[n])
226 * Horrid. But the alternative is 'defined'.
229 #define DBGFLG (dbgflg[_DBGC_])
235 extern char dbgflg[256];
237 #define dbgprint print /* for now */
240 * hardware info about a device
249 ulong intnum; /* interrupt number */
250 char *type; /* card type, malloced */
251 int nports; /* Number of ports */
252 Devport *ports; /* The ports themselves */
261 /* characteristics of a given cache level */
263 uint level; /* 1 is nearest processor, 2 further away */
264 uint l1ip; /* l1 I policy */
266 uint nways; /* associativity */
268 uint linelen; /* bytes per cache line */
272 uint waysh; /* shifts for set/way register */