2 * arm-specific definitions for cortex-a8
3 * these are used in C and assembler
5 * `cortex' refers specifically to the cortex-a8.
9 * Program Status Registers
11 #define PsrMusr 0x00000010 /* mode */
12 #define PsrMfiq 0x00000011
13 #define PsrMirq 0x00000012
14 #define PsrMsvc 0x00000013 /* `protected mode for OS' */
15 #define PsrMmon 0x00000016 /* `secure monitor' (trustzone hyper) */
16 #define PsrMabt 0x00000017
17 #define PsrMund 0x0000001B
18 #define PsrMsys 0x0000001F /* `privileged user mode for OS' (trustzone) */
19 #define PsrMask 0x0000001F
21 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */
22 #define PsrDirq 0x00000080 /* disable IRQ interrupts */
24 #define PsrV 0x10000000 /* overflow */
25 #define PsrC 0x20000000 /* carry/borrow/extend */
26 #define PsrZ 0x40000000 /* zero */
27 #define PsrN 0x80000000 /* negative/less than */
29 /* instruction decoding */
30 #define ISCPOP(op) ((op) == 0xE || ((op) & ~1) == 0xC)
31 #define ISFPAOP(cp, op) ((cp) == CpOFPA && ISCPOP(op))
32 #define ISVFPOP(cp, op) (((cp) == CpDFP || (cp) == CpFP) && ISCPOP(op))
37 #define CpOFPA 1 /* ancient 7500 FPA */
38 #define CpFP 10 /* float FP, VFP cfg. */
39 #define CpDFP 11 /* double FP */
40 #define CpSC 15 /* System Control */
43 * CpFSR op1==0, Crm==0 opcode 2 values.
45 #define CpDFSR 0 /* data fault status */
46 #define CpIFSR 1 /* instruction fault status */
49 * Primary (CRn) CpSC registers.
51 #define CpID 0 /* ID and cache type */
52 #define CpCONTROL 1 /* miscellaneous control */
53 #define CpTTB 2 /* Translation Table Base(s) */
54 #define CpDAC 3 /* Domain Access Control */
55 #define CpFSR 5 /* Fault Status */
56 #define CpFAR 6 /* Fault Address */
57 #define CpCACHE 7 /* cache/write buffer control */
58 #define CpTLB 8 /* TLB control */
59 #define CpCLD 9 /* L2 Cache Lockdown, op1==1 */
60 #define CpTLD 10 /* TLB Lockdown, with op2 */
61 #define CpVECS 12 /* vector bases, op1==0, Crm==0, op2s (cortex) */
62 #define CpPID 13 /* Process ID */
63 #define CpDTLB 15 /* TLB, L1 cache stuff (cortex) */
66 * CpTTB op1==0, Crm==0 opcode2 values.
69 #define CpTTB1 1 /* cortex */
70 #define CpTTBctl 2 /* cortex */
73 * CpID Secondary (CRm) registers.
78 * CpID op1==0 opcode2 fields.
79 * the cortex has more op1 codes for cache size, etc.
81 #define CpIDid 0 /* main ID */
82 #define CpIDct 1 /* cache type */
83 #define CpIDtlb 3 /* tlb type (cortex) */
84 #define CpIDmpid 5 /* multiprocessor id (cortex) */
86 /* CpIDid op1 values */
87 #define CpIDcsize 1 /* cache size (cortex) */
88 #define CpIDcssel 2 /* cache size select (cortex) */
91 * CpCONTROL op2 codes, op1==0, Crm==0.
98 * CpCONTROL: op1==0, CRm==0, op2==CpMainctl.
99 * main control register.
100 * cortex/armv7 has more ops and CRm values.
102 #define CpCmmu 0x00000001 /* M: MMU enable */
103 #define CpCalign 0x00000002 /* A: alignment fault enable */
104 #define CpCdcache 0x00000004 /* C: data cache on */
105 #define CpCsbo (3<<22|1<<18|1<<16|017<<3) /* must be 1 (armv7) */
106 #define CpCsbz (CpCtre|1<<26|CpCve|1<<15|7<<7) /* must be 0 (armv7) */
107 #define CpCsw (1<<10) /* SW: SWP(B) enable (deprecated in v7) */
108 #define CpCpredict 0x00000800 /* Z: branch prediction (armv7) */
109 #define CpCicache 0x00001000 /* I: instruction cache on */
110 #define CpChv 0x00002000 /* V: high vectors */
111 #define CpCrr (1<<14) /* RR: round robin vs random cache replacement */
112 #define CpCha (1<<17) /* HA: hw access flag enable */
113 #define CpCdz (1<<19) /* DZ: divide by zero fault enable */
114 #define CpCfi (1<<21) /* FI: fast intrs */
115 #define CpCve (1<<24) /* VE: intr vectors enable */
116 #define CpCee (1<<25) /* EE: exception endianness */
117 #define CpCnmfi (1<<27) /* NMFI: non-maskable fast intrs. */
118 #define CpCtre (1<<28) /* TRE: TEX remap enable */
119 #define CpCafe (1<<29) /* AFE: access flag (ttb) enable */
122 * CpCONTROL: op1==0, CRm==0, op2==CpAuxctl.
123 * Auxiliary control register on cortex at least.
125 #define CpACcachenopipe (1<<20) /* don't pipeline cache maint. */
126 #define CpACcp15serial (1<<18) /* serialise CP1[45] ops. */
127 #define CpACcp15waitidle (1<<17) /* CP1[45] wait-on-idle */
128 #define CpACcp15pipeflush (1<<16) /* CP1[45] flush pipeline */
129 #define CpACneonissue1 (1<<12) /* neon single issue */
130 #define CpACldstissue1 (1<<11) /* force single issue ld, st */
131 #define CpACissue1 (1<<10) /* force single issue */
132 #define CpACnobsm (1<<7) /* no branch size mispredicts */
133 #define CpACibe (1<<6) /* cp15 invalidate & btb enable */
134 #define CpACl1neon (1<<5) /* cache neon (FP) data in L1 cache */
135 #define CpACasa (1<<4) /* enable speculative accesses */
136 #define CpACl1pe (1<<3) /* l1 cache parity enable */
137 #define CpACl2en (1<<1) /* l2 cache enable; default 1 */
139 * CpCONTROL Secondary (CRm) registers and opcode2 fields.
141 #define CpCONTROLscr 1
146 * CpCACHE Secondary (CRm) registers and opcode2 fields. op1==0.
147 * In ARM-speak, 'flush' means invalidate and 'clean' means writeback.
149 #define CpCACHEintr 0 /* interrupt (op2==4) */
150 #define CpCACHEisi 1 /* inner-sharable I cache (v7) */
151 #define CpCACHEpaddr 4 /* 0: phys. addr (cortex) */
152 #define CpCACHEinvi 5 /* instruction, branch table */
153 #define CpCACHEinvd 6 /* data or unified */
154 // #define CpCACHEinvu 7 /* unified (not on cortex) */
155 #define CpCACHEva2pa 8 /* va -> pa translation (cortex) */
156 #define CpCACHEwb 10 /* writeback */
157 #define CpCACHEinvdse 11 /* data or unified by mva */
158 #define CpCACHEwbi 14 /* writeback+invalidate */
160 #define CpCACHEall 0 /* entire (not for invd nor wb(i) on cortex) */
161 #define CpCACHEse 1 /* single entry */
162 #define CpCACHEsi 2 /* set/index (set/way) */
163 #define CpCACHEtest 3 /* test loop */
164 #define CpCACHEwait 4 /* wait (prefetch flush on cortex) */
165 #define CpCACHEdmbarr 5 /* wb only (cortex) */
166 #define CpCACHEflushbtc 6 /* flush branch-target cache (cortex) */
167 #define CpCACHEflushbtse 7 /* ⋯ or just one entry in it (cortex) */
170 * CpTLB Secondary (CRm) registers and opcode2 fields.
172 #define CpTLBinvi 5 /* instruction */
173 #define CpTLBinvd 6 /* data */
174 #define CpTLBinvu 7 /* unified */
176 #define CpTLBinv 0 /* invalidate all */
177 #define CpTLBinvse 1 /* invalidate single entry */
178 #define CpTBLasid 2 /* by ASID (cortex) */
181 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==0. (cortex)
183 #define CpCLDena 12 /* enables */
184 #define CpCLDcyc 13 /* cycle counter */
185 #define CpCLDuser 14 /* user enable */
187 #define CpCLDenapmnc 0
188 #define CpCLDenacyc 1
191 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==1.
193 #define CpCLDl2 0 /* l2 cache */
195 #define CpCLDl2aux 2 /* auxiliary control */
198 * l2 cache aux. control
200 #define CpCl2ecc (1<<28) /* use ecc, not parity */
201 #define CpCl2noldforw (1<<27) /* no ld forwarding */
202 #define CpCl2nowrcomb (1<<25) /* no write combining */
203 #define CpCl2nowralldel (1<<24) /* no write allocate delay */
204 #define CpCl2nowrallcomb (1<<23) /* no write allocate combine */
205 #define CpCl2nowralloc (1<<22) /* no write allocate */
206 #define CpCl2eccparity (1<<21) /* enable ecc or parity */
207 #define CpCl2inner (1<<16) /* inner cacheability */
208 /* other bits are tag ram & data ram latencies */
211 * CpTLD Secondary (CRm) registers and opcode2 fields.
213 #define CpTLDlock 0 /* TLB lockdown registers */
214 #define CpTLDpreload 1 /* TLB preload */
216 #define CpTLDi 0 /* TLB instr. lockdown reg. */
217 #define CpTLDd 1 /* " data " " */
220 * CpVECS Secondary (CRm) registers and opcode2 fields.
224 #define CpVECSnorm 0 /* (non-)secure base addr */
225 #define CpVECSmon 1 /* secure monitor base addr */
228 * MMU page table entries.
229 * Mbz (0x10) bit is implementation-defined and must be 0 on the cortex.
232 #define Fault 0x00000000 /* L[12] pte: unmapped */
234 #define Coarse (Mbz|1) /* L1 */
235 #define Section (Mbz|2) /* L1 1MB */
236 #define Fine (Mbz|3) /* L1 */
238 #define Large 0x00000001 /* L2 64KB */
239 #define Small 0x00000002 /* L2 4KB */
240 #define Tiny 0x00000003 /* L2 1KB: not in v7 */
241 #define Buffered 0x00000004 /* L[12]: write-back not -thru */
242 #define Cached 0x00000008 /* L[12] */
245 #define Noaccess 0 /* AP, DAC */
246 #define Krw 1 /* AP */
247 /* armv7 deprecates AP[2] == 1 & AP[1:0] == 2 (Uro), prefers 3 (new in v7) */
248 #define Uro 2 /* AP */
249 #define Urw 3 /* AP */
250 #define Client 1 /* DAC */
251 #define Manager 3 /* DAC */
253 #define AP(n, v) F((v), ((n)*2)+4, 2)
254 #define L1AP(ap) (AP(3, (ap)))
255 #define L2AP(ap) (AP(0, (ap))) /* armv7 */
256 #define DAC(n, v) F((v), (n)*2, 2)
258 #define HVECTORS 0xffff0000