2 * omap3530 SoC (e.g. beagleboard) architecture-specific stuff
4 * errata: usb port 3 cannot operate in ulpi mode, only serial or
9 #include "../port/lib.h"
13 #include "../port/error.h"
17 #include "../port/netif.h"
18 #include "../port/etherif.h"
19 #include "../port/flashif.h"
20 #include "../port/usb.h"
23 #define FREQSEL(x) ((x) << 4)
26 typedef struct Cntrl Cntrl;
27 typedef struct Gen Gen;
28 typedef struct Gpio Gpio;
29 typedef struct L3agent L3agent;
30 typedef struct L3protreg L3protreg;
31 typedef struct L3regs L3regs;
32 typedef struct Prm Prm;
33 typedef struct Usbotg Usbotg;
34 typedef struct Usbtll Usbtll;
36 /* omap3 non-standard usb stuff */
50 /* indexed registers follow; ignore for now */
51 uchar _pad0[0x400 - 0x10];
56 ulong otgifcsel; /* interface selection */
57 uchar _pad1[0x414 - 0x410];
63 Hsen = 1<<5, /* high-speed enable */
66 Forcehost = 1<<7, /* force host (vs peripheral) mode */
67 Forcehs = 1<<4, /* force high-speed at reset */
70 Midle = 1<<12, /* no standby mode */
71 Sidle = 1<<3, /* no idle mode */
74 /* otgsyssts bits, per sysstatus */
78 ulong revision; /* ro */
79 uchar _pad0[0x10-0x4];
81 ulong sysstatus; /* ro */
93 /* only in uhh->sysstatus */
94 Ehci_resetdone = 1<<2,
95 Ohci_resetdone = 1<<1,
99 * an array of these structs is preceded by error_log at 0x20, control,
100 * error_clear_single, error_clear_multi. first struct is at offset 0x48.
102 struct L3protreg { /* hw: an L3 protection region */
103 uvlong req_info_perm;
106 uvlong addr_match; /* ro? write this one last, then flush */
109 // TODO: set these permission bits (e.g., for usb)?
117 struct L3agent { /* hw registers */
121 uchar _pad1[0x58 - 0x30];
127 L3protreg *base; /* base of array */
128 int upper; /* index maximum */
132 (L3protreg *)(PHYSL3GPMCPM+0x48), 7, "gpmc", /* known to be first */
133 (L3protreg *)(PHYSL3PMRT+0x48), 1, "rt", /* l3 config */
134 (L3protreg *)(PHYSL3OCTRAM+0x48), 7, "ocm ram",
135 (L3protreg *)(PHYSL3OCTROM+0x48), 1, "ocm rom",
136 (L3protreg *)(PHYSL3MAD2D+0x48), 7, "mad2d", /* die-to-die */
137 (L3protreg *)(PHYSL3IVA+0x48), 3, "iva2.2", /* a/v */
141 * PRM_CLKSEL (0x48306d40) low 3 bits are system clock speed, assuming
142 * units of MHz: 0 = 12, 1 = 13, 2 = 19.2, 3 = 26, 4 = 38.4, 5 = 16.8
145 struct Cm { /* clock management */
146 ulong fclken; /* ``functional'' clock enable */
149 uchar _pad0[0x10 - 0xc];
151 ulong iclken; /* ``interface'' clock enable */
154 uchar _pad1[0x20 - 0x1c];
156 ulong idlest; /* idle status */
159 uchar _pad2[0x30 - 0x2c];
164 uchar _pad3[0x40 - 0x3c];
173 uchar _pad4[0x70 - 0x40];
178 struct Prm { /* power & reset management */
188 ulong irqsts1; /* for mpu */
192 ulong irqsts2; /* for iva */
206 /* rest are uninteresting */
207 ulong deben; /* debouncing enable */
228 /* clock enable & idle status bits */
229 Wkusimocp = 1 << 9, /* SIM card: uses 120MHz clock */
230 Wkwdt2 = 1 << 5, /* wdt2 clock enable bit for wakeup */
231 Wkgpio1 = 1 << 3, /* gpio1 " */
232 Wkgpt1 = 1 << 0, /* gpt1 " */
234 Dssl3l4 = 1 << 0, /* dss l3, l4 i clks */
235 Dsstv = 1 << 2, /* dss tv f clock */
236 Dss2 = 1 << 1, /* dss clock 2 */
237 Dss1 = 1 << 0, /* dss clock 1 */
244 Perwdt3 = 1 << 12, /* wdt3 clock enable bit for periphs */
245 Peruart3 = 1 << 11, /* console uart */
253 Pergpt2 = 1 << 3, /* gpt2 clock enable bit for periphs */
255 Perenable = Pergpio6 | Pergpio5 | Perwdt3 | Pergpt2 | Peruart3,
257 Usbhost2 = 1 << 1, /* 120MHz clock enable */
258 Usbhost1 = 1 << 0, /* 48MHz clock enable */
259 Usbhost = Usbhost1, /* iclock enable */
260 Usbhostidle = 1 << 1,
261 Usbhoststdby = 1 << 0,
263 Coreusbhsotg = 1 << 4, /* usb hs otg enable bit */
264 Core3usbtll = 1 << 2, /* usb tll enable bit */
266 /* core->idlest bits */
267 Coreusbhsotgidle = 1 << 5,
268 Coreusbhsotgstdby= 1 << 4,
272 /* mpu->idlest2 bits */
276 /* wkup->idlest bits */
279 /* dss->idlest bits */
282 Gpio1vidmagic = 1<<24 | 1<<8 | 1<<5, /* gpio 1 pins for video */
285 Rstgs = 1 << 1, /* global sw. reset */
287 /* fp control regs. most are read-only */
295 /* see ether9221.c for explanation */
298 Etherchanbit = 1 << (Ethergpio % 32),
302 * these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
303 * the Cortex-A8 L2 cache (A=3, L=6).
304 * A = log2(# of ways), L = log2(bytes per cache line).
305 * see armv7 arch ref p. 1403.
314 * cache capabilities. write-back vs write-through is controlled
315 * by the Buffered bit in PTEs.
326 uchar _pad0[0x68 - 8];
341 return "ARM Cortex-A8";
352 /* see Hacker's Delight if this isn't obvious */
353 return (ul & (ul - 1)) == 0;
357 * return exponent of smallest power of 2 โฅ n
365 if (n == 0 || !ispow2(n))
377 m->cpuhz = 500 * Mhz; /* beagle speed */
378 p = getconf("*cpumhz");
381 if (mhz >= 100*Mhz && mhz <= 3000UL*Mhz)
384 m->delayloop = m->cpuhz/2000; /* initial estimate */
390 if (perm == MASK(16))
393 print("%#llux", perm);
397 prl3region(L3protreg *pr, int r)
399 int level, size, addrspace;
406 size = (am >> 3) & MASK(5);
407 if (r > 0 && size == 0) /* disabled? */
410 print(" %d: perms req ", r);
411 prperm(pr->req_info_perm);
412 if (pr->read_perm == pr->write_perm && pr->read_perm == MASK(16))
416 prperm(pr->read_perm);
418 prperm(pr->write_perm);
421 print(", all addrs level 0");
423 size = 1 << size; /* 2^size */
424 level = (am >> 9) & 1;
430 base = am & ~MASK(10);
431 print(", base %#llux size %dKB level %d addrspace %d",
432 base, size, level, addrspace);
440 * dump the l3 interconnect firewall settings by protection region.
441 * mpu, sys dma and both usbs (0x21a) should be set in all read & write
442 * permission registers.
451 for (reg = l3regs; reg < l3regs + nelem(l3regs); reg++) {
452 print("%#p (%s) enabled l3 regions:\n", reg->base, reg->name);
453 for (r = 0; r <= reg->upper; r++)
454 prl3region(reg->base + r, r);
457 /* touch up gpmc perms */
458 reg = l3regs; /* first entry is gpmc */
459 for (r = 0; r <= reg->upper; r++) {
463 print("%#p (%s) modified l3 regions:\n", reg->base, reg->name);
464 for (r = 0; r <= reg->upper; r++)
465 prl3region(reg->base + r, r);
470 p16(uchar *p, ulong v)
477 p32(uchar *p, ulong v)
486 archether(unsigned ctlrno, Ether *ether)
490 /* there's no built-in ether on the beagle but igepv2 has 1 */
491 ether->type = "9221";
492 ether->ctlrno = ctlrno;
502 * turn on all the necessary clocks on the SoC.
504 * a ``functional'' clock drives a device; an ``interface'' clock drives
505 * its communication with the rest of the system. so the interface
506 * clock must be enabled to reach the device's registers.
508 * dplls: 1 mpu, 2 iva2, 3 core, 4 per, 5 per2.
514 ulong clk, mhz, nmhz, maxmhz;
515 Cm *mpu = (Cm *)PHYSSCMMPU;
516 Cntrl *id = (Cntrl *)PHYSCNTRL;
518 if ((id->skuid & MASK(4)) == 8)
522 iprint("cpu capable of %ldMHz operation", maxmhz);
524 clk = mpu->clksel[0];
525 mhz = (clk >> 8) & MASK(11); /* configured speed */
526 // iprint("\tfclk src %ld; dpll1 mult %ld (MHz) div %ld",
527 // (clk >> 19) & MASK(3), mhz, clk & MASK(7));
528 iprint("; at %ldMHz", mhz);
529 nmhz = m->cpuhz / Mhz; /* nominal speed */
538 iprint("; limiting operation to %ldMHz", mhz);
541 /* disable dpll1 lock mode; put into low-power bypass mode */
542 mpu->fclken2 = mpu->fclken2 & ~MASK(3) | 5;
544 while (mpu->idlest2 != Dpllbypassed)
548 * there's a dance to change processor speed,
549 * prescribed in spruf98d ยง4.7.6.9.
552 /* just change multiplier; leave divider alone at 12 (meaning 13?) */
553 mpu->clksel[0] = clk & ~(MASK(11) << 8) | mhz << 8;
556 /* set output divider (M2) in clksel[1]: leave at 1 */
559 * u-boot calls us with just freqsel 3 (~1MHz) & dpll1 lock mode.
562 mpu->fclken2 = mpu->fclken2 & ~FREQSEL(MASK(4)) | FREQSEL(3);
565 /* set ramp-up delay to `fast' */
566 mpu->fclken2 = mpu->fclken2 & ~(MASK(2) << 8) | 3 << 8;
569 /* set auto-recalibration (off) */
570 mpu->fclken2 &= ~(1 << 3);
573 /* disable auto-idle: ? */
574 /* unmask clock intr: later */
576 /* enable dpll lock mode */
577 mpu->fclken2 |= Dplllock;
579 while (mpu->idlest2 != Dplllocked)
581 delay(200); /* allow time for speed to ramp up */
583 if (((mpu->clksel[0] >> 8) & MASK(11)) != mhz)
584 panic("mpu clock speed change didn't stick");
585 iprint("; now at %ldMHz\n", mhz);
592 Cm *pll = (Cm *)PHYSSCMPLL;
594 pll->clkoutctrl |= 1 << 7; /* enable sys_clkout2 */
599 * u-boot calls us with just freqsel 3 (~1MHz) & lock mode
600 * for both dplls (3 & 4). ensure that.
602 if ((pll->idlest & 3) != 3) {
603 /* put dpll[34] into low-power bypass mode */
604 pll->fclken = pll->fclken & ~(MASK(3) << 16 | MASK(3)) |
607 while (pll->idlest & 3) /* wait for both to bypass or stop */
610 pll->fclken = (FREQSEL(3) | Dplllock) << 16 |
611 FREQSEL(3) | Dplllock;
613 while ((pll->idlest & 3) != 3) /* wait for both to lock */
618 * u-boot calls us with just freqsel 1 (default but undefined)
619 * & stop mode for dpll5. try to lock it at 120MHz.
621 if (!(pll->idlest2 & Dplllocked)) {
622 /* force dpll5 into low-power bypass mode */
623 pll->fclken2 = 3 << 8 | FREQSEL(1) | 1;
625 for (i = 0; pll->idlest2 & Dplllocked && i < 20; i++)
628 iprint(" [dpll5 failed to stop]");
633 pll->clksel[4-1] = 120 << 8 | 12; /* M=120, N=12+1 */
634 /* M2 divisor: 120MHz clock is exactly the DPLL5 clock */
635 pll->clksel[5-1] = 1;
638 pll->fclken2 = 3 << 8 | FREQSEL(1) | Dplllock; /* def. freq */
641 for (i = 0; !(pll->idlest2 & Dplllocked) && i < 20; i++)
644 iprint(" [dpll5 failed to lock]");
646 if (!(pll->idlest2 & (1<<1)))
647 iprint(" [no 120MHz clock]");
648 if (!(pll->idlest2 & (1<<3)))
649 iprint(" [no dpll5 120MHz clock output]");
655 Cm *per = (Cm *)PHYSSCMPER;
657 per->clksel[0] &= ~MASK(8); /* select 32kHz clock for GPTIMER2-9 */
659 per->iclken |= Perenable;
661 per->fclken |= Perenable;
663 while (per->idlest & Perenable)
673 Cm *wkup = (Cm *)PHYSSCMWKUP;
675 /* select 32kHz clock (not system clock) for GPTIMER1 */
676 wkup->clksel[0] &= ~1;
678 wkup->iclken |= Wkusimocp | Wkwdt2 | Wkgpt1;
680 wkup->fclken |= Wkusimocp | Wkwdt2 | Wkgpt1;
682 while (wkup->idlest & (Wkusimocp | Wkwdt2 | Wkgpt1))
690 Cm *usb = (Cm *)PHYSSCMUSB;
693 * make the usb registers accessible without address faults,
694 * notably uhh, ochi & ehci. tll seems to be separate & otg is okay.
696 usb->iclken |= Usbhost;
698 usb->fclken |= Usbhost1 | Usbhost2; /* includes 120MHz clock */
700 for (i = 0; usb->idlest & Usbhostidle && i < 20; i++)
703 iprint(" [usb inaccessible]");
709 Cm *core = (Cm *)PHYSSCMCORE;
712 * make the usb tll registers accessible.
714 core->iclken |= Coreusbhsotg;
715 core->iclken3 |= Core3usbtll;
717 core->fclken3 |= Core3usbtll;
720 while (core->idlest & Coreusbhsotgidle)
722 if (core->idlest3 & Core3usbtll)
723 iprint(" [no usb tll]");
730 Gen *gen = (Gen *)PHYSSCMPCONF;
734 configmpu(); /* sets cpu clock rate, turns on dplls 1 & 2 */
737 * the main goal is to get enough clocks running, in the right order,
738 * so that usb has all the necessary clock signals.
742 configusb(); /* starts usb clocks & 120MHz clock */
744 configpll(); /* starts dplls 3, 4 & 5 & 120MHz clock */
746 configwkup(); /* starts timer clocks and usim clock */
748 configper(); /* starts timer & gpio (ether) clocks */
750 configcore(); /* starts usb tll */
753 gen->devconf0 |= 1 << 1 | 1 << 0; /* dmareq[01] edge sensitive */
754 /* make dmareq[2-6] edge sensitive */
755 gen->devconf1 |= 1 << 23 | 1 << 22 | 1 << 21 | 1 << 8 | 1 << 7;
762 resetwait(ulong *reg)
766 for (bound = 400*Mhz; !(*reg & Resetdone) && bound > 0; bound--)
769 iprint("archomap: Resetdone didn't come ready\n");
773 * gpio irq 1 goes to the mpu intr ctlr; irq 2 goes to the iva's.
774 * this stuff is magic and without it, we won't get irq 34 interrupts
775 * from the 9221 ethernet controller.
780 Gpio *gpio = (Gpio *)PHYSGPIO6;
782 gpio->sysconfig = Softreset;
784 resetwait(&gpio->sysstatus);
786 gpio->ctrl = 1<<1 | 0; /* enable this gpio module, gating ratio 1 */
787 gpio->oe |= Etherchanbit; /* cfg ether pin as input */
790 gpio->irqen1 = Etherchanbit; /* channel # == pin # */
793 gpio->lvldet0 = Etherchanbit; /* enable irq ass'n on low det'n */
794 gpio->lvldet1 = 0; /* disable irq ass'n on high det'n */
795 gpio->risingdet = 0; /* enable irq rising edge det'n */
796 gpio->fallingdet = 0; /* disable irq falling edge det'n */
800 gpio->deben = 0; /* no de-bouncing */
804 gpio->irqsts1 = ~0; /* dismiss all outstanding intrs */
810 configscreengpio(void)
812 Cm *wkup = (Cm *)PHYSSCMWKUP;
813 Gpio *gpio = (Gpio *)PHYSGPIO1;
815 /* no clocksel needed */
816 wkup->iclken |= Wkgpio1;
818 wkup->fclken |= Wkgpio1; /* turn gpio clock on */
820 // wkup->autoidle |= Wkgpio1; /* set gpio clock on auto */
823 while (wkup->idlest & Gpio1idle)
827 * 0 bits in oe are output signals.
828 * enable output for gpio 1 (first gpio) video magic pins.
830 gpio->oe &= ~Gpio1vidmagic;
832 gpio->dataout |= Gpio1vidmagic; /* set output pins to 1 */
840 Cm *dss = (Cm *)PHYSSCMDSS;
842 dss->iclken |= Dssl3l4;
844 dss->fclken = Dsstv | Dss2 | Dss1;
846 /* tv fclk is dpll4 clk; dpll4 m4 divide factor for dss1 fclk is 2 */
847 dss->clksel[0] = 1<<12 | 2;
850 while (dss->idlest & Dssidle)
857 Gpio *gpio = (Gpio *)PHYSGPIO6;
859 gpio->irqsts1 = gpio->irqsts1;
866 static char *types[] = {
873 if (type >= nelem(types) || types[type] == nil)
879 cacheinfo(int level, Memcache *cp)
883 /* select cache level */
884 cpwrsc(CpIDcssel, CpID, CpIDid, 0, (level - 1) << 1);
886 setsways = cprdsc(CpIDcsize, CpID, CpIDid, 0);
887 cp->l1ip = cprdsc(0, CpID, CpIDidct, CpIDct);
889 cp->nways = ((setsways >> 3) & MASK(10)) + 1;
890 cp->nsets = ((setsways >> 13) & MASK(15)) + 1;
891 cp->log2linelen = (setsways & MASK(2)) + 2 + 2;
892 cp->linelen = 1 << cp->log2linelen;
893 cp->setsways = setsways;
895 cp->setsh = cp->log2linelen;
896 cp->waysh = 32 - log2(cp->nways);
905 for (cache = 1; cache <= 2; cache++) {
906 cacheinfo(cache, &mc);
907 iprint("l%d: %d ways %d sets %d bytes/line",
908 mc.level, mc.nways, mc.nsets, mc.linelen);
909 if (mc.linelen != CACHELINESZ)
910 iprint(" *should* be %d", CACHELINESZ);
911 if (mc.setsways & Cawt)
913 if (mc.setsways & Cawb)
915 #ifdef COMPULSIVE /* both caches can do this */
916 if (mc.setsways & Cara)
917 iprint("; can read-allocate");
919 if (mc.setsways & Cawa)
920 iprint("; can write-allocate");
922 iprint("; l1 I policy %s",
923 l1iptype((mc.l1ip >> 14) & MASK(2)));
929 subarch(int impl, uint sa)
931 static char *armarchs[] = {
934 "VFPv3+ with common VFP subarch v2",
935 "VFPv3+ with null subarch",
936 "VFPv3+ with common VFP subarch v3",
939 if (impl != 'A' || sa >= nelem(armarchs))
946 * padconf bits in a short, 2 per long register
949 * 13 offpulltypeselect
959 * see table 7-5 in ยง7.4.4.3 of spruf98d
963 /* pad config register bits */
964 Inena = 1 << 8, /* input enable */
965 Indis = 0 << 8, /* input disable */
966 Ptup = 1 << 4, /* pull type up */
967 Ptdown = 0 << 4, /* pull type down */
968 Ptena = 1 << 3, /* pull type selection is active */
969 Ptdis = 0 << 3, /* pull type selection is inactive */
972 /* pad config registers relevant to flash */
982 GpmcA10 = 0x4800208C,
993 GpmcD10 = 0x480020A2,
994 GpmcD11 = 0x480020A4,
995 GpmcD12 = 0x480020A6,
996 GpmcD13 = 0x480020A8,
997 GpmcD14 = 0x480020AA,
998 GpmcD15 = 0x480020AC,
999 GpmcNCS0 = 0x480020AE,
1000 GpmcNCS1 = 0x480020B0,
1001 GpmcNCS2 = 0x480020B2,
1002 GpmcNCS3 = 0x480020B4,
1003 GpmcNCS4 = 0x480020B6,
1004 GpmcNCS5 = 0x480020B8,
1005 GpmcNCS6 = 0x480020BA,
1006 GpmcNCS7 = 0x480020BC,
1007 GpmcCLK = 0x480020BE,
1008 GpmcNADV_ALE = 0x480020C0,
1009 GpmcNOE = 0x480020C2,
1010 GpmcNWE = 0x480020C4,
1011 GpmcNBE0_CLE = 0x480020C6,
1012 GpmcNBE1 = 0x480020C8,
1013 GpmcNWP = 0x480020CA,
1014 GpmcWAIT0 = 0x480020CC,
1015 GpmcWAIT1 = 0x480020CE,
1016 GpmcWAIT2 = 0x480020D0,
1017 GpmcWAIT3 = 0x480020D2,
1020 /* set SCM pad config mux mode */
1022 setmuxmode(ulong addr, int shorts, int mode)
1028 for (ptr = (ushort *)addr; shorts-- > 0; ptr++) {
1029 omode = *ptr & Muxmode;
1031 *ptr = *ptr & ~Muxmode | mode;
1041 /* set scm pad modes for usb; hasn't made any difference yet */
1042 setmuxmode(0x48002166, 7, 5); /* hsusb3_tll* in mode 5; is mode 4 */
1043 setmuxmode(0x48002180, 1, 5); /* hsusb3_tll_clk; is mode 4 */
1044 setmuxmode(0x48002184, 4, 5); /* hsusb3_tll_data?; is mode 1 */
1045 setmuxmode(0x480021a2, 12, 0); /* hsusb0 (console) in mode 0 */
1046 setmuxmode(0x480021d4, 6, 2); /* hsusb2_tll* (ehci port 2) in mode 2 */
1047 /* mode 3 is hsusb2_data* */
1048 setmuxmode(0x480025d8, 18, 6); /* hsusb[12]_tll*; mode 3 is */
1049 /* hsusb1_data*, hsusb2* */
1051 setmuxmode(0x480020e4, 2, 5); /* uart3_rx_* in mode 5 */
1052 setmuxmode(0x4800219a, 4, 0); /* uart3_* in mode 0 */
1053 /* uart3_* in mode 2; TODO: conflicts with hsusb0 */
1054 setmuxmode(0x480021aa, 4, 2);
1055 setmuxmode(0x48002240, 2, 3); /* uart3_* in mode 3 */
1058 * igep/gumstix only: mode 4 of 21d2 is gpio_176 (smsc9221 ether irq).
1059 * see ether9221.c for more.
1061 *(ushort *)0x480021d2 = Inena | Ptup | Ptena | 4;
1063 /* magic from u-boot for flash */
1064 *(ushort *)GpmcA1 = Indis | Ptup | Ptena | 0;
1065 *(ushort *)GpmcA2 = Indis | Ptup | Ptena | 0;
1066 *(ushort *)GpmcA3 = Indis | Ptup | Ptena | 0;
1067 *(ushort *)GpmcA4 = Indis | Ptup | Ptena | 0;
1068 *(ushort *)GpmcA5 = Indis | Ptup | Ptena | 0;
1069 *(ushort *)GpmcA6 = Indis | Ptup | Ptena | 0;
1070 *(ushort *)GpmcA7 = Indis | Ptup | Ptena | 0;
1071 *(ushort *)GpmcA8 = Indis | Ptup | Ptena | 0;
1072 *(ushort *)GpmcA9 = Indis | Ptup | Ptena | 0;
1073 *(ushort *)GpmcA10 = Indis | Ptup | Ptena | 0;
1075 *(ushort *)GpmcD0 = Inena | Ptup | Ptena | 0;
1076 *(ushort *)GpmcD1 = Inena | Ptup | Ptena | 0;
1077 *(ushort *)GpmcD2 = Inena | Ptup | Ptena | 0;
1078 *(ushort *)GpmcD3 = Inena | Ptup | Ptena | 0;
1079 *(ushort *)GpmcD4 = Inena | Ptup | Ptena | 0;
1080 *(ushort *)GpmcD5 = Inena | Ptup | Ptena | 0;
1081 *(ushort *)GpmcD6 = Inena | Ptup | Ptena | 0;
1082 *(ushort *)GpmcD7 = Inena | Ptup | Ptena | 0;
1083 *(ushort *)GpmcD8 = Inena | Ptup | Ptena | 0;
1084 *(ushort *)GpmcD9 = Inena | Ptup | Ptena | 0;
1085 *(ushort *)GpmcD10 = Inena | Ptup | Ptena | 0;
1086 *(ushort *)GpmcD11 = Inena | Ptup | Ptena | 0;
1087 *(ushort *)GpmcD12 = Inena | Ptup | Ptena | 0;
1088 *(ushort *)GpmcD13 = Inena | Ptup | Ptena | 0;
1089 *(ushort *)GpmcD14 = Inena | Ptup | Ptena | 0;
1090 *(ushort *)GpmcD15 = Inena | Ptup | Ptena | 0;
1092 *(ushort *)GpmcNCS0 = Indis | Ptup | Ptena | 0;
1093 *(ushort *)GpmcNCS1 = Indis | Ptup | Ptena | 0;
1094 *(ushort *)GpmcNCS2 = Indis | Ptup | Ptena | 0;
1095 *(ushort *)GpmcNCS3 = Indis | Ptup | Ptena | 0;
1096 *(ushort *)GpmcNCS4 = Indis | Ptup | Ptena | 0;
1097 *(ushort *)GpmcNCS5 = Indis | Ptup | Ptena | 0;
1098 *(ushort *)GpmcNCS6 = Indis | Ptup | Ptena | 0;
1100 *(ushort *)GpmcNOE = Indis | Ptdown | Ptdis | 0;
1101 *(ushort *)GpmcNWE = Indis | Ptdown | Ptdis | 0;
1103 *(ushort *)GpmcWAIT2 = Inena | Ptup | Ptena | 4; /* GPIO_64 -ETH_NRESET */
1104 *(ushort *)GpmcNCS7 = Inena | Ptup | Ptena | 1; /* SYS_nDMA_REQ3 */
1106 *(ushort *)GpmcCLK = Indis | Ptdown | Ptdis | 0;
1108 *(ushort *)GpmcNBE1 = Inena | Ptdown | Ptdis | 0;
1110 *(ushort *)GpmcNADV_ALE = Indis | Ptdown | Ptdis | 0;
1111 *(ushort *)GpmcNBE0_CLE = Indis | Ptdown | Ptdis | 0;
1113 *(ushort *)GpmcNWP = Inena | Ptdown | Ptdis | 0;
1115 *(ushort *)GpmcWAIT0 = Inena | Ptup | Ptena | 0;
1116 *(ushort *)GpmcWAIT1 = Inena | Ptup | Ptena | 0;
1117 *(ushort *)GpmcWAIT3 = Inena | Ptup | Ptena | 0;
1120 * magic from u-boot: set 0xe00 bits in gpmc_(nwe|noe|nadv_ale)
1121 * to enable `off' mode for each.
1123 for (off = 0xc0; off <= 0xc4; off += sizeof(short))
1124 *((ushort *)(PHYSSCM + off)) |= 0xe00;
1129 implement(uchar impl)
1143 gotfp = 1 << CpFP | 1 << CpDFP;
1144 cpwrsc(0, CpCONTROL, 0, CpCPaccess, MASK(28));
1145 acc = cprdsc(0, CpCONTROL, 0, CpCPaccess);
1146 if ((acc & (MASK(2) << (2*CpFP))) == 0) {
1147 gotfp &= ~(1 << CpFP);
1148 print("fpon: no single FP coprocessor\n");
1150 if ((acc & (MASK(2) << (2*CpDFP))) == 0) {
1151 gotfp &= ~(1 << CpDFP);
1152 print("fpon: no double FP coprocessor\n");
1155 print("fpon: no FP coprocessors\n");
1159 /* enable fp. must be first operation on the FPUs. */
1160 fpwr(Fpexc, fprd(Fpexc) | 1 << 30);
1164 print("fp: %s arch %s", implement(impl),
1165 subarch(impl, (scr >> 16) & MASK(7)));
1168 // TODO configure Fpscr further
1169 scr |= 1 << 9; /* div-by-0 exception */
1170 scr &= ~(MASK(2) << 20 | MASK(3) << 16); /* all ops are scalar */
1173 /* we should now be able to execute VFP-style FP instr'ns natively */
1184 iprint("resetting usb: otg...");
1185 otg = (Usbotg *)PHYSUSBOTG;
1186 otg->otgsyscfg = Softreset; /* see omap35x errata 3.1.1.144 */
1188 resetwait(&otg->otgsyssts);
1189 otg->otgsyscfg |= Sidle | Midle;
1193 uhh = (Uhh *)PHYSUHH;
1194 uhh->sysconfig |= Softreset;
1196 resetwait(&uhh->sysstatus);
1197 for (bound = 400*Mhz; !(uhh->sysstatus & Resetdone) && bound > 0;
1200 uhh->sysconfig |= Sidle | Midle;
1203 * using the TLL seems to be an optimisation when talking
1204 * to another identical SoC, thus not very useful, so
1205 * force PHY (ULPI) mode.
1207 /* this bit is normally off when we get here */
1208 uhh->hostconfig &= ~P1ulpi_bypass;
1210 if (uhh->hostconfig & P1ulpi_bypass)
1211 iprint("utmi (tll) mode..."); /* via tll */
1213 /* external transceiver (phy), no tll */
1214 iprint("ulpi (phy) mode...");
1216 tll = (Usbtll *)PHYSUSBTLL;
1217 if (probeaddr(PHYSUSBTLL) >= 0) {
1219 tll->sysconfig |= Softreset;
1221 resetwait(&tll->sysstatus);
1222 tll->sysconfig |= Sidle;
1225 iprint("no tll...");
1230 * there are secure sdrc registers at 0x48002460
1231 * sdrc regs at PHYSSDRC; see spruf98c ยง1.2.8.2.
1232 * set or dump l4 prot regs at PHYSL4?
1237 static int beenhere;
1243 /* conservative temporary values until archconfinit runs */
1244 m->cpuhz = 500 * Mhz; /* beagle speed */
1245 m->delayloop = m->cpuhz/2000; /* initial estimate */
1249 /* fight omap35x errata 2.0.1.104 */
1250 memset((void *)PHYSSWBOOTCFG, 0, 240);
1254 configclks(); /* may change cpu speed */
1266 Prm *prm = (Prm *)PHYSPRMGLBL;
1268 iprint("archreboot: reset!\n");
1271 prm->rstctrl |= Rstgs;
1275 /* shouldn't get here */
1277 iprint("awaiting reset");
1285 lastresortprint(char *buf, long bp)
1287 iprint("%.*s", (int)bp, buf); /* nothing else seems to work */
1291 scmdump(ulong addr, int shorts)
1296 ptr = (ushort *)addr;
1297 print("scm regs:\n");
1298 while (shorts-- > 0) {
1300 print("%#p: %#ux\tinputenable %d pulltypeselect %d "
1301 "pulludenable %d muxmode %d\n",
1302 ptr, reg, (reg>>8) & 1, (reg>>4) & 1, (reg>>3) & 1,
1307 char *cputype2name(char *buf, int size);
1314 cputype2name(name, sizeof name);
1315 delay(250); /* let uart catch up */
1316 iprint("cpu%d: %lldMHz ARM %s\n", m->machno, m->cpuhz / Mhz, name);
1320 missing(ulong addr, char *name)
1322 static int firstmiss = 1;
1324 if (probeaddr(addr) >= 0)
1331 iprint(" %s at %#lux", name, addr);
1334 /* verify that all the necessary device registers are accessible */
1339 missing(PHYSSCM, "scm");
1340 missing(KZERO, "dram");
1341 missing(PHYSL3, "l3 config");
1342 missing(PHYSINTC, "intr ctlr");
1343 missing(PHYSTIMER1, "timer1");
1344 missing(PHYSCONS, "console uart2");
1345 missing(PHYSUART0, "uart0");
1346 missing(PHYSUART1, "uart1");
1347 missing(PHYSETHER, "smc9221"); /* not on beagle */
1348 missing(PHYSUSBOTG, "usb otg");
1349 missing(PHYSUHH, "usb uhh");
1350 missing(PHYSOHCI, "usb ohci");
1351 missing(PHYSEHCI, "usb ehci");
1352 missing(PHYSSDMA, "dma");
1353 missing(PHYSWDOG, "watchdog timer");
1354 missing(PHYSUSBTLL, "usb tll");
1360 archflashwp(Flash*, int)
1365 * for ../port/devflash.c:/^flashreset
1366 * retrieve flash type, virtual base and length and return 0;
1367 * return -1 on error (no flash)
1370 archflashreset(int bank, Flash *f)
1375 * this is set up for the igepv2 board.
1376 * if the beagleboard ever works, we'll have to sort this out.
1378 f->type = "onenand";
1379 f->addr = (void*)PHYSNAND; /* mapped here by archreset */
1380 f->size = 0; /* done by probe */