5 #include "../port/lib.h"
10 #include "../port/error.h"
12 #define DBG if(0) pcilog
21 pcilog(char *fmt, ...)
28 n = vseprint(buf, buf+sizeof(buf), fmt, arg) - buf;
31 memmove(PCICONS.output+PCICONS.ptr, buf, n);
37 { /* configuration mechanism #1 */
38 PciADDR = 0xCF8, /* CONFIG_ADDRESS */
39 PciDATA = 0xCFC, /* CONFIG_DATA */
41 /* configuration mechanism #2 */
42 PciCSE = 0xCF8, /* configuration space enable */
43 PciFORWARD = 0xCFA, /* which bus */
50 { /* command register */
59 static Lock pcicfglock;
60 static QLock pcicfginitlock;
61 static int pcicfgmode = -1;
62 static int pcimaxbno = 7;
64 static Pcidev* pciroot;
65 static Pcidev* pcilist;
66 static Pcidev* pcitail;
68 static int pcicfgrw32(int, int, int, int);
69 static int pcicfgrw8(int, int, int, int);
71 static char* bustypes[] = {
92 #pragma varargck type "T" int
100 if((p = malloc(READSTR)) == nil)
101 return fmtstrcpy(fmt, "(tbdfconv)");
105 tbdf = va_arg(fmt->args, int);
106 type = BUSTYPE(tbdf);
107 if(type < nelem(bustypes))
108 l = snprint(p, READSTR, bustypes[type]);
110 l = snprint(p, READSTR, "%d", type);
111 snprint(p+l, READSTR-l, ".%d.%d.%d",
112 BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf));
116 snprint(p, READSTR, "(tbdfconv)");
119 r = fmtstrcpy(fmt, p);
126 pcibarsize(Pcidev *p, int rno)
130 v = pcicfgrw32(p->tbdf, rno, 0, 1);
131 pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
132 size = pcicfgrw32(p->tbdf, rno, 0, 1);
135 pcicfgrw32(p->tbdf, rno, v, 0);
137 return -(size & ~0x0F);
141 pcisizcmp(void *a, void *b)
147 return aa->siz - bb->siz;
156 for(m = 1<<(m-1); m != 0; m >>= 1) {
170 pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
173 int ntb, i, size, rno, hole;
174 ulong v, mema, ioa, sioa, smema, base, limit;
175 Pcisiz *table, *tptr, *mtb, *itb;
176 extern void qsort(void*, long, long, int (*)(void*, void*));
181 DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
182 wrreg, root->tbdf, mema, ioa);
185 for(p = root; p != nil; p = p->link)
188 ntb *= (PciCIS-PciBAR0)/4;
189 table = malloc(2*ntb*sizeof(Pcisiz));
194 * Build a table of sizes
196 for(p = root; p != nil; p = p->link) {
197 if(p->ccrb == 0x06) {
198 if(p->ccru == 0x04 && p->bridge != nil) {
201 pcibusmap(p->bridge, &smema, &sioa, 0);
203 hole = pcimask(smema-mema);
208 hole = pcimask(sioa-ioa);
216 itb->siz = p->ioa.size;
221 mtb->siz = p->mema.size;
224 if((pcicfgr8(p, PciHDT)&0x7f) != 0)
228 for(i = 0; i <= 5; i++) {
230 v = pcicfgrw32(p->tbdf, rno, 0, 1);
231 size = pcibarsize(p, rno);
248 p->mem[i].size = size;
253 * Sort both tables IO smallest first, Memory largest
255 qsort(table, itb-table, sizeof(Pcisiz), pcisizcmp);
257 qsort(tptr, mtb-tptr, sizeof(Pcisiz), pcisizcmp);
260 * Allocate IO address space on this bus
262 for(tptr = table; tptr < itb; tptr++) {
266 ioa = (ioa+hole-1) & ~(hole-1);
273 p->mem[tptr->bar].bar = ioa|1;
275 pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), ioa|1, 0);
282 * Allocate Memory address space on this bus
284 for(tptr = table+ntb; tptr < mtb; tptr++) {
288 mema = (mema+hole-1) & ~(hole-1);
295 p->mem[tptr->bar].bar = mema;
297 pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), mema, 0);
310 * Finally set all the bridge addresses & registers
312 for(p = root; p != nil; p = p->link) {
313 if(p->bridge == nil) {
314 pcicfgrw8(p->tbdf, PciLTR, 64, 0);
317 pcicfgrw32(p->tbdf, PciPCR, p->pcr, 0);
322 limit = base+p->ioa.size-1;
323 v = pcicfgrw32(p->tbdf, PciIBR, 0, 1);
324 v = (v&0xFFFF0000)|(limit & 0xF000)|((base & 0xF000)>>8);
325 pcicfgrw32(p->tbdf, PciIBR, v, 0);
326 v = (limit & 0xFFFF0000)|(base>>16);
327 pcicfgrw32(p->tbdf, PciIUBR, v, 0);
330 limit = base+p->mema.size-1;
331 v = (limit & 0xFFF00000)|((base & 0xFFF00000)>>16);
332 pcicfgrw32(p->tbdf, PciMBR, v, 0);
335 * Disable memory prefetch
337 pcicfgrw32(p->tbdf, PciPMBR, 0x0000FFFF, 0);
338 pcicfgrw8(p->tbdf, PciLTR, 64, 0);
343 v = 0xFFFF0000 | IOen | MEMen | MASen;
344 pcicfgrw32(p->tbdf, PciPCR, v, 0);
348 pcibusmap(p->bridge, &smema, &sioa, 1);
353 pcilscan(int bno, Pcidev** list)
355 Pcidev *p, *head, *tail;
356 int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
361 for(dno = 0; dno <= pcimaxdno; dno++){
363 for(fno = 0; fno <= maxfno; fno++){
365 * For this possible device, form the
366 * bus+device+function triplet needed to address it
367 * and try to read the vendor and device ID.
368 * If successful, allocate a device struct and
369 * start to fill it in with some useful information
370 * from the device's configuration space.
372 tbdf = MKBUS(BusPCI, bno, dno, fno);
373 l = pcicfgrw32(tbdf, PciVID, 0, 1);
374 if(l == 0xFFFFFFFF || l == 0)
376 p = malloc(sizeof(*p));
387 p->rid = pcicfgr8(p, PciRID);
388 p->ccrp = pcicfgr8(p, PciCCRp);
389 p->ccru = pcicfgr8(p, PciCCRu);
390 p->ccrb = pcicfgr8(p, PciCCRb);
391 p->pcr = pcicfgr32(p, PciPCR);
393 p->intl = pcicfgr8(p, PciINTL);
396 * If the device is a multi-function device adjust the
397 * loop count so all possible functions are checked.
399 hdt = pcicfgr8(p, PciHDT);
404 * If appropriate, read the base address registers
405 * and work out the sizes.
408 case 0x01: /* mass storage controller */
409 case 0x02: /* network controller */
410 case 0x03: /* display controller */
411 case 0x04: /* multimedia device */
412 case 0x06: /* bridge device */
413 case 0x07: /* simple comm. controllers */
414 case 0x08: /* base system peripherals */
415 case 0x09: /* input devices */
416 case 0x0A: /* docking stations */
417 case 0x0B: /* processors */
418 case 0x0C: /* serial bus controllers */
419 if((hdt & 0x7F) != 0)
422 for(i = 0; i < nelem(p->mem); i++) {
424 p->mem[i].bar = pcicfgr32(p, rno);
425 p->mem[i].size = pcibarsize(p, rno);
430 case 0x05: /* memory controller */
444 for(p = head; p != nil; p = p->link){
446 * Find PCI-PCI bridges and recursively descend the tree.
448 if(p->ccrb != 0x06 || p->ccru != 0x04)
452 * If the secondary or subordinate bus number is not
453 * initialised try to do what the PCI BIOS should have
454 * done and fill in the numbers as the tree is descended.
455 * On the way down the subordinate bus number is set to
456 * the maximum as it's not known how many buses are behind
457 * this one; the final value is set on the way back up.
459 sbn = pcicfgr8(p, PciSBN);
460 ubn = pcicfgr8(p, PciUBN);
462 if(sbn == 0 || ubn == 0) {
465 * Make sure memory, I/O and master enables are
466 * off, set the primary, secondary and subordinate
467 * bus numbers and clear the secondary status before
468 * attempting to scan the secondary bus.
470 * Initialisation of the bridge should be done here.
472 pcicfgw32(p, PciPCR, 0xFFFF0000);
473 l = (MaxUBN<<16)|(sbn<<8)|bno;
474 pcicfgw32(p, PciPBN, l);
475 pcicfgw16(p, PciSPSR, 0xFFFF);
476 maxubn = pcilscan(sbn, &p->bridge);
477 l = (maxubn<<16)|(sbn<<8)|bno;
479 pcicfgw32(p, PciPBN, l);
483 pcilscan(sbn, &p->bridge);
491 pciscan(int bno, Pcidev **list)
495 qlock(&pcicfginitlock);
496 ubn = pcilscan(bno, list);
497 qunlock(&pcicfginitlock);
509 qlock(&pcicfginitlock);
514 * Try to determine which PCI configuration mode is implemented.
515 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
516 * a DWORD at 0xCF8 and another at 0xCFC and will pass through
517 * any non-DWORD accesses as normal I/O cycles. There shouldn't be
518 * a device behind these addresses so if Mode2 accesses fail try
519 * for Mode1 (which is preferred, Mode2 is deprecated).
522 if(inb(PciCSE) == 0){
528 if(inl(PciADDR) == 0){
537 fmtinstall('T', tbdffmt);
539 if(p = getconf("*pcimaxbno"))
540 pcimaxbno = strtoul(p, 0, 0);
541 if(p = getconf("*pcimaxdno"))
542 pcimaxdno = strtoul(p, 0, 0);
545 for(bno = 0; bno <= pcimaxbno; bno++) {
547 bno = pcilscan(bno, list);
550 list = &(*list)->link;
556 * If we have found a PCI-to-Cardbus bridge, make sure
557 * it has no valid mappings anymore.
561 if (pci->ccrb == 6 && pci->ccru == 7) {
564 /* reset the cardbus */
565 bcr = pcicfgr16(pci, PciBCR);
566 pcicfgw16(pci, PciBCR, 0x40 | bcr);
578 * Work out how big the top bus is
582 pcibusmap(pciroot, &mema, &ioa, 0);
584 DBG("Sizes: mem=%8.8lux size=%8.8lux io=%8.8lux\n",
585 mema, pcimask(mema), ioa);
588 * Align the windows and map it
593 pcilog("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
595 pcibusmap(pciroot, &mema, &ioa, 1);
596 DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
599 qunlock(&pcicfginitlock);
603 pcicfgrw8(int tbdf, int rno, int data, int read)
615 if(BUSDNO(tbdf) > pcimaxdno)
624 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
628 outb(PciDATA+o, data);
633 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
634 outb(PciFORWARD, BUSBNO(tbdf));
636 x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
638 outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
648 pcicfgr8(Pcidev* pcidev, int rno)
650 return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
654 pcicfgw8(Pcidev* pcidev, int rno, int data)
656 pcicfgrw8(pcidev->tbdf, rno, data, 0);
660 pcicfgrw16(int tbdf, int rno, int data, int read)
672 if(BUSDNO(tbdf) > pcimaxdno)
681 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
685 outs(PciDATA+o, data);
690 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
691 outb(PciFORWARD, BUSBNO(tbdf));
693 x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
695 outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
705 pcicfgr16(Pcidev* pcidev, int rno)
707 return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
711 pcicfgw16(Pcidev* pcidev, int rno, int data)
713 pcicfgrw16(pcidev->tbdf, rno, data, 0);
717 pcicfgrw32(int tbdf, int rno, int data, int read)
729 if(BUSDNO(tbdf) > pcimaxdno)
737 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
746 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
747 outb(PciFORWARD, BUSBNO(tbdf));
749 x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
751 outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
761 pcicfgr32(Pcidev* pcidev, int rno)
763 return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
767 pcicfgw32(Pcidev* pcidev, int rno, int data)
769 pcicfgrw32(pcidev->tbdf, rno, data, 0);
773 pcimatch(Pcidev* prev, int vid, int did)
784 if((vid == 0 || prev->vid == vid)
785 && (did == 0 || prev->did == did))
793 pcimatchtbdf(int tbdf)
800 for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
801 if(pcidev->tbdf == tbdf)
808 pciipin(Pcidev *pci, uchar pin)
816 if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
819 if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
834 putstrn(PCICONS.output, PCICONS.ptr);
836 print("bus dev type vid did intl memory\n");
838 for(t = p; t != nil; t = t->link) {
839 print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
840 BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
841 t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
843 for(i = 0; i < nelem(p->mem); i++) {
844 if(t->mem[i].size == 0)
846 print("%d:%.8lux %d ", i,
847 t->mem[i].bar, t->mem[i].size);
849 if(t->ioa.bar || t->ioa.size)
850 print("ioa:%.8lux %d ", t->ioa.bar, t->ioa.size);
851 if(t->mema.bar || t->mema.size)
852 print("mema:%.8lux %d ", t->mema.bar, t->mema.size);
854 print("->%d", BUSBNO(t->bridge->tbdf));
869 qlock(&pcicfginitlock);
871 qunlock(&pcicfginitlock);
883 for(p = pcilist; p != nil; p = p->list){
884 pcr = pcicfgr16(p, PciPCR);
886 pcicfgw16(p, PciPCR, pcr);
895 pcr = pcicfgr16(p, PciPCR);
897 pcicfgw16(p, PciPCR, pcr);
905 pcr = pcicfgr16(p, PciPCR);
907 pcicfgw16(p, PciPCR, pcr);