1 global scale sheevaplug & guruplug
3 marvell 88f6281 (feroceon kirkwood) SoC
4 arm926ej-s rev 1 [56251311] (armv5tejl) 1.2GHz cpu
6 l1 I & D VIVT caches 16K each: 4-way, 128 sets, 32-byte lines
7 l1 D is write-through, l1 I is write-back
8 unified l2 PIPT cache 256K: 4-way, 2048 sets, 32-byte lines
9 potentially 512K: 8-way
11 apparently the mmu walks the page tables in dram and won't look in the
12 l2 cache. there is no hardware cache coherence, thus the l1 caches
13 need to be flushed or invalidated when mmu mappings change, but l2
14 only needs to be flushed or invalidated around dma operations and page
15 table changes, and only the affected dma buffers and descriptors or
16 page table entries need to be flushed or invalidated in l2.
18 we arrange that device registers are uncached.
20 be aware that cache operations act on cache lines (of CACHELINESZ
21 bytes) as atomic units, so if you invalidate one word of a cache line,
22 you invalidate the entire cache line, whether it's been written back
23 (is clean) or not (is dirty). mixed data structures with parts
24 maintained by hardware and other parts by software are especially
25 tricky. we try to pad the initial hardware parts so that the software
26 parts start in a new cache line.
28 there are no video controllers so far, so this port is a cpu
31 512MB of dram at physical address 0
33 16550 uart for console
34 see http://www.marvell.com/files/products/embedded_processors/kirkwood/\
35 FS_88F6180_9x_6281_OpenSource.pdf, stored locally as
36 /public/doc/marvell/88f61xx.kirkwood.pdf
38 If you plan to use flash, it would be wise to avoid touching the first
39 megabyte, which contains u-boot, right up to 0x100000. There's a
40 linux kernel from there to 0x400000, if you care. You'll also likely
41 want to use paqfs rather than fossil or kfs for file systems in flash
42 since there is no wear-levelling.
44 The code is fairly heavy-handed with the use of barrier instructions
45 (BARRIERS in assembler, coherence in C), partly in reaction to bad
46 experience doing Power PC ports, but also just as precautions against
47 modern processors, which may feel free to execute instructions out of
48 order or some time later, store to memory out of order or some time
49 later, otherwise break the model of traditional sequential processors,
50 or any combination of the above.
52 this plan 9 port is based on the port of native inferno to the
53 sheevaplug by Salva Peiró (saoret.one@gmail.com) and Mechiel Lukkien
58 # type this once at u-boot, replacing 00504301c49e with your plug's
59 # mac address; thereafter the plug will pxe boot:
61 setenv bootcmd 'bootp; bootp; tftp 0x1000 /cfg/pxe/00504301c49e; bootp; tftp 0x800000; go 0x800000'
64 # see /cfg/pxe/example-kw
72 80000000 512MB pcie mem # default
74 d0000000 1MB internal regs default address at reset
75 d8000000 128MB nand flash # actually 512MB addressed through this
76 e8000000 128MB spi serial flash
77 f0000000 128MB boot rom # default
78 f0000000 16MB pcie io # mapped from 0xc0000000 by u-boot
80 f1000000 1MB internal regs as mapped by u-boot
81 f1000000 64K dram regs
82 f1010000 64K uart, flashes, rtc, gpio, etc.
83 f1030000 64K crypto accelerator (cesa)
84 f1040000 64K pci-e regs
85 f1050000 64K usb otg regs (ehci-like)
87 f1080000 64K non-ahci sata regs
88 f1090000 64K sdio regs
90 f8000000 128MB boot device # default, mapped to 0 by u-boot
91 f8000000 16MB spi flash # mapped by u-boot
92 f9000000 8MB nand flash # on sheeva/openrd, mapped by u-boot
93 fb000000 64KB crypto engine
94 ff000000 16MB boot rom # u-boot
99 0 512MB user process address space
101 60000000 kzero, mapped to 0
102 90000000 256MB pcie mem # mapped by u-boot
103 c0000000 64KB pcie i/o # mapped by u-boot
104 ... as per physical map