1 typedef struct Mii Mii;
2 typedef struct MiiPhy MiiPhy;
5 Bmcr = 0, /* Basic Mode Control */
6 Bmsr = 1, /* Basic Mode Status */
7 Phyidr1 = 2, /* PHY Identifier #1 */
8 Phyidr2 = 3, /* PHY Identifier #2 */
9 Anar = 4, /* Auto-Negotiation Advertisement */
10 Anlpar = 5, /* AN Link Partner Ability */
11 Aner = 6, /* AN Expansion */
12 Annptr = 7, /* AN Next Page TX */
13 Annprr = 8, /* AN Next Page RX */
14 Mscr = 9, /* Gb Control */
15 Mssr = 10, /* Gb Status */
16 Esr = 15, /* Extended Status */
18 /* 88e1116-specific paged registers */
19 Scr = 16, /* special control register */
20 Ssr = 17, /* special status register */
21 Ier = 18, /* interrupt enable reg */
22 Isr = 19, /* interrupt status reg */
23 Escr = 20, /* extended special control reg */
24 Recr = 21, /* RX error counter reg */
25 Eadr = 22, /* extended address reg (page select) */
26 Globsts = 23, /* global status */
27 Impover = 24, /* RGMII output impedance override (page 2) */
28 Imptarg = 25, /* RGMII output impedance target (page 2) */
29 Scr2 = 26, /* special control register 2 */
36 BmcrSs1 = 0x0040, /* Speed Select[1] */
37 BmcrCte = 0x0080, /* Collision Test Enable */
38 BmcrDm = 0x0100, /* Duplex Mode */
39 BmcrRan = 0x0200, /* Restart Auto-Negotiation */
40 BmcrI = 0x0400, /* Isolate */
41 BmcrPd = 0x0800, /* Power Down */
42 BmcrAne = 0x1000, /* Auto-Negotiation Enable */
43 BmcrSs0 = 0x2000, /* Speed Select[0] */
44 BmcrLe = 0x4000, /* Loopback Enable */
45 BmcrR = 0x8000, /* Reset */
49 BmsrEc = 0x0001, /* Extended Capability */
50 BmsrJd = 0x0002, /* Jabber Detect */
51 BmsrLs = 0x0004, /* Link Status */
52 BmsrAna = 0x0008, /* Auto-Negotiation Ability */
53 BmsrRf = 0x0010, /* Remote Fault */
54 BmsrAnc = 0x0020, /* Auto-Negotiation Complete */
55 BmsrPs = 0x0040, /* Preamble Suppression Capable */
56 BmsrEs = 0x0100, /* Extended Status */
57 Bmsr100T2HD = 0x0200, /* 100BASE-T2 HD Capable */
58 Bmsr100T2FD = 0x0400, /* 100BASE-T2 FD Capable */
59 Bmsr10THD = 0x0800, /* 10BASE-T HD Capable */
60 Bmsr10TFD = 0x1000, /* 10BASE-T FD Capable */
61 Bmsr100TXHD = 0x2000, /* 100BASE-TX HD Capable */
62 Bmsr100TXFD = 0x4000, /* 100BASE-TX FD Capable */
63 Bmsr100T4 = 0x8000, /* 100BASE-T4 Capable */
66 enum { /* Anar/Anlpar */
67 Ana10HD = 0x0020, /* Advertise 10BASE-T */
68 Ana10FD = 0x0040, /* Advertise 10BASE-T FD */
69 AnaTXHD = 0x0080, /* Advertise 100BASE-TX */
70 AnaTXFD = 0x0100, /* Advertise 100BASE-TX FD */
71 AnaT4 = 0x0200, /* Advertise 100BASE-T4 */
72 AnaP = 0x0400, /* Pause */
73 AnaAP = 0x0800, /* Asymmetrical Pause */
74 AnaRf = 0x2000, /* Remote Fault */
75 AnaAck = 0x4000, /* Acknowledge */
76 AnaNp = 0x8000, /* Next Page Indication */
80 Mscr1000THD = 0x0100, /* Advertise 1000BASE-T HD */
81 Mscr1000TFD = 0x0200, /* Advertise 1000BASE-T FD */
85 Mssr1000THD = 0x0400, /* Link Partner 1000BASE-T HD able */
86 Mssr1000TFD = 0x0800, /* Link Partner 1000BASE-T FD able */
90 Esr1000THD = 0x1000, /* 1000BASE-T HD Capable */
91 Esr1000TFD = 0x2000, /* 1000BASE-T FD Capable */
92 Esr1000XHD = 0x4000, /* 1000BASE-X HD Capable */
93 Esr1000XFD = 0x8000, /* 1000BASE-X FD Capable */
96 enum { /* Scr page 0 */
97 Pwrdown = 0x0004, /* power down */
98 Mdix = 0x0060, /* MDI crossover mode */
99 Endetect = 0x0300, /* energy detect */
101 enum { /* Scr page 2 */
102 Rgmiipwrup = 0x0008, /* RGMII power up: must sw reset after */
105 enum { /* Recr page 2 */
114 MiiPhy* phy[NMiiPhy];
118 int (*mir)(Mii*, int, int);
119 int (*miw)(Mii*, int, int, int);
122 typedef struct MiiPhy {
138 extern int mii(Mii*, int);
139 extern int miiane(Mii*, int, int, int);
140 extern int miimir(Mii*, int);
141 extern int miimiw(Mii*, int, int);
142 extern int miireset(Mii*);
143 extern int miistatus(Mii*);