1 typedef struct Conf Conf;
2 typedef struct Confmem Confmem;
3 typedef struct FPsave FPsave;
4 typedef struct PFPU PFPU;
5 typedef struct ISAConf ISAConf;
6 typedef struct Label Label;
7 typedef struct Lock Lock;
8 typedef struct Memcache Memcache;
9 typedef struct MMMU MMMU;
10 typedef struct Mach Mach;
11 typedef struct Page Page;
12 typedef struct Pcidev Pcidev;
13 typedef struct PhysUart PhysUart;
14 typedef struct PMMU PMMU;
15 typedef struct Proc Proc;
17 typedef struct Soc Soc;
18 typedef struct Uart Uart;
19 typedef struct Ureg Ureg;
22 #pragma incomplete Pcidev
23 #pragma incomplete Ureg
25 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */
28 * parameters for sysproc.c
30 #define AOUT_MAGIC (E_MAGIC)
49 * emulated floating point
59 ulong regs[Nfpctlregs][3];
90 ulong nmach; /* processors */
91 ulong nproc; /* processes */
92 ulong monitor; /* has monitor? */
93 Confmem mem[1]; /* physical memory */
94 ulong npage; /* total physical pages of memory */
95 usize upages; /* user page pool */
96 ulong copymode; /* 0 is copy on write, 1 is copy on reference */
97 ulong ialloc; /* max interrupt time allocation in bytes */
98 ulong pipeqsize; /* size in bytes of pipe queues */
99 ulong nimage; /* number of page cache image headers */
100 ulong nswap; /* number of swap pages */
101 int nswppo; /* max # of pageouts per segment pass */
102 // ulong hz; /* processor cycle freq */
111 PTE* mmul1; /* l1 for this processor */
120 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */
124 Page* mmul2cache; /* free mmu pages */
127 #include "../port/portdat.h"
131 int machno; /* physical id of processor */
132 uintptr splpc; /* pc of last caller to splhi */
134 Proc* proc; /* current process */
137 int flushmmu; /* flush current proc mmu state */
139 ulong ticks; /* of the clock since boot time */
140 Label sched; /* scheduler wakeup */
141 Lock alarmlock; /* access to alarm list */
142 void* alarm; /* alarms bound to this clock */
145 Proc* readied; /* for runproc */
146 ulong schedticks; /* next forced context switch */
149 int socrev; /* system-on-chip revision */
160 vlong fastclock; /* last sampled value */
161 uvlong inidle; /* time spent in idlehands() */
165 Perf perf; /* performance counters */
168 uvlong cpuhz; /* speed of cpu */
169 uvlong cyclefreq; /* Frequency of user readable cycle counter */
171 /* save areas for exceptions */
176 #define fiqstack sfiq
177 #define irqstack sirq
178 #define abtstack sabt
179 #define undstack sund
188 #define VA(k) ((uintptr)(k))
189 #define kmap(p) (KMap*)((p)->pa|kseg0)
194 char machs[MAXMACH]; /* active CPUs */
195 int exiting; /* shutdown */
199 Frequency = 1200*1000*1000, /* the processor clock */
202 extern register Mach* m; /* R10 */
203 extern register Proc* up; /* R9 */
205 extern uintptr kseg0;
206 extern Mach* machaddr[MAXMACH];
209 Nvec = 8, /* # of vectors at start of lexception.s */
213 * Layout of physical 0.
215 typedef struct Vectorpage {
216 void (*vectors[Nvec])(void);
221 * a parsed plan9.ini line
238 #define MACHP(n) (machaddr[n])
241 * Horrid. But the alternative is 'defined'.
244 #define DBGFLG (dbgflg[_DBGC_])
250 extern char dbgflg[256];
252 #define dbgprint print /* for now */
255 * hardware info about a device
264 ulong intnum; /* interrupt number */
265 char *type; /* card type, malloced */
266 int nports; /* Number of ports */
267 Devport *ports; /* The ports themselves */
276 /* characteristics of a given cache level */
278 uint level; /* 1 is nearest processor, 2 further away */
279 uint kind; /* I, D or unified */
282 uint nways; /* associativity */
284 uint linelen; /* bytes per cache line */
288 uint waysh; /* shifts for set/way register */
292 struct Soc { /* addr's of SoC controllers */
297 // uintptr sdramd; /* unused */
303 uintptr cesa; /* crypto accel. */
312 uintptr rtc; /* real-time clock */