2 * SAC/UDA 1341 Audio driver for the Bitsy
4 * The Philips UDA 1341 sound chip is accessed through the Serial Audio
5 * Controller (SAC) of the StrongARM SA-1110. This is much more a SAC
6 * controller than a UDA controller, but we have a devsac.c already.
8 * The code morphs Nicolas Pitre's <nico@cam.org> Linux controller
9 * and Ken's Soundblaster controller.
11 * The interface should be identical to that of devaudio.c
14 #include "../port/lib.h"
18 #include "../port/error.h"
20 #include "sa1110dma.h"
25 * GPIO based L3 bus support.
27 * This provides control of Philips L3 type devices.
28 * GPIO lines are used for clock, data and mode pins.
30 * Note: The L3 pins are shared with I2C devices. This should not present
31 * any problems as long as an I2C start sequence is not generated. This is
32 * defined as a 1->0 transition on the data lines when the clock is high.
33 * It is critical this code only allow data transitions when the clock
34 * is low. This is always legal in L3.
36 * The IIC interface requires the clock and data pin to be LOW when idle. We
37 * must make sure we leave them in this state.
39 * It appears the read data is generated on the falling edge of the clock
40 * and should be held stable during the clock high time.
44 * L3 setup and hold times (expressed in µs)
49 L3_DataSetupTime = (190+999)/1000, /* 190 ns */
50 L3_DataHoldTime = ( 30+999)/1000,
51 L3_ModeSetupTime = (190+999)/1000,
52 L3_ModeHoldTime = (190+999)/1000,
53 L3_ClockHighTime = (100+999)/1000,
54 L3_ClockLowTime = (100+999)/1000,
55 L3_HaltTime = (190+999)/1000,
58 /* UDA 1341 Registers */
60 /* Status0 register */
61 UdaStatusDC = 0, /* 1 bit */
62 UdaStatusIF = 1, /* 3 bits */
63 UdaStatusSC = 4, /* 2 bits */
64 UdaStatusRST = 6, /* 1 bit */
68 /* Status1 register */
69 UdaStatusPC = 0, /* 2 bits */
70 UdaStatusDS = 2, /* 1 bit */
71 UdaStatusPDA = 3, /* 1 bit */
72 UdaStatusPAD = 4, /* 1 bit */
73 UdaStatusIGS = 5, /* 1 bit */
74 UdaStatusOGS = 6, /* 1 bit */
78 * UDA1341 L3 address and command types
85 UDA1341_L3Addr = 0x14,
88 typedef struct AQueue AQueue;
89 typedef struct Buf Buf;
90 typedef struct IOstate IOstate;
118 Bufsize = 4* 1024, /* 46 ms each */
119 Nbuf = 10, /* 1.5 seconds total */
122 Ncmd = 50, /* max volume command words */
126 Flushbuf = 0xe0000000,
129 /* System Clock -- according to the manual, it seems that when the UDA is
130 configured in non MSB/I2S mode, it uses a divisor of 256 to the 12.288MHz
131 clock. The other rates are only supported in MSB mode, which should be
132 implemented at some point */
154 ".", {Qdir, 0, QTDIR}, 0, DMDIR|0555,
155 "audio", {Qaudio}, 0, 0666,
156 "volume", {Qvolume}, 0, 0666,
157 "audiostatus", {Qstatus}, 0, 0444,
158 "audiostats", {Qstats}, 0, 0444,
173 Chan *chan; /* chan of open */
174 int dma; /* dma chan, alloc on open, free on close */
175 int bufinit; /* boolean, if buffers allocated */
176 Buf buf[Nbuf]; /* buffers and queues */
177 volatile Buf *current; /* next dma to finish */
178 volatile Buf *next; /* next candidate for dma */
179 volatile Buf *filling; /* buffer being filled */
180 /* to have defines just like linux — there's a real operating system */
181 #define emptying filling
187 int amode; /* Aclosed/Aread/Awrite for /audio */
188 int intr; /* boolean an interrupt has happened */
189 int rivol[Nvol]; /* right/left input/output volumes */
193 ulong totcount; /* how many bytes processed since open */
194 vlong tottime; /* time at which totcount bytes were processed */
199 int zerodma; /* dma buffer used for sending zero */
201 typedef struct Iostats Iostats;
216 static void setaudio(int in, int out, int left, int right, int value);
217 static void setspeed(int in, int out, int left, int right, int value);
218 static void setbufsize(int in, int out, int left, int right, int value);
224 int ilval; /* initial values */
226 void (*setval)(int, int, int, int, int);
229 [Vaudio] {"audio", Fout|Fmono, 80, 80, setaudio },
230 [Vmic] {"mic", Fin|Fmono, 0, 0, nil },
231 [Vtreb] {"treb", Fout|Fmono, 50, 50, nil },
232 [Vbass] {"bass", Fout|Fmono, 50, 50, nil },
233 [Vspeed] {"speed", Fin|Fout|Fmono, Speed, Speed, setspeed },
234 [Vbufsize] {"bufsize", Fin|Fout|Fmono, Bufsize, Bufsize, setbufsize },
235 [Vfilter] {"filter", Fout|Fmono, 0, 0, nil },
236 [Vinvert] {"invert", Fin|Fout|Fmono, 0, 0, nil },
240 static void setreg(char *name, int val, int n);
243 * Grab control of the IIC/L3 shared pins
248 gpioregs->set = (GPIO_L3_MODE_o | GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
249 gpioregs->direction |= (GPIO_L3_MODE_o | GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
250 microdelay(L3_AcquireTime);
254 * Release control of the IIC/L3 shared pins
259 gpioregs->direction &= ~(GPIO_L3_MODE_o | GPIO_L3_SCLK_o | GPIO_L3_SDA_io);
260 microdelay(L3_ReleaseTime);
264 * Initialize the interface
269 gpioregs->altfunc &= ~(GPIO_L3_SDA_io | GPIO_L3_SCLK_o | GPIO_L3_MODE_o);
274 * Get a bit. The clock is high on entry and on exit. Data is read after
275 * the clock low time has expired.
282 gpioregs->clear = GPIO_L3_SCLK_o;
283 microdelay(L3_ClockLowTime);
285 data = (gpioregs->level & GPIO_L3_SDA_io) ? 1 : 0;
287 gpioregs->set = GPIO_L3_SCLK_o;
288 microdelay(L3_ClockHighTime);
294 * Send a bit. The clock is high on entry and on exit. Data is sent only
295 * when the clock is low (I2C compatibility).
300 gpioregs->clear = GPIO_L3_SCLK_o;
303 gpioregs->set = GPIO_L3_SDA_io;
305 gpioregs->clear = GPIO_L3_SDA_io;
307 /* Assumes L3_DataSetupTime < L3_ClockLowTime */
308 microdelay(L3_ClockLowTime);
310 gpioregs->set = GPIO_L3_SCLK_o;
311 microdelay(L3_ClockHighTime);
315 * Send a byte. The mode line is set or pulsed based on the mode sequence
316 * count. The mode line is high on entry and exit. The mod line is pulsed
317 * before the second data byte and before ech byte thereafter.
320 L3_sendbyte(char data, int mode)
325 case 0: /* Address mode */
326 gpioregs->clear = GPIO_L3_MODE_o;
328 case 1: /* First data byte */
330 default: /* Subsequent bytes */
331 gpioregs->clear = GPIO_L3_MODE_o;
332 microdelay(L3_HaltTime);
333 gpioregs->set = GPIO_L3_MODE_o;
337 microdelay(L3_ModeSetupTime);
339 for (i = 0; i < 8; i++)
340 L3_sendbit(data >> i);
342 if (mode == 0) /* Address mode */
343 gpioregs->set = GPIO_L3_MODE_o;
345 microdelay(L3_ModeHoldTime);
349 * Get a byte. The mode line is set or pulsed based on the mode sequence
350 * count. The mode line is high on entry and exit. The mod line is pulsed
351 * before the second data byte and before each byte thereafter. This
352 * function is never valid with mode == 0 (address cycle) as the address
353 * is always sent on the bus, not read.
362 case 0: /* Address mode - never valid */
364 case 1: /* First data byte */
366 default: /* Subsequent bytes */
367 gpioregs->clear = GPIO_L3_MODE_o;
368 microdelay(L3_HaltTime);
369 gpioregs->set = GPIO_L3_MODE_o;
373 microdelay(L3_ModeSetupTime);
375 for (i = 0; i < 8; i++)
376 data |= (L3_getbit() << i);
378 microdelay(L3_ModeHoldTime);
384 * Write data to a device on the L3 bus. The address is passed as well as
385 * the data and length. The length written is returned. The register space
386 * is encoded in the address (low two bits are set and device address is
387 * in the upper 6 bits).
390 L3_write(uchar addr, uchar *data, int len)
396 L3_sendbyte(addr, mode++);
398 L3_sendbyte(*data++, mode++);
404 * Read data from a device on the L3 bus. The address is passed as well as
405 * the data and length. The length read is returned. The register space
406 * is encoded in the address (low two bits are set and device address is
407 * in the upper 6 bits).
409 * Commented out, not used
411 L3_read(uchar addr, uchar *data, int len)
417 L3_sendbyte(addr, mode++);
418 gpioregs->direction &= ~(GPIO_L3_SDA_io);
420 *data++ = L3_getbyte(mode++);
429 egpiobits(EGPIO_audio_mute, on);
432 static char Emode[] = "illegal open mode";
433 static char Evolume[] = "illegal volume specifier";
440 if (debug) print("bufinit\n");
441 for (i = 0; i < Nbuf; i++) {
442 b->buf[i].virt = xalloc(Bufsize);
443 b->buf[i].phys = PADDR(b->buf[i].virt);
444 memset(b->buf[i].virt, 0xAA, Bufsize);
454 if (debug) print("setempty\n");
455 for (i = 0; i < Nbuf; i++) {
456 b->buf[i].nbytes = 0;
464 audioqnotempty(void *x)
468 return dmaidle(s->dma) || s->emptying != s->current;
472 audioqnotfull(void *x)
476 return dmaidle(s->dma) || s->filling != s->current;
485 /* Turn MCP operations off */
486 mcpregs = mapspecial(MCPREGS, sizeof(MCPregs));
487 mcpregs->status &= ~(1<<16);
489 sspregs = mapspecial(SSPREGS, sizeof(SSPregs));
493 uchar status0[1] = {0x02};
494 uchar status1[1] = {0x80};
495 uchar data00[1] = {0x00}; /* volume control, bits 0 – 5 */
496 uchar data01[1] = {0x40};
497 uchar data02[1] = {0x80};
498 uchar data0e0[2] = {0xc0, 0xe0};
499 uchar data0e1[2] = {0xc1, 0xe0};
500 uchar data0e2[2] = {0xc2, 0xf2};
501 /* there is no data0e3 */
502 uchar data0e4[2] = {0xc4, 0xe0};
503 uchar data0e5[2] = {0xc5, 0xe0};
504 uchar data0e6[2] = {0xc6, 0xe3};
513 /* Setup the uarts */
514 ppcregs->assignment &= ~(1<<18);
516 sspregs->control0 = 0;
517 sspregs->control0 = 0x031f; /* 16 bits, TI frames, serial clock rate 3 */
518 sspregs->control1 = 0x0020; /* ext clock */
519 sspregs->control0 = 0x039f; /* enable */
521 /* Enable the audio power */
523 egpiobits(EGPIO_codec_reset, 1);
525 setspeed(0, 0, 0, 0, volumes[Vspeed].ilval);
527 data[0] = status0[0] | 1 << UdaStatusRST;
528 L3_write(UDA1341_L3Addr | UDA1341_STATUS, data, 1 );
529 gpioregs->clear = EGPIO_codec_reset;
530 gpioregs->set = EGPIO_codec_reset;
531 /* write uda 1341 status[0] */
532 data[0] = status0[0];
533 L3_write(UDA1341_L3Addr | UDA1341_STATUS, data, 1);
536 print("enable: status0 = 0x%2.2ux\n", data[0]);
538 L3_write(UDA1341_L3Addr | UDA1341_STATUS, status1, 1);
539 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data02, 1);
540 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data0e2, 2);
541 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data0e6, 2 );
544 print("enable: status0 = 0x%2.2ux\n", data[0]);
545 print("enable: status1 = 0x%2.2ux\n", status1[0]);
546 print("enable: data02 = 0x%2.2ux\n", data02[0]);
547 print("enable: data0e2 = 0x%4.4ux\n", data0e2[0] | data0e2[1]<<8);
548 print("enable: data0e4 = 0x%4.4ux\n", data0e4[0] | data0e4[1]<<8);
549 print("enable: data0e6 = 0x%4.4ux\n", data0e6[0] | data0e6[1]<<8);
550 print("enable: sspregs->control0 = 0x%lux\n", sspregs->control0);
551 print("enable: sspregs->control1 = 0x%lux\n", sspregs->control1);
560 for(i=0; volumes[i].name; i++) {
561 audio.lovol[i] = volumes[i].ilval;
562 audio.rovol[i] = volumes[i].irval;
563 audio.livol[i] = volumes[i].ilval;
564 audio.rivol[i] = volumes[i].irval;
572 setspeed(0, 0, 0, 0, volumes[Vspeed].ilval);
573 if (!dmaidle(audio.i.dma) || !dmaidle(audio.o.dma))
574 L3_write(UDA1341_L3Addr | UDA1341_STATUS, status0, 1);
576 if(audio.amode & Aread){
579 if (left[Vmic]+right[Vmic] == 0) {
580 /* Turn on automatic gain control (AGC) */
582 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data0e4, 2 );
585 /* Turn on manual gain control */
586 v = ((left[Vmic]+right[Vmic])*0x7f/200)&0x7f;
589 data0e4[1] |= v & 0x3;
590 data0e5[0] |= (v & 0x7c)<<6;
591 data0e5[1] |= (v & 0x7c)>>2;
592 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data0e4, 2 );
593 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data0e5, 2 );
595 if (left[Vinvert]+right[Vinvert] == 0)
599 L3_write(UDA1341_L3Addr | UDA1341_STATUS, status1, 1);
601 print("mxvolume: status1 = 0x%2.2ux\n", status1[0]);
602 print("mxvolume: data0e4 = 0x%4.4ux\n", data0e4[0]|data0e4[0]<<8);
603 print("mxvolume: data0e5 = 0x%4.4ux\n", data0e5[0]|data0e5[0]<<8);
606 if(audio.amode & Awrite){
610 data00[0] |= ((200-left[Vaudio]-right[Vaudio])*0x3f/200)&0x3f;
611 if (left[Vtreb]+right[Vtreb] <= 100
612 && left[Vbass]+right[Vbass] <= 100)
613 /* settings neutral */
618 data01[0] |= ((left[Vtreb]+right[Vtreb]-100)*0x3/100)&0x03;
619 data01[0] |= (((left[Vbass]+right[Vbass]-100)*0xf/100)&0xf)<<2;
621 if (left[Vfilter]+right[Vfilter] == 0)
625 if (left[Vinvert]+right[Vinvert] == 0)
629 L3_write(UDA1341_L3Addr | UDA1341_STATUS, status1, 1);
630 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data00, 1);
631 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data01, 1);
632 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data02, 1);
634 print("mxvolume: status1 = 0x%2.2ux\n", status1[0]);
635 print("mxvolume: data00 = 0x%2.2ux\n", data00[0]);
636 print("mxvolume: data01 = 0x%2.2ux\n", data01[0]);
637 print("mxvolume: data02 = 0x%2.2ux\n", data02[0]);
643 setreg(char *name, int val, int n)
651 if(strcmp(name, "pause") == 0){
652 for(i = 0; i < n; i++)
665 if(strcmp(name, "status") == 0){
666 L3_write(UDA1341_L3Addr | UDA1341_STATUS, x, n);
667 } else if(strcmp(name, "data0") == 0){
668 L3_write(UDA1341_L3Addr | UDA1341_DATA0, x, n);
669 } else if(strcmp(name, "data1") == 0){
670 L3_write(UDA1341_L3Addr | UDA1341_DATA1, x, n);
677 /* turn on DAC, set output gain switch */
681 L3_write(UDA1341_L3Addr | UDA1341_STATUS, status1, 1);
684 L3_write(UDA1341_L3Addr | UDA1341_DATA0, data00, 1);
686 print("outenable: status1 = 0x%2.2ux\n", status1[0]);
687 print("outenable: data00 = 0x%2.2ux\n", data00[0]);
693 dmastop(audio.o.dma);
694 /* turn off DAC, clear output gain switch */
697 L3_write(UDA1341_L3Addr | UDA1341_STATUS, status1, 1);
699 print("outdisable: status1 = 0x%2.2ux\n", status1[0]);
706 /* turn on ADC, set input gain switch */
708 L3_write(UDA1341_L3Addr | UDA1341_STATUS, status1, 1);
710 print("inenable: status1 = 0x%2.2ux\n", status1[0]);
716 dmastop(audio.i.dma);
717 /* turn off ADC, clear input gain switch */
719 L3_write(UDA1341_L3Addr | UDA1341_STATUS, status1, 1);
721 print("indisable: status1 = 0x%2.2ux\n", status1[0]);
726 sendaudio(IOstate *s) {
727 /* interrupt routine calls this too */
730 if (debug > 1) print("#A: sendaudio\n");
732 if ((audio.amode & Aread) && s->next == s->filling && dmaidle(s->dma)) {
733 // send an empty buffer to provide an input clock
734 zerodma |= dmastart(s->dma, Flushbuf, volumes[Vbufsize].ilval) & 0xff;
736 if (debug) print("emptyfail\n");
737 iostats.tx.empties++;
741 while (s->next != s->filling) {
742 s->next->nbytes &= ~0x3; /* must be a multiple of 4 */
743 if(s->next->nbytes) {
744 if ((n = dmastart(s->dma, s->next->phys, s->next->nbytes)) == 0) {
745 iostats.tx.faildma++;
748 iostats.tx.totaldma++;
751 iostats.tx.idledma++;
754 iostats.tx.faildma++;
759 print("dmastart @%p\n", s->next);
766 if (s->next == &s->buf[Nbuf])
767 s->next = &s->buf[0];
773 recvaudio(IOstate *s) {
774 /* interrupt routine calls this too */
777 if (debug > 1) print("#A: recvaudio\n");
779 while (s->next != s->emptying) {
780 assert(s->next->nbytes == 0);
781 if ((n = dmastart(s->dma, s->next->phys, volumes[Vbufsize].ilval)) == 0) {
782 iostats.rx.faildma++;
785 iostats.rx.totaldma++;
788 iostats.rx.idledma++;
791 iostats.rx.faildma++;
796 print("dmastart @%p\n", s->next);
801 if (s->next == &s->buf[Nbuf])
802 s->next = &s->buf[0];
808 audiopower(int flag) {
812 iprint("audiopower %d\n", flag);
815 /* power on only when necessary */
819 egpiobits(EGPIO_codec_reset, 1);
821 if (audio.amode & Aread) {
824 dmareset(s->dma, 1, 0, 4, 2, SSPRecvDMA, Port4SSP);
827 if (audio.amode & Awrite) {
830 dmareset(s->dma, 0, 0, 4, 2, SSPXmitDMA, Port4SSP);
837 if (audio.amode & Aread)
839 if (audio.amode & Awrite)
841 egpiobits(EGPIO_codec_reset, 0);
848 audiointr(void *x, ulong ndma) {
853 iprint("#A: audio interrupt @%p\n", s->current);
857 if (s == &audio.i || (ndma & ~zerodma)) {
858 /* A dma, not of a zero buffer completed, update current
859 * Only interrupt routine touches s->current
861 s->current->nbytes = (s == &audio.i)? volumes[Vbufsize].ilval: 0;
863 if (s->current == &s->buf[Nbuf])
864 s->current = &s->buf[0];
870 } else if (s == &audio.i)
877 audioattach(char *param)
879 return devattach('A', param);
883 audiowalk(Chan *c, Chan *nc, char **name, int nname)
885 return devwalk(c, nc, name, nname, audiodir, nelem(audiodir), devgen);
889 audiostat(Chan *c, uchar *db, int n)
891 return devstat(c, db, n, audiodir, nelem(audiodir), devgen);
895 audioopen(Chan *c, int mode)
900 switch((ulong)c->qid.path) {
907 if((omode&7) != OREAD)
914 omode = (omode & 0x7) + 1;
915 if (omode & ~(Aread | Awrite))
918 if(audio.amode & omode){
923 memset(&iostats, 0, sizeof(iostats));
930 s->emptying = &s->buf[Nbuf-1];
932 s->dma = dmaalloc(1, 0, 4, 2, SSPRecvDMA, Port4SSP, audiointr, (void*)s);
933 audio.amode |= Aread;
935 if (omode & (Aread|Awrite) && (audio.amode & Awrite) == 0) {
941 s->dma = dmaalloc(0, 0, 4, 2, SSPXmitDMA, Port4SSP, audiointr, (void*)s);
943 if (omode & Awrite) {
944 audio.amode |= Awrite;
948 if (audio.amode & Aread)
952 if (debug) print("open done\n");
955 c = devopen(c, mode, audiodir, nelem(audiodir), devgen);
956 c->mode = openmode(mode);
968 switch((ulong)c->qid.path) {
980 if (debug > 1) print("#A: close\n");
981 if(c->flag & COPEN) {
983 if (audio.i.chan == c) {
984 /* closing the read end */
985 audio.amode &= ~Aread;
992 if ((audio.amode & Awrite) == 0) {
1005 if (audio.o.chan == c) {
1006 /* closing the write end */
1007 audio.amode &= ~Awrite;
1010 if (s->filling->nbytes) {
1011 /* send remaining partial buffer */
1013 if (s->filling == &s->buf[Nbuf])
1014 s->filling = &s->buf[0];
1023 if ((audio.amode & Aread) == 0)
1027 if (audio.amode == 0) {
1028 /* turn audio off */
1029 egpiobits(EGPIO_codec_reset, 0);
1039 audioread(Chan *c, void *v, long n, vlong off)
1041 int liv, riv, lov, rov;
1051 switch((ulong)c->qid.path) {
1057 return devdirread(c, p, n, audiodir, nelem(audiodir), devgen);
1060 if (debug > 1) print("#A: read %ld\n", n);
1061 if((audio.amode & Aread) == 0)
1070 if(s->emptying->nbytes == 0) {
1071 if (debug > 1) print("#A: emptied @%p\n", s->emptying);
1074 if (s->emptying == &s->buf[Nbuf])
1075 s->emptying = s->buf;
1077 /* wait if dma in progress */
1078 while (!dmaidle(s->dma) && s->emptying == s->current) {
1079 if (debug > 1) print("#A: sleep\n");
1080 sleep(&s->vous, audioqnotempty, s);
1083 m = (s->emptying->nbytes > n)? n: s->emptying->nbytes;
1084 memmove(p, s->emptying->virt + volumes[Vbufsize].ilval -
1085 s->emptying->nbytes, m);
1087 s->emptying->nbytes -= m;
1097 snprint(buf, sizeof(buf), "bytes %lud\ntime %lld\n",
1098 audio.totcount, audio.tottime);
1099 return readstr(offset, p, n, buf);
1103 snprint(buf, sizeof(buf),
1104 "bytes %lud\nRX dmas %lud, while idle %lud, while busy %lud, "
1105 "out-of-order %lud, empty dmas %lud\n"
1106 "TX dmas %lud, while idle %lud, while busy %lud, "
1107 "out-of-order %lud, empty dmas %lud\n",
1108 iostats.bytes, iostats.rx.totaldma, iostats.rx.idledma,
1109 iostats.rx.faildma, iostats.rx.samedma, iostats.rx.empties,
1110 iostats.tx.totaldma, iostats.tx.idledma,
1111 iostats.tx.faildma, iostats.tx.samedma, iostats.tx.empties);
1113 return readstr(offset, p, n, buf);
1118 for(m=0; volumes[m].name; m++){
1120 liv = audio.livol[m];
1121 riv = audio.rivol[m];
1122 lov = audio.lovol[m];
1123 rov = audio.rovol[m];
1126 lov = liv = volumes[m].ilval;
1127 rov = riv = volumes[m].irval;
1130 j += snprint(buf+j, sizeof(buf)-j, "%s", volumes[m].name);
1131 if((volumes[m].flag & Fmono) || liv==riv && lov==rov){
1132 if((volumes[m].flag&(Fin|Fout))==(Fin|Fout) && liv==lov)
1133 j += snprint(buf+j, sizeof(buf)-j, " %d", liv);
1135 if(volumes[m].flag & Fin)
1136 j += snprint(buf+j, sizeof(buf)-j,
1138 if(volumes[m].flag & Fout)
1139 j += snprint(buf+j, sizeof(buf)-j,
1143 if((volumes[m].flag&(Fin|Fout))==(Fin|Fout) &&
1144 liv==lov && riv==rov)
1145 j += snprint(buf+j, sizeof(buf)-j,
1146 " left %d right %d",
1149 if(volumes[m].flag & Fin)
1150 j += snprint(buf+j, sizeof(buf)-j,
1151 " in left %d right %d",
1153 if(volumes[m].flag & Fout)
1154 j += snprint(buf+j, sizeof(buf)-j,
1155 " out left %d right %d",
1159 j += snprint(buf+j, sizeof(buf)-j, "\n");
1161 return readstr(offset, p, n, buf);
1167 setaudio(int in, int out, int left, int right, int value)
1169 if (value < 0 || value > 100)
1172 audio.lovol[Vaudio] = value;
1174 audio.livol[Vaudio] = value;
1176 audio.rovol[Vaudio] = value;
1178 audio.rivol[Vaudio] = value;
1182 setspeed(int, int, int, int, int speed)
1186 /* external clock configured for 44100 samples/sec */
1190 gpioregs->clear = GPIO_CLK_SET0_o|GPIO_CLK_SET1_o;
1191 clock = SC384FS; /* Only works in MSB mode! */
1195 gpioregs->clear = GPIO_CLK_SET0_o|GPIO_CLK_SET1_o;
1202 gpioregs->set = GPIO_CLK_SET0_o;
1203 gpioregs->clear = GPIO_CLK_SET1_o;
1208 gpioregs->set = GPIO_CLK_SET1_o;
1209 gpioregs->clear = GPIO_CLK_SET0_o;
1210 clock = SC512FS; /* Only works in MSB mode! */
1214 gpioregs->set = GPIO_CLK_SET1_o;
1215 gpioregs->clear = GPIO_CLK_SET0_o;
1220 gpioregs->set = GPIO_CLK_SET0_o|GPIO_CLK_SET1_o;
1221 clock = SC512FS; /* Only works in MSB mode! */
1225 gpioregs->set = GPIO_CLK_SET0_o|GPIO_CLK_SET1_o;
1230 /* Wait for the UDA1341 to wake up */
1233 /* Reset the chip */
1234 status0[0] &= ~CLOCKMASK;
1237 volumes[Vspeed].ilval = speed;
1241 setbufsize(int, int, int, int, int value)
1243 if ((value % 8) != 0 || value < 8 || value >= Bufsize)
1245 volumes[Vbufsize].ilval = value;
1249 audiowrite(Chan *c, void *vp, long n, vlong)
1252 int i, v, left, right, in, out;
1259 switch((ulong)c->qid.path) {
1270 cb = parsecmd(p, n);
1276 for(i = 0; i < cb->nf; i++){
1278 * a number is volume
1280 if(cb->f[i][0] >= '0' && cb->f[i][0] <= '9') {
1281 m = strtoul(cb->f[i], 0, 10);
1282 if (volumes[v].setval)
1283 volumes[v].setval(in, out, left, right, m);
1287 for(m=0; volumes[m].name; m++) {
1288 if(strcmp(cb->f[i], volumes[m].name) == 0) {
1298 if(strcmp(cb->f[i], "reset") == 0) {
1302 if(strcmp(cb->f[i], "debug") == 0) {
1306 if(strcmp(cb->f[i], "in") == 0) {
1311 if(strcmp(cb->f[i], "out") == 0) {
1316 if(strcmp(cb->f[i], "left") == 0) {
1321 if(strcmp(cb->f[i], "right") == 0) {
1326 if(strcmp(cb->f[i], "reg") == 0) {
1329 setreg(cb->f[1], atoi(cb->f[2]), cb->nf == 4 ? atoi(cb->f[3]):1);
1342 if (debug > 1) print("#A: write %ld\n", n);
1343 if((audio.amode & Awrite) == 0)
1352 /* wait if dma in progress */
1353 while (!dmaidle(a->dma) && !zerodma && a->filling == a->current) {
1354 if (debug > 1) print("#A: sleep\n");
1355 sleep(&a->vous, audioqnotfull, a);
1357 m = volumes[Vbufsize].ilval - a->filling->nbytes;
1360 memmove(a->filling->virt + a->filling->nbytes, p, m);
1362 a->filling->nbytes += m;
1365 if(a->filling->nbytes >= volumes[Vbufsize].ilval) {
1366 if (debug > 1) print("#A: filled @%p\n", a->filling);
1368 if (a->filling == &a->buf[Nbuf])
1369 a->filling = a->buf;
1380 Dev uda1341devtab = {