sys/src/9/bcm64/sdhc.c

   1 /*
   2  * bcm2711 sd host controller
   3  *
   4  * Copyright © 2012,2019 Richard Miller <r.miller@acm.org>
   5  *
   6  * adapted from emmc.c - the two should really be merged
   7  */
   8
   9 #include "u.h"
  10 #include "../port/lib.h"
  11 #include "../port/error.h"
  12 #include "mem.h"
  13 #include "dat.h"
  14 #include "fns.h"
  15 #include "io.h"
  16 #include "../port/sd.h"
  17
  18 #define EMMCREGS        (VIRTIO+0x340000)
  19
  20 enum {
  21         Extfreq         = 100*Mhz,      /* guess external clock frequency if */
  22                                         /* not available from vcore */
  23         Initfreq        = 400000,       /* initialisation frequency for MMC */
  24         SDfreq          = 25*Mhz,       /* standard SD frequency */
  25         SDfreqhs        = 50*Mhz,       /* high speed frequency */
  26         DTO             = 14,           /* data timeout exponent (guesswork) */
  27
  28         GoIdle          = 0,            /* mmc/sdio go idle state */
  29         MMCSelect       = 7,            /* mmc/sd card select command */
  30         Setbuswidth     = 6,            /* mmc/sd set bus width command */
  31         Switchfunc      = 6,            /* mmc/sd switch function command */
  32         Voltageswitch = 11,             /* md/sdio switch to 1.8V */
  33         IORWdirect = 52,                /* sdio read/write direct command */
  34         IORWextended = 53,              /* sdio read/write extended command */
  35         Appcmd = 55,                    /* mmc/sd application command prefix */
  36 };
  37
  38 enum {
  39         /* Controller registers */
  40         SDMAaddr                = 0x00>>2,
  41         Blksizecnt              = 0x04>>2,
  42         Arg1                    = 0x08>>2,
  43         Cmdtm                   = 0x0c>>2,
  44         Resp0                   = 0x10>>2,
  45         Resp1                   = 0x14>>2,
  46         Resp2                   = 0x18>>2,
  47         Resp3                   = 0x1c>>2,
  48         Data                    = 0x20>>2,
  49         Status                  = 0x24>>2,
  50         Control0                = 0x28>>2,
  51         Control1                = 0x2c>>2,
  52         Interrupt               = 0x30>>2,
  53         Irptmask                = 0x34>>2,
  54         Irpten                  = 0x38>>2,
  55         Control2                = 0x3c>>2,
  56         Capability              = 0x40>>2,
  57         Forceirpt               = 0x50>>2,
  58         Dmadesc                 = 0x58>>2,
  59         Boottimeout             = 0x70>>2,
  60         Dbgsel                  = 0x74>>2,
  61         Exrdfifocfg             = 0x80>>2,
  62         Exrdfifoen              = 0x84>>2,
  63         Tunestep                = 0x88>>2,
  64         Tunestepsstd            = 0x8c>>2,
  65         Tunestepsddr            = 0x90>>2,
  66         Spiintspt               = 0xf0>>2,
  67         Slotisrver              = 0xfc>>2,
  68
  69         /* Control0 */
  70         Busvoltage              = 7<<9,
  71                 V1_8            = 5<<9,
  72                 V3_0            = 6<<9,
  73                 V3_3            = 7<<9,
  74         Buspower                = 1<<8,
  75         Dwidth8                 = 1<<5,
  76         Dmaselect               = 3<<3,
  77                 DmaSDMA         = 0<<3,
  78                 DmaADMA1        = 1<<3,
  79                 DmaADMA2        = 2<<3,
  80         Hispeed                 = 1<<2,
  81         Dwidth4                 = 1<<1,
  82         Dwidth1                 = 0<<1,
  83         LED                     = 1<<0,
  84
  85         /* Control1 */
  86         Srstdata                = 1<<26,        /* reset data circuit */
  87         Srstcmd                 = 1<<25,        /* reset command circuit */
  88         Srsthc                  = 1<<24,        /* reset complete host controller */
  89         Datatoshift             = 16,           /* data timeout unit exponent */
  90         Datatomask              = 0xF0000,
  91         Clkfreq8shift           = 8,            /* SD clock base divider LSBs */
  92         Clkfreq8mask            = 0xFF00,
  93         Clkfreqms2shift         = 6,            /* SD clock base divider MSBs */
  94         Clkfreqms2mask          = 0xC0,
  95         Clkgendiv               = 0<<5,         /* SD clock divided */
  96         Clkgenprog              = 1<<5,         /* SD clock programmable */
  97         Clken                   = 1<<2,         /* SD clock enable */
  98         Clkstable               = 1<<1,
  99         Clkintlen               = 1<<0,         /* enable internal EMMC clocks */
 100
 101         /* Cmdtm */
 102         Indexshift              = 24,
 103         Suspend                 = 1<<22,
 104         Resume                  = 2<<22,
 105         Abort                   = 3<<22,
 106         Isdata                  = 1<<21,
 107         Ixchken                 = 1<<20,
 108         Crcchken                = 1<<19,
 109         Respmask                = 3<<16,
 110         Respnone                = 0<<16,
 111         Resp136                 = 1<<16,
 112         Resp48                  = 2<<16,
 113         Resp48busy              = 3<<16,
 114         Multiblock              = 1<<5,
 115         Host2card               = 0<<4,
 116         Card2host               = 1<<4,
 117         Autocmd12               = 1<<2,
 118         Autocmd23               = 2<<2,
 119         Blkcnten                = 1<<1,
 120         Dmaen                   = 1<<0,
 121
 122         /* Interrupt */
 123         Admaerr         = 1<<25,
 124         Acmderr         = 1<<24,
 125         Denderr         = 1<<22,
 126         Dcrcerr         = 1<<21,
 127         Dtoerr          = 1<<20,
 128         Cbaderr         = 1<<19,
 129         Cenderr         = 1<<18,
 130         Ccrcerr         = 1<<17,
 131         Ctoerr          = 1<<16,
 132         Err             = 1<<15,
 133         Cardintr        = 1<<8,
 134         Cardinsert      = 1<<6,         /* not in Broadcom datasheet */
 135         Readrdy         = 1<<5,
 136         Writerdy        = 1<<4,
 137         Dmaintr         = 1<<3,
 138         Datadone        = 1<<1,
 139         Cmddone         = 1<<0,
 140
 141         /* Status */
 142         Bufread         = 1<<11,        /* not in Broadcom datasheet */
 143         Bufwrite        = 1<<10,        /* not in Broadcom datasheet */
 144         Readtrans       = 1<<9,
 145         Writetrans      = 1<<8,
 146         Datactive       = 1<<2,
 147         Datinhibit      = 1<<1,
 148         Cmdinhibit      = 1<<0,
 149 };
 150
 151 static int cmdinfo[64] = {
 152 [0]  Ixchken,
 153 [2]  Resp136,
 154 [3]  Resp48 | Ixchken | Crcchken,
 155 [5]  Resp48,
 156 [6]  Resp48 | Ixchken | Crcchken,
 157 [7]  Resp48busy | Ixchken | Crcchken,
 158 [8]  Resp48 | Ixchken | Crcchken,
 159 [9]  Resp136,
 160 [11] Resp48 | Ixchken | Crcchken,
 161 [12] Resp48busy | Ixchken | Crcchken,
 162 [13] Resp48 | Ixchken | Crcchken,
 163 [16] Resp48,
 164 [17] Resp48 | Isdata | Card2host | Ixchken | Crcchken,
 165 [18] Resp48 | Isdata | Card2host | Multiblock | Blkcnten | Ixchken | Crcchken,
 166 [24] Resp48 | Isdata | Host2card | Ixchken | Crcchken,
 167 [25] Resp48 | Isdata | Host2card | Multiblock | Blkcnten | Ixchken | Crcchken,
 168 [41] Resp48,
 169 [52] Resp48 | Ixchken | Crcchken,
 170 [53] Resp48     | Ixchken | Crcchken | Isdata,
 171 [55] Resp48 | Ixchken | Crcchken,
 172 };
 173
 174 typedef struct Adma Adma;
 175 typedef struct Ctlr Ctlr;
 176
 177 /*
 178  * ADMA2 descriptor
 179  *      See SD Host Controller Simplified Specification Version 2.00
 180  */
 181
 182 struct Adma {
 183         u32int  desc;
 184         u32int  addr;
 185 };
 186
 187 enum {
 188         /* desc fields */
 189         Valid           = 1<<0,
 190         End                     = 1<<1,
 191         Int                     = 1<<2,
 192         Nop                     = 0<<4,
 193         Tran            = 2<<4,
 194         Link            = 3<<4,
 195         OLength         = 16,
 196         /* maximum value for Length field */
 197         Maxdma          = ((1<<16) - 4),
 198 };
 199
 200 struct Ctlr {
 201         Rendez  r;
 202         Rendez  cardr;
 203         int     fastclock;
 204         ulong   extclk;
 205         int     appcmd;
 206         Adma    *dma;
 207 };
 208
 209 static Ctlr emmc;
 210
 211 static void mmcinterrupt(Ureg*, void*);
 212
 213 static void
 214 WR(int reg, u32int val)
 215 {
 216         u32int *r = (u32int*)EMMCREGS;
 217
 218         if(0)print("WR %2.2ux %ux\n", reg<<2, val);
 219         coherence();
 220         r[reg] = val;
 221 }
 222
 223 static uint
 224 clkdiv(uint d)
 225 {
 226         uint v;
 227
 228         assert(d < 1<<10);
 229         v = (d << Clkfreq8shift) & Clkfreq8mask;
 230         v |= ((d >> 8) << Clkfreqms2shift) & Clkfreqms2mask;
 231         return v;
 232 }
 233
 234 static Adma*
 235 dmaalloc(void *addr, int len)
 236 {
 237         int n;
 238         uintptr a;
 239         Adma *adma, *p;
 240
 241         a = (uintptr)addr;
 242         n = (len + Maxdma-1) / Maxdma;
 243         adma = sdmalloc(n * sizeof(Adma));
 244         for(p = adma; len > 0; p++){
 245                 p->desc = Valid | Tran;
 246                 if(n == 1)
 247                         p->desc |= len<<OLength | End | Int;
 248                 else
 249                         p->desc |= Maxdma<<OLength;
 250                 p->addr = dmaaddr((void*)a);
 251                 a += Maxdma;
 252                 len -= Maxdma;
 253                 n--;
 254         }
 255         cachedwbse(adma, (char*)p - (char*)adma);
 256         return adma;
 257 }
 258
 259 static void
 260 emmcclk(uint freq)
 261 {
 262         u32int *r;
 263         uint div;
 264         int i;
 265
 266         r = (u32int*)EMMCREGS;
 267         div = emmc.extclk / (freq<<1);
 268         if(emmc.extclk / (div<<1) > freq)
 269                 div++;
 270         WR(Control1, clkdiv(div) |
 271                 DTO<<Datatoshift | Clkgendiv | Clken | Clkintlen);
 272         for(i = 0; i < 1000; i++){
 273                 delay(1);
 274                 if(r[Control1] & Clkstable)
 275                         break;
 276         }
 277         if(i == 1000)
 278                 print("emmc: can't set clock to %ud\n", freq);
 279 }
 280
 281 static int
 282 datadone(void*)
 283 {
 284         int i;
 285
 286         u32int *r = (u32int*)EMMCREGS;
 287         i = r[Interrupt];
 288         return i & (Datadone|Err);
 289 }
 290
 291 static int
 292 emmcinit(void)
 293 {
 294         u32int *r;
 295         ulong clk;
 296
 297         clk = getclkrate(ClkEmmc2);
 298         if(clk == 0){
 299                 clk = Extfreq;
 300                 print("emmc: assuming external clock %lud Mhz\n", clk/1000000);
 301         }
 302         emmc.extclk = clk;
 303         r = (u32int*)EMMCREGS;
 304         if(0)print("emmc control %8.8ux %8.8ux %8.8ux\n",
 305                 r[Control0], r[Control1], r[Control2]);
 306         WR(Control1, Srsthc);
 307         delay(10);
 308         while(r[Control1] & Srsthc)
 309                 ;
 310         WR(Control1, Srstdata);
 311         delay(10);
 312         WR(Control1, 0);
 313         return 0;
 314 }
 315
 316 static int
 317 emmcinquiry(char *inquiry, int inqlen)
 318 {
 319         u32int *r;
 320         uint ver;
 321
 322         r = (u32int*)EMMCREGS;
 323         ver = r[Slotisrver] >> 16;
 324         return snprint(inquiry, inqlen,
 325                 "BCM SD Host Controller %2.2x Version %2.2x",
 326                 ver&0xFF, ver>>8);
 327 }
 328
 329 static void
 330 emmcenable(void)
 331 {
 332
 333         WR(Control0, 0);
 334         delay(1);
 335         WR(Control0, V3_3 | Buspower | Dwidth1 | DmaADMA2);
 336         WR(Control1, 0);
 337         delay(1);
 338         emmcclk(Initfreq);
 339         WR(Irpten, 0);
 340         WR(Irptmask, ~(Cardintr|Dmaintr));
 341         WR(Interrupt, ~0);
 342         intrenable(IRQmmc, mmcinterrupt, nil, BUSUNKNOWN, "sdhc");
 343 }
 344
 345 static int
 346 emmccmd(u32int cmd, u32int arg, u32int *resp)
 347 {
 348         u32int *r;
 349         u32int c;
 350         int i;
 351         ulong now;
 352
 353         r = (u32int*)EMMCREGS;
 354         assert(cmd < nelem(cmdinfo) && cmdinfo[cmd] != 0);
 355         c = (cmd << Indexshift) | cmdinfo[cmd];
 356         /*
 357          * CMD6 may be Setbuswidth or Switchfunc depending on Appcmd prefix
 358          */
 359         if(cmd == Switchfunc && !emmc.appcmd)
 360                 c |= Isdata|Card2host;
 361         if(c & Isdata)
 362                 c |= Dmaen;
 363         if(cmd == IORWextended){
 364                 if(arg & (1<<31))
 365                         c |= Host2card;
 366                 else
 367                         c |= Card2host;
 368                 if((r[Blksizecnt]&0xFFFF0000) != 0x10000)
 369                         c |= Multiblock | Blkcnten;
 370         }
 371         /*
 372          * GoIdle indicates new card insertion: reset bus width & speed
 373          */
 374         if(cmd == GoIdle){
 375                 WR(Control0, r[Control0] & ~(Dwidth4|Hispeed));
 376                 emmcclk(Initfreq);
 377         }
 378         if(r[Status] & Cmdinhibit){
 379                 print("emmccmd: need to reset Cmdinhibit intr %ux stat %ux\n",
 380                         r[Interrupt], r[Status]);
 381                 WR(Control1, r[Control1] | Srstcmd);
 382                 while(r[Control1] & Srstcmd)
 383                         ;
 384                 while(r[Status] & Cmdinhibit)
 385                         ;
 386         }
 387         if((r[Status] & Datinhibit) &&
 388            ((c & Isdata) || (c & Respmask) == Resp48busy)){
 389                 print("emmccmd: need to reset Datinhibit intr %ux stat %ux\n",
 390                         r[Interrupt], r[Status]);
 391                 WR(Control1, r[Control1] | Srstdata);
 392                 while(r[Control1] & Srstdata)
 393                         ;
 394                 while(r[Status] & Datinhibit)
 395                         ;
 396         }
 397         WR(Arg1, arg);
 398         if((i = (r[Interrupt] & ~Cardintr)) != 0){
 399                 if(i != Cardinsert)
 400                         print("emmc: before command, intr was %ux\n", i);
 401                 WR(Interrupt, i);
 402         }
 403         WR(Cmdtm, c);
 404         now = m->ticks;
 405         while(((i=r[Interrupt])&(Cmddone|Err)) == 0)
 406                 if(m->ticks-now > HZ)
 407                         break;
 408         if((i&(Cmddone|Err)) != Cmddone){
 409                 if((i&~(Err|Cardintr)) != Ctoerr)
 410                         print("emmc: cmd %ux arg %ux error intr %ux stat %ux\n", c, arg, i, r[Status]);
 411                 WR(Interrupt, i);
 412                 if(r[Status]&Cmdinhibit){
 413                         WR(Control1, r[Control1]|Srstcmd);
 414                         while(r[Control1]&Srstcmd)
 415                                 ;
 416                 }
 417                 error(Eio);
 418         }
 419         WR(Interrupt, i & ~(Datadone|Readrdy|Writerdy));
 420         switch(c & Respmask){
 421         case Resp136:
 422                 resp[0] = r[Resp0]<<8;
 423                 resp[1] = r[Resp0]>>24 | r[Resp1]<<8;
 424                 resp[2] = r[Resp1]>>24 | r[Resp2]<<8;
 425                 resp[3] = r[Resp2]>>24 | r[Resp3]<<8;
 426                 break;
 427         case Resp48:
 428         case Resp48busy:
 429                 resp[0] = r[Resp0];
 430                 break;
 431         case Respnone:
 432                 resp[0] = 0;
 433                 break;
 434         }
 435         if((c & Respmask) == Resp48busy){
 436                 WR(Irpten, r[Irpten]|Datadone|Err);
 437                 tsleep(&emmc.r, datadone, 0, 3000);
 438                 i = r[Interrupt];
 439                 if((i & Datadone) == 0)
 440                         print("emmcio: no Datadone after CMD%d\n", cmd);
 441                 if(i & Err)
 442                         print("emmcio: CMD%d error interrupt %ux\n",
 443                                 cmd, r[Interrupt]);
 444                 WR(Interrupt, i);
 445         }
 446         /*
 447          * Once card is selected, use faster clock
 448          */
 449         if(cmd == MMCSelect){
 450                 delay(1);
 451                 emmcclk(SDfreq);
 452                 delay(1);
 453                 emmc.fastclock = 1;
 454         }
 455         if(cmd == Setbuswidth){
 456                 if(emmc.appcmd){
 457                         /*
 458                          * If card bus width changes, change host bus width
 459                          */
 460                         switch(arg){
 461                         case 0:
 462                                 WR(Control0, r[Control0] & ~Dwidth4);
 463                                 break;
 464                         case 2:
 465                                 WR(Control0, r[Control0] | Dwidth4);
 466                                 break;
 467                         }
 468                 }else{
 469                         /*
 470                          * If card switched into high speed mode, increase clock speed
 471                          */
 472                         if((arg&0x8000000F) == 0x80000001){
 473                                 delay(1);
 474                                 emmcclk(SDfreqhs);
 475                                 delay(1);
 476                         }
 477                 }
 478         }else if(cmd == IORWdirect && (arg & ~0xFF) == (1<<31|0<<28|7<<9)){
 479                 switch(arg & 0x3){
 480                 case 0:
 481                         WR(Control0, r[Control0] & ~Dwidth4);
 482                         break;
 483                 case 2:
 484                         WR(Control0, r[Control0] | Dwidth4);
 485                         //WR(Control0, r[Control0] | Hispeed);
 486                         break;
 487                 }
 488         }
 489         emmc.appcmd = (cmd == Appcmd);
 490         return 0;
 491 }
 492
 493 static void
 494 emmciosetup(int write, void *buf, int bsize, int bcount)
 495 {
 496         int len;
 497
 498         len = bsize * bcount;
 499         assert(((uintptr)buf&3) == 0);
 500         assert((len&3) == 0);
 501         assert(bsize <= 2048);
 502         WR(Blksizecnt, bcount<<16 | bsize);
 503         if(emmc.dma)
 504                 sdfree(emmc.dma);
 505         emmc.dma = dmaalloc(buf, len);
 506         if(write)
 507                 cachedwbse(buf, len);
 508         else
 509                 cachedwbinvse(buf, len);
 510         WR(Dmadesc, dmaaddr(emmc.dma));
 511         okay(1);
 512 }
 513
 514 static void
 515 emmcio(int write, uchar *buf, int len)
 516 {
 517         u32int *r;
 518         int i;
 519
 520         r = (u32int*)EMMCREGS;
 521         if(waserror()){
 522                 okay(0);
 523                 nexterror();
 524         }
 525         WR(Irpten, r[Irpten] | Datadone|Err);
 526         tsleep(&emmc.r, datadone, 0, 3000);
 527         WR(Irpten, r[Irpten] & ~(Datadone|Err));
 528         i = r[Interrupt];
 529         if((i & (Datadone|Err)) != Datadone){
 530                 print("sdhc: %s error intr %ux stat %ux\n",
 531                         write? "write" : "read", i, r[Status]);
 532                 WR(Interrupt, i);
 533                 error(Eio);
 534         }
 535         WR(Interrupt, i);
 536         if(!write)
 537                 cachedinvse(buf, len);
 538         poperror();
 539         okay(0);
 540 }
 541
 542 static void
 543 mmcinterrupt(Ureg*, void*)
 544 {
 545         u32int *r;
 546         int i;
 547
 548         r = (u32int*)EMMCREGS;
 549         i = r[Interrupt];
 550         if(i&(Datadone|Err))
 551                 wakeup(&emmc.r);
 552         if(i&Cardintr)
 553                 wakeup(&emmc.cardr);
 554         WR(Irpten, r[Irpten] & ~i);
 555 }
 556
 557 SDio sdio = {
 558         "sdhc",
 559         emmcinit,
 560         emmcenable,
 561         emmcinquiry,
 562         emmccmd,
 563         emmciosetup,
 564         emmcio,
 565 };