2 #include "../port/lib.h"
11 uintptr va, pa, pe, attr;
14 attr = PTEWRITE | PTEAF | PTEKERNEL | PTEUXN | PTESH(SHARE_INNER);
15 pe = PHYSDRAM + soc.dramsize;
16 if(pe > (uintptr)-KZERO)
18 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(1), va += PGLSZ(1)){
19 if(pe - pa < PGLSZ(1)){
20 l1[PTL1X(va, 1)] = (uintptr)l1 | PTEVALID | PTETABLE;
21 l1[PTL1X(pa, 1)] = (uintptr)l1 | PTEVALID | PTETABLE;
22 for(; pa < pe; pa += PGLSZ(0), va += PGLSZ(0))
23 l1[PTLX(va, 0)] = pa | PTEVALID | PTEPAGE | attr;
26 l1[PTL1X(va, 1)] = pa | PTEVALID | PTEBLOCK | attr;
27 l1[PTL1X(pa, 1)] = pa | PTEVALID | PTEBLOCK | attr;
30 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(2), va += PGLSZ(2))
31 l1[PTL1X(pa, 2)] = (uintptr)&l1[L1TABLEX(pa, 1)] | PTEVALID | PTETABLE;
33 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(3), va += PGLSZ(3))
34 l1[PTL1X(pa, 3)] = (uintptr)&l1[L1TABLEX(pa, 2)] | PTEVALID | PTETABLE;
37 attr = PTEWRITE | PTEAF | PTEKERNEL | PTEUXN | PTEPXN | PTESH(SHARE_OUTER) | PTEDEVICE;
38 pe = soc.physio + soc.iosize;
39 for(pa = soc.physio, va = soc.virtio; pa < pe; pa += PGLSZ(1), va += PGLSZ(1)){
40 if(((pa|va) & PGLSZ(1)-1) != 0){
41 l1[PTL1X(va, 1)] = (uintptr)l1 | PTEVALID | PTETABLE;
42 for(; pa < pe && ((va|pa) & PGLSZ(1)-1) != 0; pa += PGLSZ(0), va += PGLSZ(0)){
43 assert(l1[PTLX(va, 0)] == 0);
44 l1[PTLX(va, 0)] = pa | PTEVALID | PTEPAGE | attr;
48 l1[PTL1X(va, 1)] = pa | PTEVALID | PTEBLOCK | attr;
52 attr = PTEWRITE | PTEAF | PTEKERNEL | PTEUXN | PTEPXN | PTESH(SHARE_OUTER) | PTEDEVICE;
53 pe = soc.armlocal + MB;
54 for(pa = soc.armlocal, va = ARMLOCAL; pa < pe; pa += PGLSZ(1), va += PGLSZ(1)){
55 if(((pa|va) & PGLSZ(1)-1) != 0){
56 l1[PTL1X(va, 1)] = (uintptr)l1 | PTEVALID | PTETABLE;
57 for(; pa < pe && ((va|pa) & PGLSZ(1)-1) != 0; pa += PGLSZ(0), va += PGLSZ(0)){
58 assert(l1[PTLX(va, 0)] == 0);
59 l1[PTLX(va, 0)] = pa | PTEVALID | PTEPAGE | attr;
63 l1[PTL1X(va, 1)] = pa | PTEVALID | PTEBLOCK | attr;
68 attr = PTEWRITE | PTEAF | PTEKERNEL | PTEUXN | PTEPXN | PTESH(SHARE_OUTER) | PTEDEVICE;
69 pe = soc.pciwin + 512*MB;
70 for(pa = soc.pciwin, va = VIRTPCI; pa < pe; pa += PGLSZ(1), va += PGLSZ(1))
71 l1[PTL1X(va, 1)] = pa | PTEVALID | PTEBLOCK | attr;
75 for(va = KSEG0; va != 0; va += PGLSZ(2))
76 l1[PTL1X(va, 2)] = (uintptr)&l1[L1TABLEX(va, 1)] | PTEVALID | PTETABLE;
78 for(va = KSEG0; va != 0; va += PGLSZ(3))
79 l1[PTL1X(va, 3)] = (uintptr)&l1[L1TABLEX(va, 2)] | PTEVALID | PTETABLE;
83 mmu0clear(uintptr *l1)
87 pe = PHYSDRAM + soc.dramsize;
88 if(pe > (uintptr)-KZERO)
90 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(1), va += PGLSZ(1))
91 if(PTL1X(pa, 1) != PTL1X(va, 1))
94 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(2), va += PGLSZ(2))
95 if(PTL1X(pa, 2) != PTL1X(va, 2))
98 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(3), va += PGLSZ(3))
99 if(PTL1X(pa, 3) != PTL1X(va, 3))
100 l1[PTL1X(pa, 3)] = 0;
104 mmuidmap(uintptr *l1)
108 pe = PHYSDRAM + soc.dramsize;
109 if(pe > (uintptr)-KZERO)
110 pe = (uintptr)-KZERO;
111 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(1), va += PGLSZ(1))
112 l1[PTL1X(pa, 1)] = l1[PTL1X(va, 1)];
114 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(2), va += PGLSZ(2))
115 l1[PTL1X(pa, 2)] = l1[PTL1X(va, 2)];
117 for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(3), va += PGLSZ(3))
118 l1[PTL1X(pa, 3)] = l1[PTL1X(va, 3)];
119 setttbr(PADDR(&l1[L1TABLEX(0, PTLEVELS-1)]));
126 m->mmutop = mallocalign(L1TOPSIZE, BY2PG, 0, 0);
128 panic("mmu1init: no memory for mmutop");
129 memset(m->mmutop, 0, L1TOPSIZE);
136 if((uintptr)va >= KZERO)
137 return (uintptr)va-KZERO;
138 panic("paddr: va=%#p pc=%#p", va, getcallerpc(&va));
145 if(pa < (uintptr)-KZERO)
153 if(pa < (uintptr)-KZERO)
154 return (void*)(pa + KZERO);
155 panic("kaddr: pa=%#p pc=%#p", pa, getcallerpc(&pa));
176 mmukmap(uintptr va, uintptr pa, usize size)
178 uintptr a, pe, off, attr;
183 attr = va & PTEMA(7);
187 pe = (pa + size + (PGLSZ(1)-1)) & -PGLSZ(1);
190 ((uintptr*)L1)[PTL1X(va, 1)] = pa | PTEVALID | PTEBLOCK | PTEWRITE | PTEAF
191 | PTEKERNEL | PTEUXN | PTEPXN | PTESH(SHARE_OUTER) | attr;
200 vmap(uintptr pa, int)
202 if(soc.pciwin && pa >= soc.pciwin)
203 return (void*)(VIRTPCI + (pa - soc.pciwin));
204 if(soc.armlocal && pa >= soc.armlocal)
205 return (void*)(ARMLOCAL + (pa - soc.armlocal));
206 if(soc.physio && pa >= soc.physio)
207 return (void*)(soc.virtio + (pa - soc.physio));
217 mmuwalk(uintptr va, int level)
223 x = PTLX(va, PTLEVELS-1);
225 for(i = PTLEVELS-2; i >= level; i--){
228 if(pte & (0xFFFFULL<<48))
229 iprint("strange pte %#p va %#p\n", pte, va);
230 pte &= ~(0xFFFFULL<<48 | BY2PG-1);
236 up->mmufree = pg->next;
237 pg->va = va & -PGLSZ(i+1);
238 if((pg->next = up->mmuhead[i+1]) == nil)
239 up->mmutail[i+1] = pg;
240 up->mmuhead[i+1] = pg;
241 memset(KADDR(pg->pa), 0, BY2PG);
243 table[x] = pg->pa | PTEVALID | PTETABLE;
244 table = KADDR(pg->pa);
246 x = PTLX(va, (uintptr)i);
251 static Proc *asidlist[256];
267 a %= nelem(asidlist);
269 continue; // reserved
271 if(x == p || x == nil || (x->asid < 0 && x->mach == nil))
289 if(a > 0 && asidlist[a] == p)
298 * Prevent the following scenario:
299 * pX sleeps on cpuA, leaving its page tables in mmutop
300 * pX wakes up on cpuB, and exits, freeing its page tables
301 * pY on cpuB allocates a freed page table page and overwrites with data
302 * cpuA takes an interrupt, and is now running with bad page tables
303 * In theory this shouldn't hurt because only user address space tables
304 * are affected, and mmuswitch will clear mmutop before a user process is
305 * dispatched. But empirically it correlates with weird problems, eg
306 * resetting of the core clock at 0x4000001C which confuses local timers.
316 putmmu(uintptr va, uintptr pa, Page *pg)
322 while((pte = mmuwalk(va, 0)) == nil){
324 up->mmufree = newpage(0, nil, 0);
329 if((old & PTEVALID) != 0)
330 flushasidvall((uvlong)up->asid<<48 | va>>12);
332 flushasidva((uvlong)up->asid<<48 | va>>12);
333 *pte = pa | PTEPAGE | PTEUSER | PTEPXN | PTENG | PTEAF | PTESH(SHARE_INNER);
334 if(pg->txtflush & (1UL<<m->machno)){
335 /* pio() sets PG_TXTFLUSH whenever a text pg has been written */
336 cachedwbinvse((void*)KADDR(pg->pa), BY2PG);
337 cacheiinvse((void*)va, BY2PG);
338 pg->txtflush &= ~(1UL<<m->machno);
350 for(i=1; i<PTLEVELS; i++){
351 if(p->mmuhead[i] == nil)
353 p->mmutail[i]->next = p->mmufree;
354 p->mmufree = p->mmuhead[i];
355 p->mmuhead[i] = p->mmutail[i] = nil;
365 for(va = UZERO; va < USTKTOP; va += PGLSZ(PTLEVELS-1))
366 m->mmutop[PTLX(va, PTLEVELS-1)] = 0;
369 setttbr(PADDR(m->mmutop));
378 for(t = p->mmuhead[PTLEVELS-1]; t != nil; t = t->next){
380 m->mmutop[PTLX(va, PTLEVELS-1)] = t->pa | PTEVALID | PTETABLE;
384 flushasid((uvlong)p->asid<<48);
386 setttbr((uvlong)p->asid<<48 | PADDR(m->mmutop));
397 if((t = p->mmufree) != nil){
399 p->mmufree = t->next;
401 panic("mmurelease: bad page ref");
403 } while((t = p->mmufree) != nil);
420 checkmmu(uintptr, uintptr)