4 #define SYSREG(op0,op1,Cn,Cm,op2) SPR(((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5))
7 * instruction cache operations
9 TEXT cacheiinvse(SB), 1, $-4
21 ADDW $4, R4 // log2(linelen)
27 IC R0, 3,7,5,1 // IVAU
36 TEXT cacheiinv(SB), 1, $-4
37 IC R0, 0,7,5,0 // IALLU
42 TEXT cacheuwbinv(SB), 1, $0
48 * data cache operations
50 TEXT cachedwbse(SB), 1, $-4
53 TEXT dccvac(SB), 1, $-4
54 DC R0, 3,7,10,1 // CVAC
57 TEXT cacheduwbse(SB), 1, $-4
60 TEXT dccvau(SB), 1, $-4
61 DC R0, 3,7,11,1 // CVAU
64 TEXT cachedinvse(SB), 1, $-4
67 TEXT dcivac(SB), 1, $-4
68 DC R0, 0,7,6,1 // IVAC
71 TEXT cachedwbinvse(SB), 1, $-4
74 TEXT dccivac(SB), 1, $-4
75 DC R0, 3,7,14,1 // CIVAC
78 TEXT cachedva<>(SB), 1, $-4
91 ADDW $4, R4 // log2(linelen)
110 * l1 cache operations
112 TEXT cachedwb(SB), 1, $-4
117 TEXT dccsw(SB), 1, $-4
118 DC R0, 0,7,10,2 // CSW
121 TEXT cachedinv(SB), 1, $-4
126 TEXT dcisw(SB), 1, $-4
127 DC R0, 0,7,6,2 // ISW
130 TEXT cachedwbinv(SB), 1, $-4
135 TEXT dccisw(SB), 1, $-4
136 DC R0, 0,7,14,2 // CISW
140 * l2 cache operations
142 TEXT l2cacheuwb(SB), 1, $-4
145 TEXT l2cacheuinv(SB), 1, $-4
148 TEXT l2cacheuwbinv(SB), 1, $-4
152 TEXT cachesize(SB), 1, $-4
161 TEXT cachedsw<>(SB), 1, $-4
172 ANDW $1023, R7 // lastway
173 ADDW $1, R7, R5 // #ways
176 ANDW $32767, R2 // lastset
180 ADDW $4, R4 // log2(linelen)
182 MOVWU $32, R3 // wayshift = 32 - log2(#ways)
184 CBZ R7, _loop // lastway == 0?
185 LSR $1, R7 // lastway >>= 1
186 SUB $1, R3 // wayshift--
194 LSL R3, R7, R0 // way<<wayshift
195 LSL R4, R6, R9 // set<<log2(linelen)
197 ORRW R9, R0 // setway
199 BL (R1) // op(setway)