2 * VFPv2 or VFPv3 floating point unit
5 #include "../port/lib.h"
12 /* subarchitecture code in m->havefp */
18 /* fp control regs. most are read-only */
25 Fpinst= 9, /* optional, for exceptions */
32 Fpdex = 1 << 29, /* defined synch exception */
33 // Fp2v = 1 << 28, /* Fpinst2 reg is valid */
34 // Fpvv = 1 << 27, /* if Fpdex, vecitr is valid */
35 // Fptfv = 1 << 26, /* trapped fault is valid */
36 // Fpvecitr = MASK(3) << 8,
37 /* FSR bits appear here */
38 Fpmbc = Fpdex, /* bits exception handler must clear */
40 /* Fpscr bits; see u.h for more */
41 Stride = MASK(2) << 20,
45 /* trap exception enables (not allowed in vfp3) */
46 FPIDNRM = 1 << 15, /* input denormal */
47 Alltraps = FPIDNRM | FPINEX | FPUNFL | FPOVFL | FPZDIV | FPINVAL,
48 /* pending exceptions */
49 FPAIDNRM = 1 << 7, /* input denormal */
50 Allexc = FPAIDNRM | FPAINEX | FPAUNFL | FPAOVFL | FPAZDIV | FPAINVAL,
52 Allcc = MASK(4) << 28,
56 Cpaccnosimd = 1u << 31,
61 subarch(int impl, uint sa)
63 static char *armarchs[] = {
64 "VFPv1 (unsupported)",
66 "VFPv3+ with common VFP subarch v2",
67 "VFPv3+ with null subarch",
68 "VFPv3+ with common VFP subarch v3",
71 if (impl != 'A' || sa >= nelem(armarchs))
96 gotfp = 1 << CpFP | 1 << CpDFP;
97 cpwrsc(0, CpCONTROL, 0, CpCPaccess, MASK(28));
98 acc = cprdsc(0, CpCONTROL, 0, CpCPaccess);
99 if ((acc & (MASK(2) << (2*CpFP))) == 0) {
100 gotfp &= ~(1 << CpFP);
101 print("fpon: no single FP coprocessor\n");
103 if ((acc & (MASK(2) << (2*CpDFP))) == 0) {
104 gotfp &= ~(1 << CpDFP);
105 print("fpon: no double FP coprocessor\n");
108 print("fpon: no FP coprocessors\n");
112 m->fpon = 1; /* don't panic */
115 switch((sid >> 16) & MASK(7)){
122 default: /* VFPv3 or later */
124 m->fpnregs = (acc & Cpaccd16) ? 16 : 32;
128 print("fp: %d registers, %s simd\n", m->fpnregs,
129 (acc & Cpaccnosimd? " no": ""));
135 * these can be called to turn the fpu on or off for user procs,
136 * not just at system start up or shutdown.
151 if (!m->fpon && havefp()) {
152 /* enable fp. must be first operation on the FPUs. */
153 fpwr(Fpexc, Fpenabled);
165 /* clear pending exceptions; no traps in vfp3; all v7 ops are scalar */
166 m->fpscr = Dn | FPRNR | (FPINVAL | FPZDIV | FPOVFL) & ~Alltraps;
167 /* VFPv2 needs software support for underflows, so force them to zero */
168 if(m->havefp == VFPv2)
170 fpwr(Fpscr, m->fpscr);
177 print("fp: %s arch %s; rev %ld\n", implement(impl),
178 subarch(impl, (sid >> 16) & MASK(7)), sid & MASK(4));
197 fpwr(Fpscr, (fprd(Fpscr) & Allcc) | m->fpscr);
199 fpcfg(); /* 1st time on this fpu; configure it */
209 // scr = fprd(Fpscr);
210 // m->fpscr = scr & ~Allexc;
211 // fpwr(Fpscr, m->fpscr);
213 fpwr(Fpexc, fprd(Fpexc) & ~Fpmbc);
218 * Called when a note is about to be delivered to a
219 * user process, usually at the end of a system call.
220 * Note handlers are not allowed to use the FPU so
221 * the state is marked (after saving if necessary) and
222 * checked in the Device Not Available handler.
227 if(up->fpstate == FPactive){
229 up->fpstate = FPinactive;
231 up->fpstate |= FPillegal;
235 * Called from sysnoted() via the machine-dependent
237 * Clear the flag set above in fpunotify().
242 up->fpstate &= ~FPillegal;
245 /* should only be called if p->fpstate == FPactive */
252 fps->control = fps->status = fprd(Fpscr);
254 for (n = 0; n < m->fpnregs; n++)
255 fpsavereg(n, (uvlong *)fps->regs[n]);
265 fpwr(Fpscr, p->fpsave->control);
266 m->fpscr = fprd(Fpscr) & ~Allcc;
268 for (n = 0; n < m->fpnregs; n++)
269 fprestreg(n, *(uvlong *)p->fpsave->regs[n]);
273 * Called from sched() and sleep() via the machine-dependent
274 * procsave() routine.
275 * About to go in to the scheduler.
276 * If the process wasn't using the FPU
277 * there's nothing to do.
282 if(p->fpstate == FPactive){
283 if(p->state == Moribund)
287 * Fpsave() stores without handling pending
288 * unmasked exeptions. Postnote() can't be called
289 * here as sleep() already has up->rlock, so
290 * the handling of pending exceptions is delayed
291 * until the process runs again and generates an
292 * emulation fault to activate the FPU.
296 p->fpstate = FPinactive;
301 * The process has been rescheduled and is about to run.
302 * Nothing to do here right now. If the process tries to use
303 * the FPU again it will cause a Device Not Available
304 * exception and the state will then be restored.
307 fpuprocrestore(Proc *)
312 * The current process has been forked,
313 * save and copy neccesary state to child.
321 switch(up->fpstate & ~FPillegal){
324 up->fpstate = FPinactive;
327 memmove(p->fpsave, up->fpsave, sizeof(FPsave));
328 p->fpstate = FPinactive;
335 * Called from sysexec() via sysprocsetup() to
336 * set the FPU for the new process.
339 fpusysprocsetup(Proc *p)
353 char *msg, note[ERRMAX];
355 status = up->fpsave->status;
358 * Some attention should probably be paid here to the
359 * exception masks and error summary.
361 if (status & FPAINEX)
363 else if (status & FPAOVFL)
365 else if (status & FPAUNFL)
367 else if (status & FPAZDIV)
368 msg = "divide by zero";
369 else if (status & FPAINVAL)
370 msg = "bad operation";
373 snprint(note, sizeof note, "sys: fp: %s fppc=%#p status=%#lux",
374 msg, up->fpsave->pc, status);
375 postnote(up, 1, note, NDebug);
383 error("illegal instruction: VFP opcode in emulated mode");
386 up->fpstate = FPactive;
390 * Before restoring the state, check for any pending
391 * exceptions. There's no way to restore the state without
392 * generating an unmasked exception.
393 * More attention should probably be paid here to the
394 * exception masks and error summary.
396 if(up->fpsave->status & (FPAINEX|FPAUNFL|FPAOVFL|FPAZDIV|FPAINVAL)){
401 up->fpstate = FPactive;
404 error("illegal instruction: bad vfp fpu opcode");
413 if (m->fppc == pc && m->fppid == up->pid) {
416 panic("fpuemu: cpu%d stuck at pid %ld %s pc %#p "
417 "instr %#8.8lux", m->machno, up->pid, up->text,
435 condok(int cc, int c)
440 case 1: /* Z clear */
444 case 3: /* C clear */
448 case 5: /* N clear */
452 case 7: /* V clear */
454 case 8: /* C set and Z clear */
455 return cc&C && (cc&Z) == 0;
456 case 9: /* C clear or Z set */
457 return (cc&C) == 0 || cc&Z;
458 case 10: /* N set and V set, or N clear and V clear */
459 return (~cc&(N|V))==0 || (cc&(N|V)) == 0;
460 case 11: /* N set and V clear, or N clear and V set */
461 return (cc&(N|V))==N || (cc&(N|V))==V;
462 case 12: /* Z clear, and either N set and V set or N clear and V clear */
463 return (cc&Z) == 0 && ((~cc&(N|V))==0 || (cc&(N|V))==0);
464 case 13: /* Z set, or N set and V clear or N clear and V set */
465 return (cc&Z) || (cc&(N|V))==N || (cc&(N|V))==V;
466 case 14: /* always */
468 case 15: /* never (reserved) */
471 return 0; /* not reached */
474 /* only called to deal with user-mode instruction faults */
483 postnote(up, 1, up->errstr, NDebug);
487 if(up->fpstate & FPillegal)
488 error("floating point in note handler");
493 op = (*(ulong *)pc >> 24) & MASK(4);
494 cop = (*(ulong *)pc >> 8) & MASK(4);
496 fpstuck(pc); /* debugging; could move down 1 line */
497 if (ISFPAOP(cop, op)) { /* old arm 7500 fpa opcode? */
500 pprint("warning: emulated arm7500 fpa instr %#8.8lux at %#p\n", *(ulong *)pc, pc);
505 nfp = fpiarm(ureg); /* advances pc past emulated instr(s) */
506 if (nfp > 1) /* could adjust this threshold */
507 m->fppc = m->fpcnt = 0;
510 } else if (ISVFPOP(cop, op)) { /* if vfp, fpu off or unsupported instruction */
511 mathemu(ureg); /* enable fpu & retry */