2 * armv6/armv7 reboot code
6 #define WFI WORD $0xe320f003 /* wait for interrupt */
7 #define WFE WORD $0xe320f002 /* wait for event */
33 /* clean dcache using appropriate code for armv6 or armv7 */
34 MRC CpSC, 0, R1, C(CpID), C(CpIDfeat), 7 /* Memory Model Feature Register 3 */
35 TST $0xF, R1 /* hierarchical cache maintenance? */
39 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEall
45 /* load entry before turning off mmu */
49 MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
50 BIC $(CpCdcache|CpCicache|CpCpredict), R1
51 MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
54 /* invalidate icache */
56 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
60 MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
62 MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
66 MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
68 MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
76 /* other cpus wait for inter processor interrupt */
79 WFE /* wait for event signal */
80 MOVW $0x400000CC, R1 /* inter-core .startcpu mailboxes */
81 ADD R2<<4, R1 /* mailbox for this core */
82 MOVW 0(R1), R8 /* content of mailbox */
84 BEQ dowfi /* if zero, wait again */
87 MOVW $0, R2 /* no ATAGS/DTB pointer */
88 BIC $KSEGM, R8 /* entry to physical */
93 #define ICACHELINESZ 32