4 * HZ should divide 1000 evenly, ideally.
5 * 100, 125, 200, 250 and 333 are okay.
7 #define HZ 100 /* clock frequency */
8 #define MS2HZ (1000/HZ) /* millisec per clock tick */
9 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
15 typedef struct Conf Conf;
16 typedef struct Confmem Confmem;
17 typedef struct FPsave FPsave;
18 typedef struct PFPU PFPU;
19 typedef struct ISAConf ISAConf;
20 typedef struct Label Label;
21 typedef struct Lock Lock;
22 typedef struct Memcache Memcache;
23 typedef struct MMMU MMMU;
24 typedef struct Mach Mach;
25 typedef struct Page Page;
26 typedef struct PhysUart PhysUart;
27 typedef struct PMMU PMMU;
28 typedef struct Proc Proc;
30 typedef struct Uart Uart;
31 typedef struct Ureg Ureg;
34 #pragma incomplete Ureg
36 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */
39 * parameters for sysproc.c
41 #define AOUT_MAGIC (E_MAGIC)
60 * emulated or vfp3 floating point
63 Maxfpregs = 32, /* could be 16 or 32, see Mach.fpnregs */
72 * vfp3 with ieee fp regs; uvlong is sufficient for hardware but
73 * each must be able to hold an Internal from fpi.h for sw emulation.
75 ulong regs[Maxfpregs][3];
78 uintptr pc; /* of failed fp instr. */
94 /* bits or'd with the state */
109 ulong nmach; /* processors */
110 ulong nproc; /* processes */
111 Confmem mem[1]; /* physical memory */
112 ulong npage; /* total physical pages of memory */
113 usize upages; /* user page pool */
114 ulong copymode; /* 0 is copy on write, 1 is copy on reference */
115 ulong ialloc; /* max interrupt time allocation in bytes */
116 ulong pipeqsize; /* size in bytes of pipe queues */
117 ulong nimage; /* number of page cache image headers */
118 ulong nswap; /* number of swap pages */
119 int nswppo; /* max # of pageouts per segment pass */
120 ulong hz; /* processor cycle freq */
122 int monitor; /* flag */
130 PTE* mmul1; /* l1 for this processor */
139 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */
143 Page* mmul2cache; /* free mmu pages */
146 #include "../port/portdat.h"
150 int machno; /* physical id of processor */
151 uintptr splpc; /* pc of last caller to splhi */
153 Proc* proc; /* current process */
156 int flushmmu; /* flush current proc mmu state */
158 ulong ticks; /* of the clock since boot time */
159 Label sched; /* scheduler wakeup */
160 Lock alarmlock; /* access to alarm list */
161 void* alarm; /* alarms bound to this clock */
163 Proc* readied; /* for runproc */
164 ulong schedticks; /* next forced context switch */
177 uvlong fastclock; /* last sampled value */
178 uvlong inidle; /* time spent in idlehands() */
182 Perf perf; /* performance counters */
186 uvlong cpuhz; /* speed of cpu */
187 uvlong cyclefreq; /* Frequency of user readable cycle counter */
189 /* vfp2 or vfp3 fpu */
195 ulong fpscr; /* sw copy */
196 int fppid; /* pid of last fault */
197 uintptr fppc; /* addr of last fault */
198 int fpcnt; /* how many consecutive at that addr */
200 /* save areas for exceptions, hold R0-R4 */
205 u32int smon[5]; /* probably not needed */
215 #define VA(k) ((uintptr)(k))
216 #define kmap(p) (KMap*)((p)->pa|kseg0)
221 char machs[MAXMACH]; /* active CPUs */
222 int exiting; /* shutdown */
225 extern register Mach* m; /* R10 */
226 extern register Proc* up; /* R9 */
227 extern uintptr kseg0;
228 extern Mach* machaddr[MAXMACH];
229 extern ulong memsize;
230 extern int normalprint;
233 * a parsed plan9.ini line
250 #define MACHP(n) (machaddr[n])
253 * Horrid. But the alternative is 'defined'.
256 #define DBGFLG (dbgflg[_DBGC_])
262 extern char dbgflg[256];
264 #define dbgprint print /* for now */
267 * hardware info about a device
276 ulong intnum; /* interrupt number */
277 char *type; /* card type, malloced */
278 int nports; /* Number of ports */
279 Devport *ports; /* The ports themselves */