2 * armv6/v7 machine assist, definitions
4 * loader uses R11 as scratch.
10 #define PADDR(va) (PHYSDRAM | ((va) & ~KSEGM))
12 #define L1X(va) (((((va))>>20) & 0x0fff)<<2)
20 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEwait
24 MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
26 #define BARRIERS DSB; ISB
28 #define MCRR(coproc, op, rd, rn, crm) \
29 WORD $(0xec400000|(rn)<<16|(rd)<<12|(coproc)<<8|(op)<<4|(crm))
30 #define MRRC(coproc, op, rd, rn, crm) \
31 WORD $(0xec500000|(rn)<<16|(rd)<<12|(coproc)<<8|(op)<<4|(crm))
32 #define MSR(R, rn, m, m1) \
33 WORD $(0xe120f200|(R)<<22|(m1)<<16|(m)<<8|(rn))
35 #define CPSIE WORD $0xf1080080 /* intr enable: zeroes I bit */
36 #define CPSID WORD $0xf10c0080 /* intr disable: sets I bit */
39 MOVW $0x7E200028,R2; \
44 * get cpu id, or zero if armv6
47 MRC CpSC, 0, r, C(CpID), C(CpIDfeat), 7; \
50 MRC CpSC, 0, r, C(CpID), C(CpIDidct), CpIDmpid; \