2 * arm-specific definitions for armv6
3 * these are used in C and assembler
7 * Program Status Registers
9 #define PsrMusr 0x00000010 /* mode */
10 #define PsrMfiq 0x00000011
11 #define PsrMirq 0x00000012
12 #define PsrMsvc 0x00000013 /* `protected mode for OS' */
13 #define PsrMmon 0x00000016 /* `secure monitor' (trustzone hyper) */
14 #define PsrMabt 0x00000017
15 #define PsrMund 0x0000001B
16 #define PsrMsys 0x0000001F /* `privileged user mode for OS' (trustzone) */
17 #define PsrMask 0x0000001F
19 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */
20 #define PsrDirq 0x00000080 /* disable IRQ interrupts */
22 #define PsrV 0x10000000 /* overflow */
23 #define PsrC 0x20000000 /* carry/borrow/extend */
24 #define PsrZ 0x40000000 /* zero */
25 #define PsrN 0x80000000 /* negative/less than */
27 /* instruction decoding */
28 #define ISCPOP(op) ((op) == 0xE || ((op) & ~1) == 0xC)
29 #define ISFPAOP(cp, op) ((cp) == CpOFPA && ISCPOP(op))
30 #define ISVFPOP(cp, op) (((cp) == CpDFP || (cp) == CpFP) && ISCPOP(op))
35 #define CpOFPA 1 /* ancient 7500 FPA */
36 #define CpFP 10 /* float FP, VFP cfg. */
37 #define CpDFP 11 /* double FP */
38 #define CpSC 15 /* System Control */
41 * Primary (CRn) CpSC registers.
43 #define CpID 0 /* ID and cache type */
44 #define CpCONTROL 1 /* miscellaneous control */
45 #define CpTTB 2 /* Translation Table Base(s) */
46 #define CpDAC 3 /* Domain Access Control */
47 #define CpFSR 5 /* Fault Status */
48 #define CpFAR 6 /* Fault Address */
49 #define CpCACHE 7 /* cache/write buffer control */
50 #define CpTLB 8 /* TLB control */
51 #define CpCLD 9 /* L2 Cache Lockdown, op1==1 */
52 #define CpTLD 10 /* TLB Lockdown, with op2 */
53 #define CpVECS 12 /* vector bases, op1==0, Crm==0, op2s (cortex) */
54 #define CpPID 13 /* Process ID */
55 #define CpSPM 15 /* system performance monitor (arm1176) */
58 * CpTTB op1==0, Crm==0 opcode2 values.
61 #define CpTTB1 1 /* cortex */
62 #define CpTTBctl 2 /* cortex */
65 * CpFSR opcode2 values.
67 #define CpFSRdata 0 /* armv6, armv7 */
68 #define CpFSRinst 1 /* armv6, armv7 */
71 * CpID Secondary (CRm) registers.
76 * CpID op1==0 opcode2 fields.
77 * the cortex has more op1 codes for cache size, etc.
79 #define CpIDid 0 /* main ID */
80 #define CpIDct 1 /* cache type */
81 #define CpIDtlb 3 /* tlb type (cortex) */
82 #define CpIDmpid 5 /* multiprocessor id (cortex) */
84 /* CpIDid op1 values */
85 #define CpIDcsize 1 /* cache size (cortex) */
86 #define CpIDcssel 2 /* cache size select (cortex) */
89 * CpCONTROL op2 codes, op1==0, Crm==0.
96 * CpCONTROL: op1==0, CRm==0, op2==CpMainctl.
97 * main control register.
98 * cortex/armv7 has more ops and CRm values.
100 #define CpCmmu 0x00000001 /* M: MMU enable */
101 #define CpCalign 0x00000002 /* A: alignment fault enable */
102 #define CpCdcache 0x00000004 /* C: data cache on */
103 #define CpCsbo (3<<22|1<<18|1<<16|017<<3) /* must be 1 (armv7) */
104 #define CpCsbz (CpCtre|1<<26|CpCve|1<<15|7<<7) /* must be 0 (armv7) */
105 #define CpCsw (1<<10) /* SW: SWP(B) enable (deprecated in v7) */
106 #define CpCpredict 0x00000800 /* Z: branch prediction (armv7) */
107 #define CpCicache 0x00001000 /* I: instruction cache on */
108 #define CpChv 0x00002000 /* V: high vectors */
109 #define CpCrr (1<<14) /* RR: round robin vs random cache replacement */
110 #define CpCha (1<<17) /* HA: hw access flag enable */
111 #define CpCdz (1<<19) /* DZ: divide by zero fault enable */
112 #define CpCfi (1<<21) /* FI: fast intrs */
113 #define CpCve (1<<24) /* VE: intr vectors enable */
114 #define CpCee (1<<25) /* EE: exception endianness */
115 #define CpCnmfi (1<<27) /* NMFI: non-maskable fast intrs. */
116 #define CpCtre (1<<28) /* TRE: TEX remap enable */
117 #define CpCafe (1<<29) /* AFE: access flag (ttb) enable */
120 * CpCONTROL: op1==0, CRm==0, op2==CpAuxctl.
121 * Auxiliary control register on cortex at least.
123 #define CpACcachenopipe (1<<20) /* don't pipeline cache maint. */
124 #define CpACcp15serial (1<<18) /* serialise CP1[45] ops. */
125 #define CpACcp15waitidle (1<<17) /* CP1[45] wait-on-idle */
126 #define CpACcp15pipeflush (1<<16) /* CP1[45] flush pipeline */
127 #define CpACneonissue1 (1<<12) /* neon single issue */
128 #define CpACldstissue1 (1<<11) /* force single issue ld, st */
129 #define CpACissue1 (1<<10) /* force single issue */
130 #define CpACnobsm (1<<7) /* no branch size mispredicts */
131 #define CpACibe (1<<6) /* cp15 invalidate & btb enable */
132 #define CpACl1neon (1<<5) /* cache neon (FP) data in L1 cache */
133 #define CpACasa (1<<4) /* enable speculative accesses */
134 #define CpACl1pe (1<<3) /* l1 cache parity enable */
135 #define CpACl2en (1<<1) /* l2 cache enable; default 1 */
137 * CpCONTROL Secondary (CRm) registers and opcode2 fields.
139 #define CpCONTROLscr 1
144 * CpCACHE Secondary (CRm) registers and opcode2 fields. op1==0.
145 * In ARM-speak, 'flush' means invalidate and 'clean' means writeback.
147 #define CpCACHEintr 0 /* interrupt (op2==4) */
148 #define CpCACHEisi 1 /* inner-sharable I cache (v7) */
149 #define CpCACHEpaddr 4 /* 0: phys. addr (cortex) */
150 #define CpCACHEinvi 5 /* instruction, branch table */
151 #define CpCACHEinvd 6 /* data or unified */
152 #define CpCACHEinvu 7 /* unified (not on cortex) */
153 #define CpCACHEva2pa 8 /* va -> pa translation (cortex) */
154 #define CpCACHEwb 10 /* writeback */
155 #define CpCACHEinvdse 11 /* data or unified by mva */
156 #define CpCACHEwbi 14 /* writeback+invalidate */
158 #define CpCACHEall 0 /* entire (not for invd nor wb(i) on cortex) */
159 #define CpCACHEse 1 /* single entry */
160 #define CpCACHEsi 2 /* set/index (set/way) */
161 #define CpCACHEtest 3 /* test loop */
162 #define CpCACHEwait 4 /* wait (prefetch flush on cortex) */
163 #define CpCACHEdmbarr 5 /* wb only (cortex) */
164 #define CpCACHEflushbtc 6 /* flush branch-target cache (cortex) */
165 #define CpCACHEflushbtse 7 /* ⋯ or just one entry in it (cortex) */
168 * CpTLB Secondary (CRm) registers and opcode2 fields.
170 #define CpTLBinvi 5 /* instruction */
171 #define CpTLBinvd 6 /* data */
172 #define CpTLBinvu 7 /* unified */
174 #define CpTLBinv 0 /* invalidate all */
175 #define CpTLBinvse 1 /* invalidate single entry */
176 #define CpTBLasid 2 /* by ASID (cortex) */
179 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==0. (cortex)
181 #define CpCLDena 12 /* enables */
182 #define CpCLDcyc 13 /* cycle counter */
183 #define CpCLDuser 14 /* user enable */
185 #define CpCLDenapmnc 0
186 #define CpCLDenacyc 1
189 * CpCLD Secondary (CRm) registers and opcode2 fields for op1==1.
191 #define CpCLDl2 0 /* l2 cache */
193 #define CpCLDl2aux 2 /* auxiliary control */
196 * l2 cache aux. control
198 #define CpCl2ecc (1<<28) /* use ecc, not parity */
199 #define CpCl2noldforw (1<<27) /* no ld forwarding */
200 #define CpCl2nowrcomb (1<<25) /* no write combining */
201 #define CpCl2nowralldel (1<<24) /* no write allocate delay */
202 #define CpCl2nowrallcomb (1<<23) /* no write allocate combine */
203 #define CpCl2nowralloc (1<<22) /* no write allocate */
204 #define CpCl2eccparity (1<<21) /* enable ecc or parity */
205 #define CpCl2inner (1<<16) /* inner cacheability */
206 /* other bits are tag ram & data ram latencies */
209 * CpTLD Secondary (CRm) registers and opcode2 fields.
211 #define CpTLDlock 0 /* TLB lockdown registers */
212 #define CpTLDpreload 1 /* TLB preload */
214 #define CpTLDi 0 /* TLB instr. lockdown reg. */
215 #define CpTLDd 1 /* " data " " */
218 * CpVECS Secondary (CRm) registers and opcode2 fields.
222 #define CpVECSnorm 0 /* (non-)secure base addr */
223 #define CpVECSmon 1 /* secure monitor base addr */
226 * CpSPM Secondary (CRm) registers and opcode2 fields.
228 #define CpSPMperf 12 /* various counters */
230 #define CpSPMctl 0 /* performance monitor control */
231 #define CpSPMcyc 1 /* cycle counter register */
234 * CpCACHERANGE opcode2 fields for MCRR instruction (armv6)
236 #define CpCACHERANGEinvi 5 /* invalidate instruction */
237 #define CpCACHERANGEinvd 6 /* invalidate data */
238 #define CpCACHERANGEdwb 12 /* writeback */
239 #define CpCACHERANGEdwbi 14 /* writeback+invalidate */
242 * MMU page table entries.
243 * Mbz (0x10) bit is implementation-defined and must be 0 on the cortex.
246 #define Fault 0x00000000 /* L[12] pte: unmapped */
248 #define Coarse (Mbz|1) /* L1 */
249 #define Section (Mbz|2) /* L1 1MB */
250 #define Fine (Mbz|3) /* L1 */
252 #define Large 0x00000001 /* L2 64KB */
253 #define Small 0x00000002 /* L2 4KB */
254 #define Tiny 0x00000003 /* L2 1KB: not in v7 */
255 #define Buffered 0x00000004 /* L[12]: write-back not -thru */
256 #define Cached 0x00000008 /* L[12] */
259 #define Noaccess 0 /* AP, DAC */
260 #define Krw 1 /* AP */
261 /* armv7 deprecates AP[2] == 1 & AP[1:0] == 2 (Uro), prefers 3 (new in v7) */
262 #define Uro 2 /* AP */
263 #define Urw 3 /* AP */
264 #define Client 1 /* DAC */
265 #define Manager 3 /* DAC */
267 #define F(v, o, w) (((v) & ((1<<(w))-1))<<(o))
268 #define AP(n, v) F((v), ((n)*2)+4, 2)
269 #define L1AP(ap) (AP(3, (ap)))
270 #define L2AP(ap) (AP(3, (ap))|AP(2, (ap))|AP(1, (ap))|AP(0, (ap))) /* pre-armv7 */
271 #define DAC(n, v) F((v), (n)*2, 2)
273 #define HVECTORS 0xffff0000