2 #include "../port/lib.h"
9 * 8259 interrupt controllers
13 Int0ctl= 0x20, /* control port (ICW1, OCW2, OCW3) */
14 Int0aux= 0x21, /* everything else (ICW2, ICW3, ICW4, OCW1) */
15 Int1ctl= 0xA0, /* control port */
16 Int1aux= 0xA1, /* everything else (ICW2, ICW3, ICW4, OCW1) */
18 Icw1= 0x10, /* select bit in ctl register */
22 EOI= 0x20, /* non-specific end of interrupt */
24 Elcr1= 0x4D0, /* Edge/Level Triggered Register */
28 static int int0mask; /* interrupts enabled for first 8259 */
29 static int int1mask; /* interrupts enabled for second 8259 */
31 int elcr; /* mask of level-triggered interrupts */
38 ioalloc(Int0ctl, 2, 0, "i8259.0");
39 ioalloc(Int1ctl, 2, 0, "i8259.1");
44 * Set up the first 8259 interrupt processor.
45 * Make 8259 interrupts start at CPU vector Int0vec.
46 * Set the 8259 as master with edge triggered
47 * input with fully nested interrupts.
49 outb(Int0ctl, (1<<4)|(0<<3)|(1<<0)); /* ICW1 - master, edge triggered,
51 outb(Int0aux, VectorPIC); /* ICW2 - interrupt vector offset */
52 outb(Int0aux, 0x04); /* ICW3 - have slave on level 2 */
53 outb(Int0aux, 0x01); /* ICW4 - 8086 mode, not buffered */
56 * Set up the second 8259 interrupt processor.
57 * Make 8259 interrupts start at CPU vector VectorPIC+8.
58 * Set the 8259 as slave with edge triggered
59 * input with fully nested interrupts.
61 outb(Int1ctl, (1<<4)|(0<<3)|(1<<0)); /* ICW1 - master, edge triggered,
63 outb(Int1aux, VectorPIC+8); /* ICW2 - interrupt vector offset */
64 outb(Int1aux, 0x02); /* ICW3 - I am a slave on level 2 */
65 outb(Int1aux, 0x01); /* ICW4 - 8086 mode, not buffered */
66 outb(Int1aux, int1mask);
69 * pass #2 8259 interrupts to #1
72 outb(Int0aux, int0mask);
75 * Set Ocw3 to return the ISR when ctl read.
76 * After initialisation status read is set to IRR.
77 * Read IRR first to possibly deassert an outstanding
80 x = inb(Int0ctl); USED(x);
81 outb(Int0ctl, Ocw3|0x03);
82 x = inb(Int1ctl); USED(x);
83 outb(Int1ctl, Ocw3|0x03);
86 * Check for Edge/Level register.
87 * This check may not work for all chipsets.
89 /* elcr1 = inb(Elcr1);
93 if(inb(Elcr1) == 0x20)
94 elcr = (inb(Elcr2)<<8)|elcr1;
98 iprint("ELCR: %4.4uX\n", elcr);
108 * tell the 8259 that we're done with the
109 * highest level interrupt (interrupts are still
113 if(v >= VectorPIC && v <= MaxVectorPIC){
116 if(v >= VectorPIC+8){
117 isr |= inb(Int1ctl)<<8;
122 return isr & (1<<(v-VectorPIC));
126 i8259enable(int v, int, Vctl* vctl)
129 print("i8259enable: vector %d out of range\n", v);
134 * enable corresponding interrupt in 8259
138 outb(Int0aux, int0mask);
141 int1mask &= ~(1<<(v-8));
142 outb(Int1aux, int1mask);
146 vctl->eoi = i8259isr;
148 vctl->isr = i8259isr;