3 vgadb \- VGA controller and monitor database
9 the first describing how to identify and program a VGA controller
10 and the second describing the timing parameters for known
11 monitors to be loaded into a VGA controller to give a particular
12 resolution and refresh rate.
13 Conventionally, at system boot, the program
17 uses the monitor type in
19 the display resolution in
21 and the VGA controller information in the database to
22 find a matching monitor entry and initialize the VGA controller accordingly.
24 The file comprises multi-line entries made up of
25 attribute/value pairs of the form
29 Each line starting without white space starts a new entry.
34 The first part of the database, the VGA controller identification and
35 programming information,
36 consists of a number of entries with attribute
39 Within one of these entries the following attributes are
44 an offset into the VGA BIOS area.
45 The value is a string expected to be found there that will
46 identify the controller.
48 .B 0xC0068="#9GXE64 Pro"
49 would identify a #9GXEpro VGA controller if the string
51 was found in the BIOS at address 0xC0068.
52 There may be more than one identifier attribute per controller.
53 If a match cannot be found, the first few bytes of the BIOS
54 are printed to help identify the card and create a controller
58 A range of the VGA BIOS area.
59 The value is a string as above, but the entire range
60 is searched for that string.
61 The string must begin at or after
63 and not contain any characters at or after
66 .B 0xC0000-0xC0200="MACH64LP"
67 identifies a Mach 64 controller with the
70 occurring anywhere in the first 512 bytes of BIOS memory.
73 VGA controller chip type.
74 This must match one of the VGA controller types
109 RAMDAC controller type.
110 This must match one of the types
129 clock generator type.
130 This must match one of the types
145 hardware graphics cursor type.
146 This must match one of the types
171 Memory bandwidth in megabytes per second.
173 chooses the highest refresh rate possible within the constraints
174 of the monitor (explained below) and the
175 card's memory bandwidth.
178 Whether the card supports a large (>64kb) linear memory
179 window. The value is either
183 (equivalent to unspecified).
184 The current kernel graphics subsystem
185 requires a linear window; entries without
187 are of historic value only.
190 This must match one of the types
200 handles generic VGA functions and should almost always be included.
203 handles basic graphics accelerator initialization on controllers
204 such as the early S3 family of GUI chips.
213 values can all take an extension following a
215 that can be used as a speed-grade
216 or subtype; matching is done without the extension.
218 .B ramdac=stg1702-135
219 indicates the STG1702 RAMDAC has a maximum clock frequency of 135MHz,
221 .B clock=ics2494a-324
222 indicates that the frequency table numbered
224 should be used for the ICS2494A clock generator.
226 The functions internal to
234 values will be called in the order given for initialization.
235 Sometimes the clock should be set before the RAMDAC is initialized,
236 for example, depending on the components used.
239 will always be first and,
244 The entries in the second part of
246 have as attribute the name of a monitor type
247 and the value is conventionally a resolution in the form
253 are numbers representing width and height in pixels.
254 The monitor type (i.e. entry)
256 has special properties, described below and shown in the examples.
257 The remainder of the entry contains timing information for
258 the desired resolution.
259 Within one of these entries the following attributes are
264 the video dot-clock frequency in MHz required for this resolution.
265 The value 25.175 is known internally to
267 as the baseline VGA clock rate.
269 the default video dot-clock frequency in MHz used
270 for this resolution when no
271 memory bandwidth is specified for the card
274 cannot determine the maximum clock frequency of the card.
277 start horizontal blanking, in character clocks.
280 end horizontal blanking, in character clocks.
283 horizontal total, in character clocks.
286 vertical refresh start, in character clocks.
289 vertical refresh end, in character clocks.
292 vertical total, in character clocks.
295 horizontal sync polarity.
302 vertical sync polarity.
315 continue, replacing the
317 line by the contents of the entry whose attribute is given as
321 continue, replacing this
323 line by the contents of the previously defined
325 monitor type with matching
328 Any non-zero attributes already set will not be overwritten.
329 This is used to save duplication of timing information.
332 is not parsed, it is only used as a string
333 to identify the previous
349 scope of this manual page.
356 entry for a laptop with a Chips and Technology 65550
359 ctlr # NEC Versa 6030X/6200MX
360 0xC0090="CHIPS 65550 PCI & VL Accelerated VGA BIOS"
362 ctlr=hiqvideo linear=1
365 A more complex entry. Note the extensions on the
370 attributes. The order here is important: the RAMDAC clock input must be
371 initialized before the RAMDAC itself. The clock frequency is selected by
376 ctlr # Hercules Dynamite Power
377 0xC0076="Tseng Laboratories, Inc. 03/04/94 V8.00N"
383 Monitor entry for type
385 (the default monitor type used by
387 and resolution 640x480x[18].
389 include = 640x480@60Hz # 60Hz, 31.5KHz
391 shb=664 ehb=760 ht=800
392 vrs=491 vre=493 vt=525
394 vga = 640x480 # 60Hz, 31.5KHz
397 Entries for multisync monitors with video bandwidth up to 65MHz.
400 # Multisync monitors with video bandwidth up to 65MHz.
402 multisync65 = 1024x768 # 60Hz, 48.4KHz
403 include=1024x768@60Hz
404 multisync65 = 1024x768i # 87Hz, 35.5KHz (interlaced)
405 include=1024x768i@87Hz
409 Note how this builds on the existing
424 Programming Guide to the EGA, VGA and Super VGA Cards,
427 The database should provide a way
429 as well as BIOS memory to identify cards.
430 .SH "ADDING A NEW MONITOR"
431 Adding a new monitor is usually fairly straightforward, as most modern monitors
432 are multisync and the only interesting parameter is the
433 maximum video bandwidth.
434 Once the timing parameters are worked out for a particular maximum
435 video bandwidth as in the example above, an entry for a new monitor
436 with that limit is simply
441 # Allowable frequency range: 28-50KHz
443 # Allowable frequency range: 50-87Hz
448 Even this is not necessary, as the monitor type could simply be
451 .SH "ADDING A NEW VGA CONTROLLER"
452 While the use of this database formalizes the steps needed to
453 program a VGA controller,
454 unless you are lucky and all the important components on
455 a new VGA controller card are interconnected in the same way as an
456 existing entry, adding a new entry requires adding new internal
459 Fortunately, the unit of variety
460 has, for the most part, shifted from
461 individual components to entire
463 Thus in lucky cases all that is necessary
464 is the addition of another
466 line to the entry for the controller.
467 This is particularly true in the case
468 of the ATI Mach 64 and the S3 Virge.
470 If you need to actually add support
471 for a controller with a different chipset,
472 you will need the data sheets for the VGA controller
473 as well as any RAMDAC or clock generator
474 (these are commonly integrated into the controller).
475 You will also need to know how these components interact.
476 For example, a common combination is an S3 86C928 VGA chip with
477 an ICD2061A clock generator. The ICD2061A is usually loaded by clocking
478 a serial bit-stream out of one of the 86C928 registers.
479 Similarly, the RAMDAC may have an internal clock-doubler and/or
480 pixel-multiplexing modes, in which case both the clock generator and
481 VGA chip must be programmed accordingly.
482 Hardware acceleration for rectangle fills
483 and block copies is provided in the kernel;
484 writing code to handle this is necessary
485 to achieve reasonable performance at high
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