3 getfcr, setfcr, getfsr, setfsr \- control floating point
13 void setfcr(ulong fcr)
19 void setfsr(ulong fsr)
21 These routines provide a fairly portable interface to control the
22 rounding and exception characteristics of IEEE 754 floating point units.
23 In effect, they define a pair of pseudo-registers, the floating
24 point control register,
26 which affects rounding, precision, and exceptions, and the
27 floating point status register,
29 which holds the accrued exception bits.
32 routine to retrieve its value, a
35 and macros that identify its contents.
39 contains bits that, when set, halt execution upon exceptions:
41 (enable inexact exceptions),
43 (enable overflow exceptions),
45 (enable underflow exceptions),
47 (enable zero divide exceptions), and
49 (enable invalid operation exceptions).
50 Rounding is controlled by installing in
60 (round towards positive infinity), and
62 (round towards negative infinity).
63 Precision is controlled by installing in
71 (single precision), and
77 holds the accrued exception bits
90 Not all machines support all modes. If the corresponding mask
91 is zero, the machine does not support the rounding or precision modes.
92 On some machines it is not possible to clear selective accrued
96 The exception bits defined here work on all architectures.
97 Where possible, the initial state is equivalent to
100 setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL);
103 However, this may vary between architectures:
104 the default is to provide what the hardware does most efficiently.
106 if you need guaranteed behavior.
107 Also, gradual underflow is not available on some machines.
109 To enable overflow traps and make sure registers are rounded
110 to double precision (for example on the MC68020, where the
111 internal registers are 80 bits long):
115 setfcr((getfcr() & ~FPPMASK) | FPPDBL | FPOVFL);
119 .B /sys/src/libc/$objtype/getfcr.s