2 // Issue #34427: On ARM, the code in `foo` at one time was generating
3 // a machine code instruction of the form: `str r0, [r0, rN]!` (for
4 // some N), which is not legal because the source register and base
5 // register cannot be identical in the preindexed form signalled by
8 // See LLVM bug: https://llvm.org/bugs/show_bug.cgi?id=28809
11 fn foo(n: usize) -> Vec<Option<(*mut (), &'static ())>> {
12 (0..n).map(|_| None).collect()
16 let _ = (foo(10), foo(32));