1 // assembly-output: ptx-linker
2 // compile-flags: --crate-type cdylib
5 #![feature(abi_ptx, core_intrinsics)]
8 use core::intrinsics::*;
10 // aux-build: breakpoint-panic-handler.rs
11 extern crate breakpoint_panic_handler;
13 // Currently, LLVM NVPTX backend can only emit atomic instructions with
14 // `relaxed` (PTX default) ordering. But it's also useful to make sure
15 // the backend won't fail with other orders. Apparently, the backend
16 // doesn't support fences as well. As a workaround `llvm.nvvm.membar.*`
17 // could work, and perhaps on the long run, all the atomic operations
18 // should rather be provided by `core::arch::nvptx`.
20 // Also, PTX ISA doesn't have atomic `load`, `store` and `nand`.
22 // FIXME(denzp): add tests for `core::sync::atomic::*`.
25 pub unsafe extern "ptx-kernel" fn atomics_kernel(a: *mut u32) {
26 // CHECK: atom.global.and.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
27 // CHECK: atom.global.and.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
29 atomic_and_relaxed(a, 1);
31 // CHECK: atom.global.cas.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1, 2;
32 // CHECK: atom.global.cas.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1, 2;
33 atomic_cxchg(a, 1, 2);
34 atomic_cxchg_relaxed(a, 1, 2);
36 // CHECK: atom.global.max.s32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
37 // CHECK: atom.global.max.s32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
39 atomic_max_relaxed(a, 1);
41 // CHECK: atom.global.min.s32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
42 // CHECK: atom.global.min.s32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
44 atomic_min_relaxed(a, 1);
46 // CHECK: atom.global.or.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
47 // CHECK: atom.global.or.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
49 atomic_or_relaxed(a, 1);
51 // CHECK: atom.global.max.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
52 // CHECK: atom.global.max.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
54 atomic_umax_relaxed(a, 1);
56 // CHECK: atom.global.min.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
57 // CHECK: atom.global.min.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
59 atomic_umin_relaxed(a, 1);
61 // CHECK: atom.global.add.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
62 // CHECK: atom.global.add.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
64 atomic_xadd_relaxed(a, 1);
66 // CHECK: atom.global.exch.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
67 // CHECK: atom.global.exch.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
69 atomic_xchg_relaxed(a, 1);
71 // CHECK: atom.global.xor.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
72 // CHECK: atom.global.xor.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
74 atomic_xor_relaxed(a, 1);
76 // CHECK: mov.u32 %[[sub_0_arg:r[0-9]+]], 100;
77 // CHECK: neg.s32 temp, %[[sub_0_arg]];
78 // CHECK: atom.global.add.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], temp;
81 // CHECK: mov.u32 %[[sub_1_arg:r[0-9]+]], 200;
82 // CHECK: neg.s32 temp, %[[sub_1_arg]];
83 // CHECK: atom.global.add.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], temp;
84 atomic_xsub_relaxed(a, 200);