src/librustc_trans/llvm_util.rs

   1 // Copyright 2017 The Rust Project Developers. See the COPYRIGHT
   2 // file at the top-level directory of this distribution and at
   3 // http://rust-lang.org/COPYRIGHT.
   4 //
   5 // Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
   6 // http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
   7 // <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
   8 // option. This file may not be copied, modified, or distributed
   9 // except according to those terms.
  10
  11 use syntax_pos::symbol::Symbol;
  12 use back::write::create_target_machine;
  13 use llvm;
  14 use rustc::session::Session;
  15 use rustc::session::config::PrintRequest;
  16 use libc::{c_int, c_char};
  17 use std::ffi::CString;
  18
  19 use std::sync::atomic::{AtomicBool, Ordering};
  20 use std::sync::Once;
  21
  22 pub fn init(sess: &Session) {
  23     unsafe {
  24         // Before we touch LLVM, make sure that multithreading is enabled.
  25         static POISONED: AtomicBool = AtomicBool::new(false);
  26         static INIT: Once = Once::new();
  27         INIT.call_once(|| {
  28             if llvm::LLVMStartMultithreaded() != 1 {
  29                 // use an extra bool to make sure that all future usage of LLVM
  30                 // cannot proceed despite the Once not running more than once.
  31                 POISONED.store(true, Ordering::SeqCst);
  32             }
  33
  34             configure_llvm(sess);
  35         });
  36
  37         if POISONED.load(Ordering::SeqCst) {
  38             bug!("couldn't enable multi-threaded LLVM");
  39         }
  40     }
  41 }
  42
  43 unsafe fn configure_llvm(sess: &Session) {
  44     let mut llvm_c_strs = Vec::new();
  45     let mut llvm_args = Vec::new();
  46
  47     {
  48         let mut add = |arg: &str| {
  49             let s = CString::new(arg).unwrap();
  50             llvm_args.push(s.as_ptr());
  51             llvm_c_strs.push(s);
  52         };
  53         add("rustc"); // fake program name
  54         if sess.time_llvm_passes() { add("-time-passes"); }
  55         if sess.print_llvm_passes() { add("-debug-pass=Structure"); }
  56
  57         for arg in &sess.opts.cg.llvm_args {
  58             add(&(*arg));
  59         }
  60     }
  61
  62     llvm::LLVMInitializePasses();
  63
  64     llvm::initialize_available_targets();
  65
  66     llvm::LLVMRustSetLLVMOptions(llvm_args.len() as c_int,
  67                                  llvm_args.as_ptr());
  68 }
  69
  70 // WARNING: the features must be known to LLVM or the feature
  71 // detection code will walk past the end of the feature array,
  72 // leading to crashes.
  73
  74 const ARM_WHITELIST: &'static [&'static str] = &["neon\0", "vfp2\0", "vfp3\0", "vfp4\0"];
  75
  76 const AARCH64_WHITELIST: &'static [&'static str] = &["neon\0"];
  77
  78 const X86_WHITELIST: &'static [&'static str] = &["avx\0", "avx2\0", "bmi\0", "bmi2\0", "sse\0",
  79                                                  "sse2\0", "sse3\0", "sse4.1\0", "sse4.2\0",
  80                                                  "ssse3\0", "tbm\0", "lzcnt\0", "popcnt\0",
  81                                                  "sse4a\0", "rdrnd\0", "rdseed\0", "fma\0",
  82                                                  "xsave\0", "xsaveopt\0", "xsavec\0",
  83                                                  "xsaves\0",
  84                                                  "avx512bw\0", "avx512cd\0",
  85                                                  "avx512dq\0", "avx512er\0",
  86                                                  "avx512f\0", "avx512ifma\0",
  87                                                  "avx512pf\0", "avx512vbmi\0",
  88                                                  "avx512vl\0", "avx512vpopcntdq\0", "mmx\0"];
  89
  90 const HEXAGON_WHITELIST: &'static [&'static str] = &["hvx\0", "hvx-double\0"];
  91
  92 const POWERPC_WHITELIST: &'static [&'static str] = &["altivec\0",
  93                                                      "power8-altivec\0", "power9-altivec\0",
  94                                                      "power8-vector\0", "power9-vector\0",
  95                                                      "vsx\0"];
  96
  97 const MIPS_WHITELIST: &'static [&'static str] = &["msa\0"];
  98
  99 pub fn target_features(sess: &Session) -> Vec<Symbol> {
 100     let target_machine = create_target_machine(sess);
 101
 102     let whitelist = match &*sess.target.target.arch {
 103         "arm" => ARM_WHITELIST,
 104         "aarch64" => AARCH64_WHITELIST,
 105         "x86" | "x86_64" => X86_WHITELIST,
 106         "hexagon" => HEXAGON_WHITELIST,
 107         "mips" | "mips64" => MIPS_WHITELIST,
 108         "powerpc" | "powerpc64" => POWERPC_WHITELIST,
 109         _ => &[],
 110     };
 111
 112     let mut features = Vec::new();
 113     for feat in whitelist {
 114         assert_eq!(feat.chars().last(), Some('\0'));
 115         if unsafe { llvm::LLVMRustHasFeature(target_machine, feat.as_ptr() as *const c_char) } {
 116             features.push(Symbol::intern(&feat[..feat.len() - 1]));
 117         }
 118     }
 119     features
 120 }
 121
 122 pub fn print_version() {
 123     unsafe {
 124         println!("LLVM version: {}.{}",
 125                  llvm::LLVMRustVersionMajor(), llvm::LLVMRustVersionMinor());
 126     }
 127 }
 128
 129 pub fn print_passes() {
 130     unsafe { llvm::LLVMRustPrintPasses(); }
 131 }
 132
 133 pub fn print(req: PrintRequest, sess: &Session) {
 134     let tm = create_target_machine(sess);
 135     unsafe {
 136         match req {
 137             PrintRequest::TargetCPUs => llvm::LLVMRustPrintTargetCPUs(tm),
 138             PrintRequest::TargetFeatures => llvm::LLVMRustPrintTargetFeatures(tm),
 139             _ => bug!("rustc_trans can't handle print request: {:?}", req),
 140         }
 141     }
 142 }
 143
 144 pub fn enable_llvm_debug() {
 145     unsafe { llvm::LLVMRustSetDebug(1); }
 146 }